JPS6315066U

JPS6315066U -

Info

Publication number: JPS6315066U
Application number: JP10716186U
Authority: JP
Priority date: 1986-07-11
Filing date: 1986-07-11
Publication date: 1988-02-01

Description

[Brief explanation of the drawing]

第１図は本考案を説明するための断面図、第２
図は従来例を説明するための断面図である。２１はＰ型半導体基板、２５ａは第１の島領域
、２５ｂは第２の島領域、２５ｃは第３の島領域
、２５ｄは第４の島領域、３２は第１領域、３３
は第２領域、３５，３６…４２は電極である。 Figure 1 is a sectional view for explaining the present invention, Figure 2 is a sectional view for explaining the present invention.
The figure is a sectional view for explaining a conventional example. 21 is a P-type semiconductor substrate, 25a is a first island region, 25b is a second island region, 25c is a third island region, 25d is a fourth island region, 32 is a first region, 33
is the second region, and 35, 36, . . . , 42 are electrodes.

Claims

[Scope of utility model registration request]

It includes a plurality of island regions separated into island shapes, an output transistor formed in the first island region, and another transistor formed in the second island region, and the output transistor and the other transistor are formed in the second island region. In a semiconductor integrated circuit in which a parasitic transistor is generated between the transistor and the collector of the parasitic transistor, a third island region biased to a high potential is provided between the first island region and the second island region. The current is formed so that all of the current is supplied from the third island region, and the first island region and the third island region
A semiconductor integrated circuit characterized in that hFE of the parasitic transistor is reduced by providing a floating fourth island region between the island region and the island region.