JPH0467356U - - Google Patents
Info
- Publication number
- JPH0467356U JPH0467356U JP11093590U JP11093590U JPH0467356U JP H0467356 U JPH0467356 U JP H0467356U JP 11093590 U JP11093590 U JP 11093590U JP 11093590 U JP11093590 U JP 11093590U JP H0467356 U JPH0467356 U JP H0467356U
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- region
- type
- integrated circuit
- back surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 4
- 239000000956 alloy Substances 0.000 claims 1
- 229910045601 alloy Inorganic materials 0.000 claims 1
- 229910001020 Au alloy Inorganic materials 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
Landscapes
- Bipolar Integrated Circuits (AREA)
Description
第１図及び第２図は本考案の第１及び第２の実
施例の半導体チツプの断面図、第３図は従来例を
示す半導体チツプの断面図である。
１……Ｐ型Ｓｉ基板、２……Ｎ型領域、３……
酸化膜、４……Ｐ型領域、５……Ｎ＋型領域、６
……電極、７……埋込Ｎ＋型領域、８，８Ａ……
埋込Ｐ＋型領域、９……Ａｕ合金層、１０……選
択エツチング領域。
1 and 2 are cross-sectional views of semiconductor chips according to first and second embodiments of the present invention, and FIG. 3 is a cross-sectional view of a semiconductor chip showing a conventional example. 1... P-type Si substrate, 2... N-type region, 3...
Oxide film, 4...P type region, 5...N + type region, 6
...Electrode, 7...Embedded N + type region, 8,8A...
Buried P + type region, 9...Au alloy layer, 10...Selective etching region.
Claims (1)
たトランジスタ領域を少くとも有し、かつＳｉ基
板を最低電位として用いる半導体集積回路におい
て、前記トランジスタ領域の周囲の少くとも一部
にＳｉ基板の裏面へ達するＰ＋型領域を設け、か
つこのＰ＋型領域に接続する合金層をＳｉ基板の
裏面に設けたことを特徴とする半導体集積回路。 In a semiconductor integrated circuit that has at least a transistor region in which an NPN transistor is provided on a P-type Si substrate and uses the Si substrate as the lowest potential, at least a part of the periphery of the transistor region has P that reaches the back surface of the Si substrate. A semiconductor integrated circuit characterized in that a + type region is provided and an alloy layer connected to the P + type region is provided on the back surface of a Si substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11093590U JPH0467356U (en) | 1990-10-23 | 1990-10-23 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11093590U JPH0467356U (en) | 1990-10-23 | 1990-10-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0467356U true JPH0467356U (en) | 1992-06-15 |
Family
ID=31858339
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11093590U Pending JPH0467356U (en) | 1990-10-23 | 1990-10-23 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0467356U (en) |
-
1990
- 1990-10-23 JP JP11093590U patent/JPH0467356U/ja active Pending
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