JPH0356155U - - Google Patents
Info
- Publication number
- JPH0356155U JPH0356155U JP11727089U JP11727089U JPH0356155U JP H0356155 U JPH0356155 U JP H0356155U JP 11727089 U JP11727089 U JP 11727089U JP 11727089 U JP11727089 U JP 11727089U JP H0356155 U JPH0356155 U JP H0356155U
- Authority
- JP
- Japan
- Prior art keywords
- metal wiring
- power supply
- conductivity type
- supply terminal
- diffusion layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 5
- 238000009792 diffusion process Methods 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims 3
- 239000003990 capacitor Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Description
第１図は本考案の一実施例の断面模式図、第２
図は第１図に示す実施例に形成されるコンデンサ
の等価回路図、第３図は従来の半導体装置の一例
の断面模式図、第４図は第３図に示す半導体装置
に形成されるコンデンサの等価回路図である。
１……Ｎ型シリコン基板、２……Ｐ型拡散層、
３，４……酸化膜、５，６……配線。
Figure 1 is a schematic cross-sectional view of one embodiment of the present invention;
The figure is an equivalent circuit diagram of a capacitor formed in the embodiment shown in Fig. 1, Fig. 3 is a schematic cross-sectional view of an example of a conventional semiconductor device, and Fig. 4 is a capacitor formed in the semiconductor device shown in Fig. 3. FIG. 1... N-type silicon substrate, 2... P-type diffusion layer,
3, 4... Oxide film, 5, 6... Wiring.
Claims (1)
に絶縁膜を介して金属配線が設けられている半導
体装置において、前記一導電型拡散層と金属配線
との間の絶縁層内を通りかつ一端が前記半導体チ
ツプに設けられている最高電位電源端子または最
低電位電源端子に接続されていることを特徴とす
る半導体装置。 In a semiconductor device in which a metal wiring is provided on a diffusion layer of one conductivity type formed on a semiconductor chip via an insulating film, a metal wiring that passes through the insulating layer between the diffusion layer of one conductivity type and the metal wiring and has one end. is connected to a highest potential power supply terminal or a lowest potential power supply terminal provided on the semiconductor chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11727089U JPH0356155U (en) | 1989-10-04 | 1989-10-04 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11727089U JPH0356155U (en) | 1989-10-04 | 1989-10-04 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0356155U true JPH0356155U (en) | 1991-05-30 |
Family
ID=31665491
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11727089U Pending JPH0356155U (en) | 1989-10-04 | 1989-10-04 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0356155U (en) |
-
1989
- 1989-10-04 JP JP11727089U patent/JPH0356155U/ja active Pending
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