JPH02281745A - Gate array device - Google Patents

Abstract

PURPOSE:To enable formation of both an interface of different potential signals and an interface of the same potential signal and attainment of high integration by one and the same gate array device by a construction wherein N-type diffusion layers (NWEL) of IO cell groups arranged in the shape of an array in the gate array device are made independent discretely by each IO cell. CONSTITUTION:NWELs 8 of IO cells 10 are so designed that they can be made independent discretely by each IO cell 10 when the IO cells 10 are arranged in the shape of an array, and therefore the NWELs 8 can correspond to both potentials of VDD1 and VDD2. All input-output circuits can be constructed of the 10 cells and, in addition, they can be constructed of any IO cells. By one and the same gate array device, according to this constitution, both an interface of different potential signals and an interface of the same potential signal can be formed, the interfaces can be constructed of arbitrary IO cells and high integration can be attained.

Description

[Detailed Description of the Invention] [Industrial Application Field 1] The present invention enables an input/output circuit group capable of interfacing different potential signals and an input/output circuit group capable of interfacing same potential signals to be configured by wiring layers. The present invention relates to a gate array device having 10 cells.

[Prior Art] Regarding the interface between the internal circuit composed of the basic cell group of the gate array device and other devices outside the gate array device, the power supply potential of the internal circuit composed of the basic cell group of the gate array device is set to VDD. I, the power supply potential of other devices outside the gate array device is set to the VDDI
When VDD2, which has a higher potential, or the power supply potential of another device outside the gate array device is VDDl, which has the same potential as VDD1, the different potential signal VDD2
An example of an input circuit and an example of an output circuit that can interface with the same potential signals VDD 1 and VDD I are shown in FIGS. 1 and 2, respectively. They are shown in FIGS. 3 and 4, respectively.

In FIGS. 1, 2, 3, and 4, the dashed dotted line 1 indicates the boundary between the outside and the inside of the gate array device, and the dashed dotted line 2 indicates the input/output circuit group and basic cells inside the gate array device. Indicates the boundary between groups.

3 and 5 are P-type MO3FETs, 4 and 6 are N-type MO3FETs.
SFET 7 indicates a voltage conversion circuit that converts DDl into VDD2+.

Conventionally, one of the input circuit examples and output circuit examples shown in FIGS. 1 and 2 and the input circuit examples and output circuit examples shown in FIGS. 3 and 4 in the same gate array device has been used. The structure of the NWEL, which is a basic element that can be configured by wiring layers, is basically a one-stage structure as shown in the shaded area 12 at the top right of FIG. 7, and the basic elements are arranged in an array as shown in FIG. In the arrayed gate array device, the NWELs of the basic element group are all connected between the basic elements, and have a potential of either VDD1 or VDD2.

Furthermore, in the same gate array device, both the input circuit example and output circuit example shown in FIGS. 1 and 2 and the input circuit example and output circuit example shown in FIGS. The structure of the basic element NWEL that can be configured by the VD
NWEL of D l and VDD indicated by the right upward slope part 15
The P-type MOSFETs 3 and 5 shown in FIGS. 1, 2, 3, and 4 are connected to the NWEL of VDD 1 and VDD2.
NWEL 15 respectively, and the first
In a gate array device in which the basic elements are arranged in an array as shown in FIG.
All NWELs of No. 1 were connected between the basic elements, and all NWELs of VDD2 of the basic element group were connected between the basic elements.

[Problems to be Solved by the Invention] However, in the conventional technology shown in FIGS. 7 and 8, the input circuit example and the output circuit example shown in FIGS. 1 and 2 are connected to the same gate array device. There is a problem in that it is not possible to configure both the input circuit example and the output circuit example shown in FIGS. 3 and 4, that is, both an interface for different potential signals and an interface for signals at the same potential.

In addition, in the prior art shown in FIGS. 9 and 10, the NWEL is the NWEL of VDD I and the NWEL of VDD2.
Since it is composed of two stages of WELs, the area of the basic element shown in FIG. 9 becomes large, making it difficult to achieve high integration of the gate array device shown in FIG. 1O. There was also the problem of increased chip cost.

Therefore, the present invention solves the above-mentioned problems.
The same gate array device enables both different potential signal interfaces and same potential signal interfaces,
Another object of the present invention is to provide a gate array device that can be highly integrated.

[Means for Solving the Problems 1] The gate array device of the present invention includes: a) a group of input/output circuits capable of interfacing different potential signals using MOSFETs and a group of input/output circuits capable of interfacing the same potential signals in a wiring layer; I can be configured by
○ In a gate array device for a semiconductor integrated circuit, in which cells are arranged in an array, and basics that allow an internal circuit group to be configured by wiring layers are arranged in an array.
b) a PWE in which the IO cell forms an N-type MOSFET;
C) and that the NWEL of the I○ cell group arranged in an array in the gate array device is individually independent for each I○ cell; Features.

〔Example] The present invention will be described below based on examples.

FIG. 5 shows a ■○ cell of the present invention, and FIG. 6 shows a gate array device of the present invention.

In FIG. 5, the upper right hatched area 8 indicates the P-type MQS of the input/output circuit examples shown in FIGS. 1, 2, 3, and 4.
The NWEL in which the FETs 3 and 5 are formed, and the downward-slanted area 9 to the right is the PWE L in which the N-type MOSFETs 4 and 6 of the input/output circuit examples shown in FIGS. 1, 2, 3, and 4 are formed. It is.

In FIG. 6, 10 is the ■○ cell shown in FIG. 5, and these work cells are arranged in an array.
1 is a basic cell group arranged in an array.

When the I○ cells in FIG. 5 are arranged in an array as shown in FIG. 6, the NWEL 8 of the I○ cells in FIG. 5 is designed so that each I○ cell can be independent. NWEL8 can respond to either VDDl or VDD2 potential.

Therefore, all of the input/output circuit examples shown in FIGS. 1, 2, 3, and 4 can be configured with the I○ cells shown in FIG. It can be composed of any factory cells that can be used.

The case where the NWEL is individually independent in each IQ cell has been described above, but the same can be said about the case where the PWEL is individually independent in each I○ cell.

[Effects of the Invention] As described above, according to the present invention, it is possible to interface both different potential signals and the same potential signal with the same gate array device, and to connect the interface to any The present invention has the advantage of providing a gate array device that can be configured with a high degree of integration, and can be highly integrated, thereby reducing chip cost.

[Brief explanation of drawings]

Figures 1 and 2 are an input circuit diagram, an example diagram of an output circuit, and Figure 3, respectively, which enable interfacing of different potential signals.
FIG. 4 is a side view of an input circuit and an example of an output circuit that enable interface of the same potential signals, FIG. 5 is a configuration diagram of an IO cell of the present invention, and FIG. 6 is a configuration diagram of a gate array device of the present invention. , FIG. 7, and FIG. 9 are configuration diagrams of conventional I○ cells. FIG. 8 and FIG. 1O are configuration diagrams of conventional gate array devices. l... Boundary line between the outside and the inside of the gate array device 2... Boundary line between the input/output circuit group and the basic cell group inside the gate array device 3.5 P-type MO3FET 4.6 N-type MO3FET 7 ... Voltage conversion circuit 8.12.14.15 ... NWEL 9 ... PWE L 10.13.16 ... IQ cell 11 ... Basic cell group Same in Figures 1 to 10 Structures are given the same reference numerals. Applicant: Seiko Epson Co., Ltd. Agent Patent Attorney Kizobe Suzuki (and 1 other person) No. 1? Yasumanbo No. δ Fig. Fig. No.”

Claims (1)

[Claims] a) Insulated gate field effect transistor (hereinafter referred to as MOSFE)
An array of basic elements (hereinafter abbreviated as 10 cells) that can configure an input/output circuit group that can interface different potential signals using a wiring layer (abbreviated as T) and an input/output circuit group that can interface the same potential signal. arranged in a shape, and
In a gate array device for a semiconductor integrated circuit in which basic elements (hereinafter abbreviated as basic cells) that allow an internal circuit group to be configured by wiring layers are arranged in an array, b) the I@O@ cell is an N-type M@ P-type diffusion layer (hereinafter abbreviated as PWEL) forming O@SFET and P-type M@O@S
c) an N-type diffusion layer (hereinafter abbreviated as NWEL) forming a FET; A gate array device characterized by being individually independent.