JPH0521729A - Semiconductor device - Google Patents

Abstract

PURPOSE:To share a single transistor region among a plurality of MOS transistors. CONSTITUTION:A single transistor region 2 is formed with three diffusion regions 6a to 6c on one of sides interposing a gate electrode 4, while three diffusion regions 6d to 6f are formed on the other side. The gate electrode 4 shows a trapezoidal shape, wherein the diffusion regions 6a to 6c are opposite to the other diffusion regions 6d to 6f with two non-parallel sides interposed therebetween. For example, a transistor size as the diffusion region 6d is an input and the diffusion region 6C is an output is W/L1, while a transistor size as the diffusion region 6d is an input and the diffusion region 6a is an output is W/L2, so that MOS transistors with different transistor sizes sharing the gate electrode with a single transistor region are constituted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device.

[0002]

2. Description of the Related Art A MOS transistor is an element-isolated 1
A gate electrode is formed on one transistor region via a gate oxide film to form one MOS transistor. Therefore, in order to obtain a plurality of MOS transistors having different or equal transistor sizes, that number of transistor regions is required. The A / D converter that obtains a digital output corresponding to the analog input has a sample hold circuit, and holds the analog input data while converting the analog signal into the digital signal. In a MOS transistor, the gate electrode is usually a single-layer polycrystalline silicon gate electrode, and a double-layer polycrystalline silicon gate electrode is provided, and neither of these two gate electrodes serves as an input gate. PROM and EPR
OM uses a two-layer gate electrode, one of which is
The layer is a floating gate electrode, not an input gate electrode.

[0003]

When forming a plurality of MOS transistors having different transistor sizes,
Even if the transistor sizes are the same, multiple MOS
If a transistor is to be obtained, that number of transistor regions is required, which is an obstacle to reducing the chip area. Therefore, a first object of the present invention is to reduce the chip area by making one transistor region common to a plurality of MOS transistors.

Since the conventional A / D converter uses a sample and hold circuit, it takes time to convert an analog signal into a digital signal, and it is impossible to instantaneously and sequentially convert an analog input. In addition, the provision of the sample and hold circuit complicates the circuit and hinders an increase in the degree of integration. Therefore, a second object of the present invention is to instantaneously and sequentially convert an analog input into a digital output and simplify the circuit to improve the degree of integration. A third object of the present invention is to obtain a MOS transistor capable of obtaining a plurality of outputs in one transistor area.

[0005]

In order to achieve the first object of making one transistor region common to a plurality of MOS transistors, the present invention forms a gate electrode on a semiconductor substrate via a gate oxide film. At least one diffusion region is formed on one side of the gate electrode in the transistor formation region including the lower side region of the gate electrode, and at least two diffusion regions are formed on the other side of the gate electrode. A diffusion region is formed to make this gate electrode common 2
The above MOS transistors are formed.

In order to achieve the second object of instantaneously and sequentially converting an analog input into a digital output and simplifying the circuit, in the A / D converter of the present invention, a gate oxide film is formed in the N-type region of the semiconductor substrate. A gate electrode is formed through the gate electrode, and at least one P-type diffusion region is formed on one side of the gate electrode in the transistor formation region including the lower region of the gate electrode. On the other side, at least two P-type diffusion regions are formed and two or more PMOS transistors having a common gate electrode are formed, and a gate electrode is formed in the P-type region of the same semiconductor substrate via a gate oxide film. , At least one N-type diffusion region is formed on one side of the transistor formation region including the lower region of the gate electrode, and the gate electrode is sandwiched between the transistor formation region and the transistor formation region. A plurality of inverters having different thresholds are formed from two or more NMOS transistors having a common gate electrode, in which at least two N-type diffusion regions are formed on one side, and the plurality of inverters are provided. A combination circuit is provided in which the gate electrodes of the above are used as analog inputs and the outputs of these plurality of inverters are used as digital outputs.

In order to achieve the third object of obtaining a plurality of outputs in one transistor region, in the present invention, a first gate electrode is formed on one transistor region of a semiconductor substrate via a gate oxide film, A second gate electrode, which is insulated from the first gate electrode and is orthogonal to the first gate electrode, is formed on the transistor region through the gate oxide film, and four diffusion regions are formed in one transistor region. There is.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1A shows an embodiment corresponding to the invention of claim 1 in which a plurality of MOS transistors having a common gate electrode in one transistor region are realized.
A polycrystalline silicon gate electrode 4 is formed on one transistor region 2 separated by a field oxide film via a gate oxide film. In the transistor region 2, three diffusion regions 6a to 6c are formed on one side of the gate electrode 4 and three diffusion regions 6d to 6f are formed on the other side of the gate electrode 4. Has been done. Each diffusion region 6a-
6f is provided with contacts 8a to 8f, which are connected to wirings via an interlayer insulating film. Gate electrode 4
Has a trapezoidal shape, and one diffusion region 6a to 6c and the other diffusion region 6d to 6f face each other across two non-parallel sides.

In the MOS transistor of FIG. 1A, an input voltage is applied to the gate electrode 4 and one of the diffusion regions 6a to 6c on one side is input while the channel is formed, and the diffusion region on the other side is input. By outputting one of 6d to 6f, 15 types of MOS transistors having different transistor sizes can be realized. It is the same even if the input and output are reversed. Now, for example, the diffusion region 6d is input, the diffusion region 6c
The case where 6 and 6a are output respectively will be described.
When (B) uses the diffusion region 6c as an output, (C) shows 6a.
It is a schematic diagram at the time of making into an output. Since the transistor size in the case of (B) is W / L ₁ and the transistor size in the case of (C) is W / L ₂ , MOS transistors having different transistor sizes with a common gate electrode in one transistor region. Has been configured.

FIG. 2 corresponds to claim 2, and the present invention is A / D.
It shows an embodiment applied to a converter. (A)
Then, for example, a polycrystalline silicon gate electrode 12 is formed in one transistor region 10 formed in an N-type well of a P-type silicon substrate via a gate oxide film, and one side of the gate electrode 12 is formed in the transistor region 10. One P-type diffusion region 14a is formed on one side, and three P-type diffusion regions 14a on the other side.
The type diffusion regions 14b to 14d are formed, and a plurality of PMOS transistors are formed in one transistor region 10. Further, in order to form an NMOS transistor on the same silicon substrate, a polycrystalline silicon gate electrode 18 is formed on the transistor region 16 via a gate oxide film, and the transistor region 16 has a gate electrode 18 on one side thereof. One N-type diffusion region 20a and three N-type diffusion regions 20b to 20d are formed on the other side, and a plurality of NMOS transistors are formed in one transistor region 16.

In the PMOS transistor, the diffusion region 14a
Is connected to the high voltage side power supply Vcc to serve as a source, and the diffusion regions 14b to 14d serve as drains to form three PMOS transistors having different transistor sizes. And the three diffusion regions 20b-
3d with different transistor size with 20d as drain
Individual NMOS transistors are configured. Three PMOs formed between diffusion regions 14a and 14b-14d
In the S transistor, the transistor size W / L is the largest using the diffusion region 14b, and then the diffusion region 1
4c and the diffusion region 14d are the smallest. In the three NMOS transistors, the transistor size W / L is the largest when the diffusion region 20b is used, is the largest when the diffusion region 20c is used next, and is the smallest when the diffusion region 20d is used.

By connecting the wires as shown in FIG. 2A, three inverters 2 are provided as shown in the equivalent circuit of FIG. 2B.
2a to 22c are formed, and the threshold voltages thereof are higher in the order of the inverters 22a, 22b, 22c.
The three outputs a, b, c of the inverter are input to the combinational circuit 24 formed by the exclusive OR circuit (EX / OR) together with the power supply Vcc level and the ground level to obtain digital outputs A, B, C, D. Inverters 22a-22c
Of the threshold voltage of Vth ₁ to
If Vth ₃ is set, when the gate voltage Vg of the input signal is increased, the outputs A to D change as shown in the truth table of Table 1 by the gate voltages in the regions of (C) to.
That is, analog changes in the input voltage Vg are instantaneously and sequentially converted into digital signals A to D. In Table 1, "0" corresponds to a low level signal, and "1" corresponds to a high level signal.

[0013]

FIG. 3 shows an embodiment in which the present invention is applied to a MOS transistor having a two-layer polycrystalline silicon gate electrode. In the transistor region 30 surrounded by the field oxide film on the silicon substrate, a first-layer polycrystalline silicon gate electrode 32 is formed via the gate oxide film, and in the transistor region 30 via the gate oxide film, the gate electrode is formed. Three
A second-layer polycrystalline silicon gate electrode 34 in a direction orthogonal to the gate electrode 32 is formed on the second layer 2 with an interlayer insulating film interposed therebetween. A field oxide film 36 is provided in a region below the intersection of the two gate electrodes 32 and 34.
The transistor region 30 is divided into four regions by the two gate electrodes 32 and 34, and an impurity is introduced into each region to serve as a source / drain. The four areas are represented by symbols d, e, f, and g, respectively. The first-layer gate electrode is represented by the symbol b, and the second-layer is represented by the symbol c.

The operation of this MOS transistor will be described. One of the four diffusion regions d to g is input, and the other three are output. Any diffusion area may be input, but now the diffusion area d is input. This MOS
Table 2 shows a truth table when the transistor is an N channel.

[0016]

Table 3 shows a truth table when the MOS transistor is a P channel.

[0018]

In Tables 2 and 3, L, H, and Z represent logical values, which mean "0", "1", and "Hi-Z (undefined)" states, respectively. According to FIG. 3, a 1-input / 3-output MOS transistor is realized.

[0020]

According to the invention of claim 1, two or more MOS transistors having different transistor sizes or the same transistor size can be realized in one transistor region, and a desired circuit can be formed in a small area. be able to. According to the invention of claim 2, the analog input is directly supplied as the gate voltage of the MOS transistor, and a digital output is obtained by a plurality of inverters having different threshold voltages and a combination circuit. A / D converter can be realized. Also,
Since the structure is simple, the degree of integration can be improved. According to the invention of claim 3, a switching circuit or the like having a plurality of outputs in one transistor region can be realized.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment, (A) is a schematic plan view, and (B) and (C) are schematic plan views showing an example of an operation.

2A and 2B are diagrams showing a second embodiment, in which FIG. 2A is a schematic plan view partially showing a circuit diagram, FIG. 2B is an equivalent circuit diagram, and FIG.
FIG. 7 is a diagram showing an operation.

FIG. 3 is a schematic plan view showing a third embodiment.

[Explanation of symbols]

2,10,16,30 Transistor area 4,12,18,32,34 Gate electrode

Claims (3)

[Claims] 1. A gate electrode is formed on a semiconductor substrate via a gate oxide film, and a transistor forming region including a region below the gate electrode has at least one diffusion on one side of the gate electrode. A semiconductor device in which a region is formed, at least two diffusion regions are formed on the other side of the gate electrode, and two or more MOS transistors having the gate electrode in common are formed. 2. A gate electrode is formed in an N-type region of a semiconductor substrate via a gate oxide film, and a transistor forming region including a region below the gate electrode has at least one on one side across the gate electrode. Two P-type diffusion regions are formed, and at least two P-type diffusion regions are formed on the other side of the gate electrode.
A gate electrode is formed in the P-type region of the same semiconductor substrate via the gate oxide film as the PMOS transistor described above, and at least one side of the gate electrode is sandwiched in the transistor formation region including the region below the gate electrode. One N-type diffusion region is formed, and at least two N-type diffusion regions are formed on the other side of the gate electrode, and two or more NMOS transistors having a common gate electrode,
A plurality of inverters having different thresholds are configured, and a combination circuit is provided in which the gate electrodes of the plurality of inverters are analog inputs and the outputs of the plurality of inverters are digital outputs. / D converter. 3. A first gate electrode is formed on one transistor region of a semiconductor substrate via a gate oxide film,
A second gate electrode, which is insulated from the first gate electrode and is orthogonal to the first gate electrode, is formed on the transistor region via a gate oxide film, and four diffusion regions are formed in one transistor region. Semiconductor device.