JPS6195605A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To set optionally the width of a logic threshold voltage by providing an N-channel and a P-channel MOSFET in parallel with a CMOS inverter circuit. CONSTITUTION:An input signal fed from an external terminal IN is inputted to the CMOS inverter IV0 comprising the P-channel MOSFETQ1 and the N- channel MOSFETQ2. An output of the inverter IV0 is fed sequentially to CMOS inverters IV1, IV2 of the similar constitution. Further, the output of the inverter IV1 is given to gates of P-channel MOSFETs Q3-Q5 and N-channel MOSFETs Q6-Q8 connected in parallel with the FETs Q1, Q2. A connecting point between the FETs Q5 and Q6 is fed back to the input of the inverter IV1. In short- circuiting the FETs Q3-Q8, the hysteresis width of the Schmitt output from the inverter IV2 is set.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor integrated circuit device, and, for example, to a technique effective for use in a CMO3 integrated circuit incorporating a Schmitt trigger circuit.

[Background technology]

As a Schmitt trigger circuit constituted by an 0MO3 (complementary MO3) circuit, a circuit as shown in FIG. 4 is known from Japanese Patent Laid-Open No. 58-77317. As described in the same publication, this Schmitt trigger circuit has a problem in that the logic threshold voltage having hysteresis characteristics cannot have a large width. The reason for this is that the P-channel MOS in diode form
Threshold voltage of FETQ20 P-channel MOS
This is because the width of the logic threshold voltage is set by changing the operating voltage of the CMOS inverter circuit consisting of FETQ22 and N-channel MOSFETQ23.

1 Furthermore, since the threshold voltage of the MOSFET Q20 has relatively large variations due to its manufacturing process, the hysteresis characteristics themselves have relatively large variations.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device equipped with a scissor trigger circuit that can arbitrarily set the width of a logic threshold voltage within a relatively wide range.

Another object of the present invention is to provide a semiconductor integrated circuit device equipped with a Schmitt trigger circuit having hysteresis characteristics that are not affected by manufacturing processes.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, an inverter circuit receives the output signal of the CMOS inverter circuit and forms an inverted signal, and the inverter circuit receives the output signal of the inverter circuit and is arranged in parallel with an N-channel MOSFET and/or a P-channel MOSFET forming the CMOS inverter circuit. N channel MO
By providing an S FET and/or a P-channel MOSFET, the input/output transfer characteristics of the CMOS inverter circuit are converted according to the input signal level, thereby providing hysteresis characteristics.

C Embodiment 1] FIG. 1 shows a circuit diagram of an embodiment of a Schmitt trigger circuit according to the present invention. Each circuit element in the same figure is
The well-known OMO3 (complementary MO3) integrated circuit fabrication technique is formed on a single semiconductor substrate, such as single crystal silicon.

In the figure, the MOSFET with a straight line added between the source and drain is a P-channel type (this means that
The same applies to the circuit shown in FIG. 4 above.)

Although not particularly limited, the two integrated circuits are formed on a semiconductor substrate made of single-crystal P-type silicon. N channel MOS
The FET is made of polysilicon, which has a source region, a drain region formed on the surface of the semiconductor substrate, and a thin gate insulating film formed on the surface of the semiconductor substrate between the source region and the drain region. Consists of a gate electrode. The P-channel MOS FET is formed in an N-type well region formed on the surface of the semiconductor substrate.

Thereby, the semiconductor substrate constitutes a common substrate gate for a plurality of N-channel MOSFETs formed thereon. The N-type well region constitutes the base gate of the P-channel MOSFET formed thereon. The substrate gate or N-type well region of the P-channel MOSFET is coupled to the @source terminal Vcc of FIG. Although not particularly limited, a substrate back bias voltage generation circuit (not shown) is provided, and this substrate back bias voltage generation circuit is connected to a power supply terminal V that constitutes an external terminal of the integrated circuit 82.
A negative beta bias voltage to be supplied to the semiconductor substrate is generated in response to a positive power supply voltage such as +5 cm applied between cc and a reference potential terminal or a ground terminal. As a result, a bank bias voltage is applied to the substrate gate of the N-channel MOSFET. As a result, the capacitance value of the parasitic capacitance with the substrate gate is reduced, so that high-speed operation can be achieved.

Although not particularly limited, the shemint trigger of this embodiment ■
The path constitutes an input sofa in a semiconductor integrated circuit device such as a gate array. That is, the input signal supplied from the external input signal is input to the CM configured by the P-channel MOSFET QI and the N-channel MOSFET Q2.
It is supplied to the input terminal of the OS inverter circuit. Note that the external terminal is provided with an electrostatic breakdown prevention circuit, but it is omitted in the figure because it is not directly related to the present invention.

The output of the above CMOS inverter circuit (Ql, Q2) is
It is supplied to the input of a similar CMOS inverter circuit IVI. The output of this CMOS inverter circuit IVI is fed to the input of a similar CMOS inverter circuit IV2, which on the one hand forms an input signal for an internal circuit, not shown. On the other hand, the output of the CMOS inverter circuit IVI is connected to the input stage CMOS inverter circuit (Ql, Q
2) is supplied to the gate of the next MOSFET in order to give desired hysteresis characteristics to the input/output transfer characteristics. Although not particularly limited, P-channel MOSFETs Q3 to Q5 arranged in series are prepared in parallel to the P-channel MOS FETQl constituting the CMOS inverter circuit. In addition, for the N-channel MOSFET Q2 constituting the above CMOS inverter circuit, an N-channel MOSFET Q2 that is also connected in series is
TQ6 to QB are prepared in parallel form. The number of MOS FETs in series is selectively selected by changing the aluminum wiring using a master slicing method.

When the connection shown by the solid line in the figure is selected, the three series MOSFETs Q3 to Q5 and Q6 to Q8 are arranged in parallel with the P channel MOSFET Q1 and the N channel MOSFET Q2, respectively. Furthermore, by selecting one of the connections shown by dotted lines in the figure, the number of MOSFETs can be changed from two to one.

Each of the MOSFETs Q3 to Q8 arranged in series is at least a P-channel MOSFET Q1 and an N-channel MOSFET Q1, which constitute the CMOS inverter circuit.
The channel length is set to be the same as that of OSFETQ2.

The operation of this embodiment circuit will now be described with reference to the input/output transfer characteristics shown in FIG.

Three series MOSFETs Q3 to Q5 as above
When Q6 to Q8 are connected, the width of the hysteresis characteristic is the narrowest as shown by the dotted line in FIG. 2. For example, when the signal Vtn at the input terminal IN is at a low level, P-channel MOS FETQl is turned on and its output Vout is set to high level. As a result, the output of the inverter circuit IV1 is set to low level. therefore,
The three P-channel MOSFETs Q3 to Q5 are turned on, and the three N-channel MOSFETs Q6 to Q
8 is turned off. From this state, the input signal V
At a moment when in changes to high level, the above P channel M
OSFETQ3~Q5 and P-channel MOSFETQI
Since the combined conductance of the N-channel MOSFET Q2 is larger than the conductance of the N-channel MOSFET Q2, which turns on when the level changes to the high level, the MOS
The switching is performed at a higher level than when FETs Q1 to Q3 are not added. And once the above CM
When the output Vout of the OS inverter circuit changes to a low level, the output of the inverter circuit IVI is changed to a high level, so the P-channel MOSFETs Q3 to Q5 are turned off, and the N-channel MOSFETs Q6 to Q8 are turned on. Channel MOSFE
Since the combined conductance of TOIIJ increases, its logic threshold voltage is shifted to the lower level side. That is, when the input signal Vin changes from high level to low level, one P channel M
This is because the logic threshold voltage is determined by the ratio of the conductance of the OS FET Q 1 and the combined conductance of the N-channel MOS FET Q 2 and Q6 to Q8.

By changing the connection using the above master slice method, the number of MOS FETs in the above series type is changed to MOSFETQ4.
．． Q5 and Q6. If there are two such as Ql, the combined conductance in the series circuit will increase, so the above CM
l) Channel MOSF that constitutes one OS inverter circuit
The combined conductance of ETQI and N channel = MOSFET Q2 is further increased. therefore,
In the above signal transmission operation, N-channel MO
P channel M for conductance of SFETQI
OSFETQI and Q4. The ratio of composite conductance due to Q5 can be increased, and similarly P-channel MOSFETQ
N-channel MOSFET for conductance of I
Q2 and Q6. The ratio of composite conductance due to Ql can be increased. This allows two MOSFETs Q4. Q
5 and Q6°Ql, the width of the hysteresis characteristic can be made larger, as shown by the two-dot chain line in FIG. Similarly, by changing the connection using the master slice method, the number of MOSFETs in series can be changed to
When TQ5 and Q6 are combined into one, the conductance becomes even larger, so that the combined conductance of the P-channel MOSFET Q1 and the N-channel MO8FET Q2 constituting the CMOS inverter circuit is maximized. Therefore, in the above signal transmission operation, the ratio of the combined conductance of P-channel MOSFETQI and Q5 to the conductance of N-channel MOSFETQI can be maximized, and similarly, the ratio of the combined conductance of P-channel MOSFETQI (7):M/conductance to N-channel MOSFETQ2 and The ratio of composite conductance due to Q6 can be maximized. This gives 1(11
When MOSFETs Q5 and Q6 are used, the width of the hysteresis characteristic can be maximized, as shown by the solid line in FIG.

As in this example, three series MOSFET'Q3~
If Q5 and Q6 to Q8 are prepared and the number of each is the same, although it is not particularly limited, it is possible to obtain a Schmitt trigger circuit having the above three logic threshold voltage widths.

It goes without saying that a Schmitt trigger circuit with more hysteresis characteristics can be obtained by increasing the number of MOSFETs connected in series.
5. Even when forming Q6 to QB, the number is a combination of different numbers including 0 (added P channel length O
S FET and N-channel MOSFET are both 00
(excluding cases), more hysteresis characteristics can be realized.

Furthermore, by making the channel lengths of the MOSFETs Q1 to Q8 the same, even if variations in conductance occur due to manufacturing variations in the channel lengths of the MOSFETs, the variations will occur at the same ratio in each MOSFET, so it is determined by that ratio. Although there is no variation in the hysteresis characteristic itself, it can be made extremely small. In order to further reduce such variations, the sizes (channel length and channel III) of each of the above MOSFETs may be all made equal, or each of the above MOSFETs Q3 to Q5, Q6 to Q8
may be selectively arranged in parallel using the master slice method.

(Embodiment 2) FIG. 3 shows a circuit diagram of another embodiment of the Schmitt trigger circuit according to the present invention.

Each circuit element in the figure is formed in the same manner as the circuit element in FIG. 1 above.

In this embodiment, the CM that receives a signal from the input terminal IN
The OS inverter circuit is composed of P-channel MOSFETs QI O-Q13 and N-channel MOSFETs Q14-Q17, respectively, prepared in parallel. These MOSFETs are connected to an arbitrary number using a master slice method. Above P
Channel MOSFETQI 0-Ql 3 and N-channel 71/M05FETQI 4-Q17 are each equipped with a CMOS inverter circuit I similar to the embodiment shown in FIG.
■P channel length OS F ETQ1 that receives the output of 1
8 and N channel MOSFET QI 9 are respectively added in parallel configuration. In this embodiment, since the conductance characteristic on the CMOS inverter circuit side is changed by the master slice method, it is possible to provide a hysteresis characteristic similar to the embodiment shown in FIG. 1 above.

In this example, the MOSFEs prepared in the above-mentioned parallel configuration are
TQIO~Q13. As the number of Q14 to Q17 is reduced, the ratio of the conductance of the added MOSFETs Q1B and Q19 to the combined conductance increases, so that the width of the hysteresis characteristic can be increased.

In this embodiment as well, in order to reduce variations in hysteresis characteristics due to process variations, each MOSFET
It is desirable that QIO to Q19 have at least the same channel length.

〔effect〕

(1) By adding a P-channel O3FET and/or an N-channel length OSFET that receives an inverted signal of the output signal to the P-channel O3FET and N-channel MOSFET that constitute the CM OS inverter circuit, the input signal can be made high. The conductance ratio when changing from a low level to a high level or from a low level to a high level can be made different. This provides the effect that a Schmitt trigger circuit having a hysteresis characteristic of an arbitrary width can be obtained by setting the conductance ratio.

(2) The hysteresis characteristic according to +1) above is determined by the conductance ratio, so each MOSF
By making the channel length of the ET the same, it is possible to obtain the effect that the channel length can be kept constant regardless of process variations.

(3) The effect of easily changing the hysteresis characteristics by preparing multiple MOSFETs with different conductance ratios and selectively connecting them using the master slice method. is obtained.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. For example, in the embodiment shown in FIG. 3, MOSFETs Q10 to Q13. Among Q14 to Q17,
If the connection is cut at the point marked with an x in the same figure, it will not be used, and NMOSFETQ13 or Q13 and Q12 (Q1
7 or Q17 and Q16) to the above inverter circuit IV1f
7) MOSFETQ18 that receives the output. It may be used in parallel connection with Q19, or it may be a combination of the embodiment circuit shown in FIG. 1 and the embodiment circuit shown in FIG. 3.

By doing so, a wider variety of hysteresis characteristics can be selected. In addition, the inverter circuit IV2 may be omitted. If the above-mentioned hysteresis characteristic does not need to be changed, the above-mentioned added MOS FETs may be formed in the required number and connected in a fixed manner. It is something that

[Application field]

The present invention can be widely used in various semiconductor integrated circuit devices including Schmitt trigger circuits, such as CMOS gate arrays or custom built circuits.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the Schmitt trigger circuit according to the present invention, FIG. 2 is an input/output transfer characteristic diagram for explaining its operation, and FIG. 3 is a circuit diagram showing an embodiment of the Schmitt trigger circuit according to the present invention. A circuit diagram showing another embodiment of the circuit. FIG. 4 is a circuit diagram showing an example of the prior art.

Claims (1)

[Claims] 1. A first CMOS inverter circuit and this first CM
a second inverter circuit that receives the output signal of the OS inverter circuit; and an N-channel MOSFET and/or P-channel MOSFET that receives the output signal of the second inverter circuit and constitutes the first CMOS inverter circuit.
N-channel MOSFET configured in parallel with T and/or
Alternatively, a semiconductor integrated circuit device comprising a Schmitt trigger circuit including a P-channel MOSFET. 2. N-channel MOSFET and/or P-channel MOSF that receives the output signal of the second inverter circuit
Claim 1, characterized in that the ET is formed with the same channel length as the MOSFET constituting the first CMOS inverter circuit, and is one or more MOSFETs connected in series using a master slice method. The semiconductor integrated circuit device described above. 3. The N-channel MOSFET and P-channel MOSFET that constitute the first CMOS inverter circuit are:
A plurality of MOSFETs are selectively connected in parallel using a master slice method, and the N-channel M is configured to receive an output signal from the second inverter circuit.
The OSFET and/or P-channel MOSFET is one MOSFET that constitutes the first CMOS inverter circuit.
2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is formed to have the same size as an SFET. 4. The semiconductor according to claim 1, 2, or 3, wherein the Schmitt trigger circuit constitutes an input buffer that transmits an input signal supplied from an external terminal to an internal circuit. Integrated circuit device.