JPS60111440A - Integrated circuit device - Google Patents

Abstract

PURPOSE:To enable to obtain a gate array having a higher integration density by using only one-layer aluminum wirings in a semiconductor integrated circuit device, wherein the gate array consisting of MOSFETs is formed by a master slice system, by a method wherein gate metal wires are connected to the aluminum wirings running to the Y direction. CONSTITUTION:In a gate array, a wiring region is respectively provided between the rows of fundamental cells disposed in a matrix type and plural wires of first aluminum wirings 11 are provided there in such a way as to run to the Y direction in parallel with the rows. In the conventional method, second aluminum wirings, which intersect orthogonally with the first aluminum wirings, have been used for connecting the fundamental cells and the abovementioned first aluminum wirings or connecting the first aluminum wirings with each other, but in this method, the role of the second aluminum wirings has been replaced with that of gate metal wires consisting of polycrystalline silicon, etc., for eliminating the second aluminum wirings consisting of aluminum. This method has been designed in such a way that a gate metal wire 14 consisting of the gate of the fundamental cell is extended to a wiring region and the gate metal wire 14 can be connected with any first aluminum wirings 11 in the wiring region. As a result, the gate metal wires 14 can be used for the use of wirings in a direction, which intersects orthogonally with the first aluminum wirings.

Description

[Detailed description of the invention] [Technical field to which the invention pertains] The present invention relates to a semiconductor integrated circuit device, and in particular to a MOSFET.
The present invention relates to a semiconductor integrated circuit device in which a gate array according to the present invention is formed by a master slicing method.

[Prior art and its problems]

A typical integrated circuit requires about 15 masks, and the mask manufacturing time and wafer manufacturing time also take longer depending on the number of masks used, so the disadvantage of a typical integrated circuit is that it takes a relatively long time to complete. A gate array based on the mass-to-slice method, which has been proposed as a method to improve all of these points, is a method in which commonly used basic cells are arranged in advance in a matrix, and a metal wiring mask is fabricated for each integrated circuit to integrate the gate array. It constitutes a circuit.

Therefore, according to this method, even if the circuits are different, about 10 masks can be used in common before the metal wiring process, and since they can be manufactured in common, they can be kept in stock before the metal wiring process. Therefore, the manufacturing period for each integrated circuit can be greatly shortened, and the manufacturing process can be easily managed even in the case of high-mix, low-volume production.

As described above, the gate array using the mask slicing method has great advantages, but since the metal wiring process usually uses two layers of aluminum, the time required for the process cannot be said to be short. When using a single layer of aluminum wire, which requires a short process time, the integration density was usually very low.

[Purpose of the invention]

It is an object of the present invention to provide an integrated circuit device including all basic cells that enables a gate array with high integration density using only one layer of aluminum.

[Summary of the invention]

In the gate array, a wiring area is provided between the columns of basic cells arranged in an IJ square shape, and a plurality of first aluminum wirings run parallel to the columns (in the two Y directions). Orthogonal to this, a second aluminum wiring connects the basic cell to the first aluminum wire or the first aluminum wire.
Used for connections between aluminum wires.

In order to eliminate the second aluminum wiring, its role is replaced with a gate metal such as polysilicon. The gate metal constituting the gate of the basic cell is extended to the wiring area to enable connection with any first aluminum in the wiring area, and a transverse line is made by the gate metal in the basic cell, and a cross line is created in the direction perpendicular to the first aluminum. Used for wiring. This transverse line now extends into nine wiring areas.

〔Effect of the invention〕

Not only does a single layer of aluminum allow wiring of the gate array, but it also facilitates connection with the aluminum lines in the channel region, thus providing a high integration density. Moreover, since only one layer of aluminum is used, the process period is short and the cost is low.

[Embodiments of the invention]

A typical gate array has basic cell rows in which basic cells 1 are lined up in the Y direction in a chip as shown in FIG. 1, and a wiring region 2 exists between them. Furthermore, the basic cell that is currently widely used uses two layers of wiring metal, as shown in FIG. In the figure, the hatched portion 12 is made of the first layer wiring metal, and the hatched portion 12 is made of the second layer wiring metal. Further, 13 indicates the frame of the basic cell.

As shown in FIG. 3, the embodiment of the present invention extends the gate metal 14 (in the X direction) instead of using the 20th wiring metal 12 in FIG. 2, which is connected to the first wiring metal in the wiring area. It can be connected to any wiring metal running in the Y direction of the area. The same parts as in Fig. 2 are given the same numbers.

Furthermore, connecting lines 15, 1.6 made of metal wires of the same layer as the metal gate are parallel to the extension line of gate metal ■4 running in the X direction.
is being made. ``The dotted line 13 in FIG. 3 represents the frame m of the basic cell. In this case, the basic cell also includes a part that becomes the wiring area,
When the dotted line frames in FIG. 3 are arranged horizontally, the cell column area 1 seen in FIG. A wiring area can be formed. 17 is a gate extension line of an adjacent cell column.・If the basic cells '6x in FIG. High-density wiring similar to that achieved by using the second aluminum wiring becomes possible.

[Brief explanation of drawings]

Fig. 1 is a plan view showing basic cell rows and wiring areas of a gate array, Fig. 2 is a plan view showing an example of a normal basic cell, and Fig. 3 is a plan view showing an example of a normal basic cell.
The figure is a plan view of the basic cell and wiring area of the present invention.

Claims (1)

[Claims] Using a cell array formed by arranging a plurality of basic cells in a matrix as a common base, different types can be created by changing the wiring metal connection patterns within the basic cells and the wiring metal connection patterns between the basic cells. In the integrated circuit device that constitutes the circuit of
As a general rule, the wiring metal runs in the Y direction, and the gate of the transistor of the cell is extended to the wiring area existing between the basic cell rows, and the gate dedicated to wiring interconnection runs across the basic cell in the t-x direction. An integrated circuit device characterized by having one or more wirings in the same layer.