JPS61283143A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To enable the reduction of a chip size by setting the disposing pitch of a wiring track for forming a circuit block and the disposing pitch of a wiring track between circuit blocks disposed in the same direction to different size for allowing a designing rule. CONSTITUTION:A wiring pitch of 6mum or larger is allowed as 1-layer wirings, and a wiring pitch of 12mum or larger is allowed as 2-layer wirings. Accordingly, the x direction disposing pitch of y direction wiring track 18 in the 1-layer block is set to 8mum, and the x direction disposing pitch of y direction wiring track 16 between 2-layer blocks is set to 12mum. When the y direction disposing pitch of x direction wiring track 17 in the 1-layer block is set to 8mum, the data positions in the 1-layer block wirings are all disposed 8mum in the block designing lattice positions of x direction and 8mum in y direction. The tracks 18, 16 are so disposed as to coincide with each other at every 24mum of the least common multiple of the pitches, and the block terminals are disposed on the coincident wiring track.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a semiconductor integrated circuit, and particularly relates to a master slice type semiconductor integrated circuit.

[Conventional technology]

Conventionally, in the manufacture of master slice type semiconductor integrated circuits, cells consisting of multiple elements such as transistors and resistors are arranged in a play shape within a chip, and a semiconductor substrate having a nine structure (usually a mass N/T slice) is first manufactured. Processes (usually called master processes) that can be processed all at once are prepared in a completed form. Next, in the wiring process, metal wiring such as aluminum laminate is used to connect multiple elements of one or more cells to each other to form a circuit block, and also to make connections between circuit blocks. A method has been adopted in which a group of large-scale integrated circuits (hereinafter referred to as LSI) having desired functions is derived.

By adopting this method, the labor and time required for designing and manufacturing each LSI type are reduced only to the part related to the wiring process that uses a layout pattern unique to each type. In order to significantly shorten the development period for LSI products, it is necessary to save labor in designing wiring process patterns in master slicing. There is a need. For this purpose, in recent years, automation of the placement of circuit blocks and the wiring design between circuit blocks has been developed.
Furthermore, it has become common to simplify and even automate the wiring design within circuit blocks.

Simplification of the wiring process design for the above =

A chip layout structure that enables automation will be explained using drawings.

FIG. 3 is a layout diagram of an example of a conventional i-star slice type semiconductor chip.

The chip 1 is composed of a peripheral region 2 in which pads, input/output circuit cells, etc. are placed, and an internal cell array region 3. In the internal cell array region 3, internal cells 4 made up of a plurality of transistors and resistors are arranged in an internal cell column 5 arranged in the X direction. An inter-internal cell wiring area 6 is provided between the internal cell rows 5.
The pitch in the lateral direction and the pitch in the y direction (vertical direction) are each determined according to rules in consideration of automatic design and the like.

Regarding the wiring process pattern unique to each LSI type used on the mask substrate layout structure described above, the case where two wiring layers are used will be described using FIG. 4.

FIG. 4 is a layout diagram of an example of an internal cell array unit repeating unit centered on one internal cell of a conventional bipolar ECL circuit master slice.

- In these internal cells, not only the arrangement of each transistor 1° and resistor 11, but also the contacts 12 of each transistor and resistor, and the single-layer wiring pattern 13 for electrodes covering the contacts are also mapped. , regardless of the difference in LSI type. A circuit block (hereinafter simply referred to as a block) is constructed by using a plurality of internal cells and interconnecting the electrodes of the elements in each cell. Connections between elements are mainly made using one-layer wiring arranged on the inter-element wiring area 14 in internal cells, but if one-layer wiring alone is insufficient, a block can be connected using multiple cells adjacent in the y direction. When configuring, use 2 layers! is also used. Within each block, block terminal positions are appropriately defined in preparation for later inter-block connections. Next, a plurality of blocks of a plurality of types are arranged on the internal cell array, and the block terminals are connected to each other so that each LS
I variety is completed.

Connections between blocks include one-layer wiring running in the X direction within the internal intercell wiring area 6, and 2 wiring running in the y direction vertically through the cell rows.
1! This is done using wiring. In preparation for the automatic design of wiring between normal blocks, paths (hereinafter referred to as tracks) 15 where wiring can be arranged in the X direction between blocks on the first layer and y between blocks on the second layer
A directional wiring track 16 is set. Furthermore, in preparation for the simplification and automation of block design, an X-direction wiring track 17 for one-layer block configuration (hereinafter abbreviated as "intra-block") and a one-layer intra-block y-direction wiring track 18 are set. Regarding the wiring within the 2-layer block.

A two-layer inter-block y-direction wiring track 16 will be used.

[Problem that the invention seeks to solve]

In the conventional master slice internal cell structure shown in FIGS. 3 and 4, wiring tracks in the same direction are normally set at the same pitch regardless of whether they are intra-block wiring tracks or inter-block wiring tracks. Therefore, the wiring track pitch is often not the minimum value allowed by the design rules for each wiring layer.This will be explained using the cell layout example shown in FIG. 4.

When A/wiring having a thickness of about 0.7 μm is used as the first layer wiring, the minimum wiring pitch allowed by today's lithography technology is 5 to 7 μm. On the other hand, the arrangement pitch of element electrodes such as transistors is affected by factors other than wiring design rules, such as diffusion pattern design rules, and needs to be approximately 8 μm. Therefore, in FIG. 4, the first layer X-direction intra-block wiring tracks 17 are set at a pitch of 8 μm, and since the wiring tracks in the same direction are set at the same pitch,
The first layer X-direction inter-block wiring tracks 15 also have a pitch of 8 μm. Similarly, regarding the y-direction wiring track,
When A/wiring with a thickness of approximately 1.5 μm is used as the second layer wiring, the minimum allowable wiring pitch is approximately 12 μm.
The arrangement pitch of the wiring tracks 18 in the y direction within the layer block is also 1.
It becomes 2 μm. Therefore, the conventional wiring track structure described above increases the internal cell area and the internal cell arrangement pitch, leading to an increase in chip size, which becomes unacceptable especially in a large-scale master slice.

An object of the present invention is to provide a master slice type semiconductor integrated circuit which reduces the chip area by N〆 without impairing the ease of wiring design of the conventional layout structure described above.

[Means for solving problems]

The semiconductor integrated circuit of the present invention has a cell array in which a plurality of cells each consisting of a plurality of elements are arranged in rows and columns in two directions perpendicular to each other, and one or more wiring layers are used to connect one or more cells within the cell. In a master slice type semiconductor integrated circuit, which connects a plurality of elements to form a circuit block and connects one or more of the circuit blocks to derive a group of integrated circuits having different functions, 1
Arrangement pitch of circuit block wiring that is arranged in one or more directions belonging to one or more wiring layers and a circuit block that belongs to at least one or more wiring layers that is arranged in the same direction as the circuit block wiring This structure is constructed by making the arrangement pitches of the inter-wirings different.

〔Example〕

- Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a layout diagram of a first embodiment of the present invention.

This embodiment is similar to the conventional example shown in FIG.
This is an example in which the present invention is applied to a mold master slice, and the first
The figure shows the layout of the internal cell array unit repeating unit 7a. That is, in this embodiment, the present invention is applied to the y-direction wiring track 18 within the first layer block and the y-direction wiring track 16 between the second layer blocks.

The arrangement pitches of the first-layer intra-block y-direction wiring tracks 18 and the second-layer inter-block y-direction wiring tracks 16 are set to different pitches permitted by the layout design rules for each wiring layer.

When wiring layers similar to those shown in the conventional example shown in FIG. 4 are used, a wiring pitch of 6 μm or more is allowed for first-layer wiring, and a wiring pitch of 12 μm or more is allowed for second-layer wiring. Therefore, in this embodiment, the arrangement pitch in the X direction of the y-direction wiring tracks 18 within the first-layer block is 8 μm, and the arrangement pitch in the X-direction of the y-direction wiring tracks 16 between the second-layer blocks is 12 μm.
It is set to m. The arrangement pitch in the y-direction of the X-direction wiring tracks 17 in the first-layer block is set to 8μ as in the conventional example shown in FIG.
In the case of m, all the data positions of the wiring within the first layer block are arranged at 8 positions in the X direction. Furthermore, the first-layer block intra-block y-direction wiring track 18 and the second-layer inter-block y-direction wiring track 16 are arranged so as to match every 24 μm, which is the least common multiple of their respective pitches, and the block terminals are placed on the matching wiring tracks. It is preferable that the

By using the wiring track arrangement structure explained above using FIG. 1, intra-block wiring and block terminals are placed at preset block design grid point positions, and block terminals are placed on inter-block wiring tracks. Therefore, it becomes possible to set the intra-block y-direction wiring tracks 18 densely without impairing the ease of block design and inter-block wiring design in consideration of automatic design and the like. As a result, the cell size can be reduced while securing the same number of wiring tracks in the y-direction in one layer block compared to the conventional method.

FIG. 2 is a layout diagram of a second embodiment of the present invention.

Similar to the first embodiment, this embodiment is also an example in which the present invention is applied to an ECL type master slice, and the X-direction wiring track 17 within the first layer block and the X-direction wiring track 15 between the first layer blocks are The present invention is applied. That is, the X-direction pitch of the X-direction wiring tracks 17 within the first layer block and the X-direction pitch of the X-direction wiring tracks 15 between the 14th block are different. The X-direction pitch of the X-direction wiring tracks 17 in the first-layer block is selected to be the minimum pitch allowed by the design rules for the first-layer wiring electrodes of elements such as transistors, for example, 8 μm, which is the same as the conventional example shown in FIG. . On the other hand, the first
The X-direction pitch of the inter-layer block X-direction wiring tracks 15 is selected to be the minimum pitch, for example, 6 μm, which is allowed by today's interlayer trinography technology, without being affected by the elements or the like. t, y-direction wiring track 18 between first layer blocks
The pitch in the X direction is set to 8 μm, for example, as in the first embodiment. Furthermore, preferably, by making the arrangement pitch of the internal cells in the y direction a multiple of the pitch in the In the design of a large-scale circuit block composed of two or more adjacent nine-cell groups, the X-direction 8 μ
The design data is set so that it can be arranged on the block design grid points of m pitch and 8 μm pitch in the y direction. in particular,
In this example, the pitch of the internal cells in the X direction is
X-direction pitch 8 of X-direction wiring track 17 in layer block
It is set to 96 μm, which is a multiple of μm.

Therefore, for example, if the lower left block design lattice point of the lower cell is selected as the block design origin 19, the X direction pitch of the 1-layer inter-block
Regardless of the fact that K is m, all the block design grid points including the lower and upper cells are arranged on a uniform pitch of 8 μm in the X direction and 8 μm in the Y direction, so two cells are placed at once. This makes it possible to simplify and even automate the design of all blocks. On the other hand, since the pitch in the X direction of the X-direction wiring tracks 15 between the first-layer blocks is reduced to 6 μm, the same number of X-direction wiring tracks between the first-layer blocks can be secured compared to the conventional example shown in FIG. At the same time, it becomes possible to reduce the pitch of the internal cells in the X direction and, by extension, the chip size.

In the above embodiment, an example was explained in which two-layer wiring is used in a bipolar ECL type master slice, but the present invention can also be applied to other types such as CMO8fl1, etc. Of course, it can also be applied.

〔Effect of the invention〕

As described above, in the master slice, the arrangement pitch of wiring tracks for circuit block configuration and the arrangement pitch of inter-circuit block wiring tracks arranged in the same direction can be set to be compatible with each other as permitted by design rules. Since they are set to different dimensions, it is possible to obtain a semiconductor integrated circuit with a reduced internal cell arrangement pitch and, by extension, chip size, without sacrificing the ease of simplification and automation of single circuit block design and design between circuit blocks. It has the effect of being

[Brief explanation of drawings]

Fig. 1 is a layout diagram of a first embodiment of the present invention, Fig. 2 is a layout diagram of a second embodiment of the invention, and Fig. 3 is a layout diagram of an example of a conventional mass-machine-two-chair type semiconductor chip. , FIG. 4 is a layout diagram of an example of an internal cell array unit repeating unit centered on one internal cell of a conventional bipolar ECL circuit master slice. l...chip, 2...peripheral area, 3.
...Internal cell array area, 4...Internal cell, 5...Cell column, 6...Wiring area,
7a, 7b...Internal cell array unit repeating unit,
10...Transistor, 11...Resistor, 12...Contact, 13...1-layer wiring pattern for electrode, 14...Inside cell Inter-element wiring area, 15...X-direction wiring track between 1st layer blocks, -16...Y-direction wiring track between 2nd layer blocks, 17...X within 1st layer block Direction wiring track, 18... Y-direction wiring track in 1st layer block, 19... Origin for block design. Kaya 1st book

Claims (1)

[Claims] 1. It has a cell array in which a plurality of cells consisting of a plurality of elements are arranged in rows and columns in two directions orthogonal to each other, and one or more wiring layers connect the plurality of elements in one or more cells. In a master slice type semiconductor integrated circuit that connects one or more circuit blocks to form a circuit block and connects one or more of the circuit blocks to derive a group of integrated circuits having different functions, the one or more wiring layers The arrangement pitch of circuit block wirings arranged in one or more directions to which they belong and the arrangement pitch of intercircuit block wirings belonging to at least one or more wiring layers arranged in the same direction as the circuit block structure wirings, Semiconductor integrated circuits have different characteristics.