JPS6245112A - Semconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To detect a positioning mark easily and positively by electron beams, etc., by selectively leaving a film shaped before the formation of a wiring layer constituting the positioning mark in a positioning-mark forming region. CONSTITUTION:A second wiring layer 10 is positioned while using a positioning mark shaped at the same time as a first wiring layer 5 as a reference position on the operation of exposure for forming the second wiring layer 10 in order to shape the second wiring layer 10 in precise positional relationship to the first wiring layer 5 under the second wiring layer. Since a bulk swelling layer 2a is left in the lower section of the positioning mark 6 at that time, the top section of the positioning mark 6 is projected in size higher than a wiring connector 8 for the simultaneously shaped first wiring layer 5 only by approximately the thickness section of the bulk swelling layer 2a, thus distinctly discriminating the positioning mark 6.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device and its manufacturing technology, and particularly to a technology that is effective when applied to a semiconductor device having a multilayer wiring structure and its manufacturing technology.

[Background technology] In the manufacturing of semiconductor devices, there is an increase in the density of semiconductor elements,
In order to reduce the area of the wiring structure, which greatly affects the degree of integration of devices, as the degree of integration increases, so-called Multilayer wiring techniques may be used.

In this case, the level difference in the insulating film caused by the wiring structure is likely to cause disconnection in the wiring structure formed in the upper layer.
For this reason, it is conceivable to use a wiring planarization technique that uniformly fills the wiring gaps with an insulator.

Furthermore, in order to connect multiple wiring layers formed in multiple layers, instead of the technique of forming through holes in an insulating film by etching or the like to achieve electrical continuity between each wiring layer, we have developed a method that allows the wiring layers to be connected in advance. A wiring connector is formed in the negative part of the structure to a height that penetrates the insulating film formed thereon and exposes the surface, and this wiring connector ensures electrical connection between each wiring layer. It is conceivable to make it possible to cope with the miniaturization of the wiring structure by making the wiring structure smaller.

On the other hand, in the multilayer wiring technology described above, it is important to maintain the mutual positional relationship of each wiring layer with high precision. It is conceivable that the wiring connectors that are formed protruding from the structure are formed at the same time and used as positioning marks in the exposure operation when forming the next wiring layer, but it is possible to form them before forming the next wiring layer. The difference in level between the wiring connector, which serves as a device alignment mark made of an insulating film, and the surrounding insulating layer is small, and the detection accuracy of the alignment mark using an electron beam is relatively low, for example in an exposure operation using an electron beam. The inventors of the present invention have found that there is a drawback that the positional accuracy in forming a multilayer wiring structure is reduced.

In addition, as a document explaining the multilayer wiring technology in the manufacture of semiconductor devices, there is Kogyo Research Association Co., Ltd., published November 10, 1982 [Electronic Materials J, 1982 special issue, P23 to P.28].

[Object of the Invention] An object of the present invention is to provide a semiconductor device and a manufacturing technique thereof that can form a multilayer wiring structure with high precision.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows.

That is, a film formed before forming the wiring layer constituting the alignment mark is selectively applied to the alignment mark forming region of the semiconductor device in which the alignment mark is constituted using a part of the wiring layer. By leaving the wiring layer in the alignment mark forming area, the alignment mark formed using a part of the wiring layer at the same time as the formation of the wiring layer is formed.
By protruding relatively high from the periphery by the thickness of the film that was selectively left before, the detection accuracy of alignment marks by, for example, electron beams can be improved, and the multilayer wiring structure of semiconductor devices can be improved. This makes it possible to form with high precision.

[Example] FIG. 1 (al to tel are enlarged cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention in order of steps.

First, as shown in FIG. 1+a+, on a substrate 1 on which a predetermined transistor structure (not shown) is formed, a conductive layer is placed at a position corresponding to the electrode part of the transistor structure. After the buffer layer 2 made of polycrystalline silicon or the like is deposited, an insulating film made of silicon oxide or the like is deposited over the entire surface, and the portion of the insulating film 3 deposited on the buffer layer 2 is etched. etc., and the opening 4 is formed.

In this case, when forming the buffer layer 2 on the surface of the substrate 1, the alignment mark forming area on the surface of the substrate 1 is covered with the entire surface of the substrate 1 in order to form the buffer layer 2. By leaving a part of the deposited film made of polycrystalline silicon etc., a bulky layer (in other words,
A bulky region 2a protruding from the surface of the substrate 1 is formed at the same time, and the portion corresponding to the position of the bulky layer 2a of the insulating film 3 deposited on top of this height q2a is another flat portion. It is in a raised state by the thickness of the bulky layer 2a compared to the above.

Next, as shown in FIG. The electrode portions of the transistor structure formed in 1 are electrically connected via the buffer layer 2.

In this case, the first arrangement 'lL! The A layer 5 is composed of a lower layer 5b and an upper layer 5C with a stopper layer 5a made of a conductor or the like indicated by a broken line sandwiched therebetween.

Next, as shown in Figure C1, a part of the first wiring N5 is removed by etching, a predetermined wiring structure is formed on the insulating film 3, and the bulky layer 2a remains. A portion of the first wiring layer 5 is left in a portion corresponding to the alignment mark forming area, and an alignment mark 6 is formed.

Further, after a resist 7 is deposited on the alignment mark 6 and a predetermined portion of the first wiring layer 5, the upper layer 5C constituting the first wiring layer 5 is removed by etching up to the stopper layer 5a. As shown in dl, the first
The upper layer 5C is left in a part of the wiring layer 5, and a protruding wiring connector 8 is formed.

As shown in FIG. 5E, an insulating film 9 is formed flat on the first wiring layer 5 by, for example, an etch-back technique, and the wiring connectors formed on the first wiring layer 5 are The top of N5 is made to slightly protrude from the surface of the insulating film 9, and is connected to the next second wiring layer 10 formed on the insulating film 9 and indicated by the dashed line, thereby forming the first wiring N5. Electrical connection between the second wiring layer 10 and the second wiring layer 10 is achieved.

In this case, in order to form the second wiring layer 10 in a precise positional relationship with respect to the first wiring layer 5 below, the exposure operation for forming the second wiring layer 10 is performed at the same time as the first wiring layer 5. Positioning is performed using the formed alignment mark 6 as a reference position, but in this embodiment, since the height 1i12a remains below the alignment mark 6,
The top of the alignment mark 6 protrudes higher than the wiring connector 8 of the first wiring layer 5 formed at the same time by approximately the height N2a.

As a result, the alignment mark 6 can be easily and clearly distinguished from the periphery of the alignment mark 6 during an exposure operation using an electron beam or the like, and the second wiring layer 10 can be accurately distinguished from the first wiring layer 5. It can be formed with high precision depending on the positional relationship.

By sequentially repeating the above operations, a multilayer wiring structure can be formed with high precision.

[Effects] (1) One alignment mark is formed in the alignment mark forming region of a semiconductor device using a part of a wiring layer before the wiring layer forming the alignment mark is formed. Since the film has a structure in which the film is selectively left, at the same time as the wiring layer is formed in the alignment mark forming area, the alignment mark formed using a part of the wiring layer is left selectively before that. It protrudes relatively largely from the periphery by the thickness of said one pattern, and allows for easy and reliable detection of alignment marks using, for example, electron beams, and enables highly accurate formation of multilayer wiring structures of semiconductor devices. It becomes possible to do so.

(2) As a result of +11, the wiring in each wiring layer can be arranged more densely, the density and integration of semiconductor elements can be increased, and performance such as operating speed of the semiconductor device can be improved.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Nor.

For example, a plurality of alignment marks may be formed.

[Field of Application] In the above explanation, the invention made by the present inventor was mainly applied to the field of application which is the background thereof, which is the formation of a multilayer wiring structure of a semiconductor device, but the present invention is not limited thereto. It can be widely applied to the manufacturing process of fine structures.

[Brief explanation of drawings]

FIGS. 1A to 1E are enlarged cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention in order of steps. 1...Substrate, 2...Buffer layer, 2a... ...bulky layer, 3
... Insulating film, 4... Opening, 5... First wiring layer,
5a... Stopper layer, 5b... Lower layer, 5C... Upper layer, 6... Positioning mark, 7... Resist, 8
... Wiring connector, 9... Insulating film, 10... Second wiring layer.

Claims (1)

[Scope of Claims] 1. A semiconductor device in which an alignment mark is formed using a part of a wiring layer, wherein the alignment mark is formed in the alignment mark formation region before the wiring layer forming the alignment mark is formed. A semiconductor device characterized in that a formed film is selectively left. 2. Claim 1, wherein the semiconductor device has a planarized multilayer wiring structure using interlayer connectors.
1. Semiconductor device described in Section 1. 3. A method for manufacturing a semiconductor device in which an alignment mark is formed using a part of a wiring layer, the method comprising: leaving a bulky layer on the substrate in the alignment mark forming region, and forming a wiring layer above the bulky layer; 1. A method for manufacturing a semiconductor device, characterized by forming a semiconductor device. 4. Claim 3, wherein the semiconductor device has a planarized multilayer wiring structure using interlayer connectors.
A method for manufacturing a semiconductor device according to section 1.