KR20090091957A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- KR20090091957A KR20090091957A KR1020080017201A KR20080017201A KR20090091957A KR 20090091957 A KR20090091957 A KR 20090091957A KR 1020080017201 A KR1020080017201 A KR 1020080017201A KR 20080017201 A KR20080017201 A KR 20080017201A KR 20090091957 A KR20090091957 A KR 20090091957A
- Authority
- KR
- South Korea
- Prior art keywords
- contact plug
- interlayer insulating
- auxiliary contact
- forming
- region
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
Abstract
The present invention includes a first interlayer insulating film formed on an upper surface of a semiconductor substrate, an auxiliary contact plug formed in an interlayer insulating film, a monitoring pattern formed on an upper part of an interlayer insulating film adjacent to the auxiliary contact plug, and after the etching process, a contact plug and an upper portion thereof You can monitor the alignment between the patterns.
Description
TECHNICAL FIELD The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device and a method for manufacturing the same that can monitor an alignment error.
The semiconductor device includes a contact plug for electrically connecting the substructure and the superstructure. For example, the lower structure may include a gate or a lower metal wiring, and the upper structure may include an upper metal wiring.
Meanwhile, as the degree of integration of semiconductor devices increases, the widths and spacings of the lower structures and the upper structures become narrower, making it difficult to align the lower layers with the layers to be formed in the semiconductor device manufacturing process.
Specifically, an overlay vernier may be formed in the scribe lane area to align and monitor the alignment. The case of a flash device will be described as an example.
In the process of forming the first metal wiring (M1) formed on the drain contact plug in the flash device, the overlay vernier is used to compare the overlap with the drain drain plug in the lower portion, followed by etching (or patterning). Carry out the process. However, it is difficult to determine the degree of overlap after the etching process.
For example, if the axis in the direction in which the contact plug is formed is referred to as the X axis and the axis perpendicular to the X axis is referred to as the Y axis, the degree of alignment error between the contact plug and the upper metal wiring pattern can be determined for the X axis. Is difficult to determine.
As described above, since the alignment error cannot be easily determined after the etching process for the metal wiring, the reliability of the semiconductor device may be degraded.
SUMMARY OF THE INVENTION An object of the present invention is to form an auxiliary contact plug in a non-driving region inside a die, and to form an insulating film for forming a metal wiring in electrical contact with the contact plug. By forming a monitoring pattern on the substrate, the alignment between the contact plug and the pattern on which the metal wiring is to be formed can be monitored even after performing the etching process for the metal wiring.
The semiconductor device according to the present invention includes a first interlayer insulating film formed over the semiconductor substrate. And an auxiliary contact plug formed in the interlayer insulating film. The semiconductor device may include a monitoring pattern formed on the interlayer insulating layer adjacent to the auxiliary contact plug.
The auxiliary contact plug is formed in an area where no gate and metal wiring is formed or in a non-driven area that is not connected to the electrically substantial elements, and the auxiliary contact plug is formed in a peripheral circuit area of the semiconductor substrate.
The monitoring pattern is formed in a rectangular, circular or oval pattern that exposes the auxiliary contact plug.
The auxiliary contact plug is formed in singular or plural, and when the auxiliary contact plug is formed in plural, the auxiliary contact plug is exposed to the inside of the monitoring pattern.
In a method of manufacturing a semiconductor device according to an embodiment of the present invention, a first interlayer insulating film is formed on a semiconductor substrate. An auxiliary contact plug is formed in the first interlayer insulating film. A second interlayer insulating film is formed on the first interlayer insulating film and the auxiliary contact plug. And a patterning process for forming the second interlayer insulating film into a monitoring pattern.
The auxiliary contact plug is formed in a region in which a gate and a metal wiring is not formed in the semiconductor substrate or in a non-driving region in which it is not electrically connected to the devices. The auxiliary contact plug is formed in a peripheral circuit region in the semiconductor substrate.
The auxiliary contact plug is formed of a conductive film or a metal film, or is formed by stacking a conductive film and a metal film, and the second interlayer insulating film is formed of an oxide film.
In the method of manufacturing a semiconductor device according to an embodiment of the present disclosure, a semiconductor substrate including a driving region and a non-driving region is provided. A first interlayer insulating film is formed on the semiconductor substrate. Contact plugs are formed in the driving region of the first interlayer insulating layer, and auxiliary contact plugs are formed in the non-driving region. A second interlayer insulating layer is formed on the first interlayer insulating layer, the contact plugs, and the auxiliary contact plug. And forming a second interlayer insulating pattern for the metal wiring in the driving region, and performing a patterning process on the second interlayer insulating layer to form a monitoring pattern in the non-driving region.
The contact plug and the auxiliary contact plug are formed in the same structure, and the contact plug and the auxiliary contact plug are formed of a conductive film or a metal film, or are formed by stacking a conductive film and a metal film.
According to the present invention, a monitoring pattern is formed on an upper portion of an auxiliary contact plug region during a patterning process of an insulating layer for forming an auxiliary contact plug in a non-driving region inside a die and for forming a metal wiring electrically contacting the contact plug. As a result, even after the etching process, the alignment between the contact plug and the pattern on the upper part may be monitored. As a result, deterioration of electrical characteristics of the semiconductor device can be prevented, so that reliability can be improved.
1A to 1C are plan views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
2A to 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
3 is a plan view illustrating a monitoring pattern according to an embodiment of the present invention.
4A to 4C are plan views illustrating a monitoring pattern according to another exemplary embodiment of the present invention.
<Description of the symbols for the main parts of the drawings>
100 semiconductor substrate 102 device isolation film
104: first interlayer insulating film 106a: contact plug
106b, CP: auxiliary contact plug 108: second interlayer insulating film
110: photoresist pattern MP: monitoring pattern
Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.
1A to 1C are plan views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention, and FIGS. 2A to 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. to be.
Referring to FIGS. 1A and 2A, a region in which a drain contact plug is formed in the flash device will be described as an example.
A semiconductor substrate 100 is provided in which a drive region and a non-drive region are partitioned. In this case, the driving region may be referred to as a cell region. The non-driving area may be referred to as an area in which devices (gates and metal wirings) are not formed or an area that is not electrically connected to devices. The non-driven region may be included in the cell region but is preferably included in the peripheral region.
A trench is formed in the semiconductor substrate 100 on which the junction region 100a is formed to define an isolation region and an active region, and then an isolation layer 102 is formed in the trench. Next, an interlayer insulating film 104 is formed on the device isolation film 102 and the semiconductor substrate 100. An etching process is performed to form a contact hole in the interlayer insulating film 104, and to fill the conductive film or the metal film in the contact hole, or to stack the conductive film and the metal film to form the contact plug 106a and the auxiliary contact plug 106b. ). The contact plug 106a formed in the drive region can be used as a drain contact plug. In this case, the auxiliary contact plugs 106b formed in the non-driving region are used for monitoring for subsequent overlap, and are not used for the operation of the semiconductor device.
1B and 2B, a second interlayer insulating film 104, a contact plug 106a and an auxiliary contact plug 106b are formed on the second layer to form a metal wiring to be subsequently formed by a damascene method. An interlayer insulating film 108 is formed. The second interlayer insulating film 108 may be formed of an oxide film.
Referring to FIGS. 1C and 2C, a photoresist pattern 110 for forming a metal wiring pattern is formed on the second interlayer insulating layer 108 of FIG. 2B. In particular, the photoresist pattern 110 forms a metal wiring pattern in the driving region, and forms a pattern for a monitoring pattern MP around the auxiliary contact plug 106b of the non-driving region. Subsequently, the second interlayer insulating layer 108 of FIG. 2B is patterned according to the photoresist pattern 110 to form a second interlayer insulating pattern 108a in the driving region, and a monitoring pattern MP in the non-driving region. To form. Subsequently, an interval between the monitoring pattern MP and the auxiliary contact plug 106b may be compared to determine whether an alignment error occurs after the etching process. The monitoring pattern MP will be described in more detail as follows.
3 is a plan view illustrating a monitoring pattern according to an embodiment of the present invention.
Referring to FIG. 3, when the monitoring pattern MP is formed in a rectangular shape at regular intervals around the auxiliary contact plug CP, a patterning process for forming metal wiring is performed by determining a change in the distance between the X and Y axes. The degree and direction of alignment errors before and after can be monitored. In particular, since the alignment error range in the Y-axis direction, which is difficult to determine in the driving region, can be known, this can be referred to in the subsequent manufacturing process of other semiconductor devices, thereby reducing the alignment error.
In the above-described exemplary embodiment, although the monitoring pattern MP is formed in a rectangular shape, the monitoring pattern MP may be changed and applied in various forms. For example, as shown in FIG. 4A, a circular or elliptical monitoring pattern MP may be formed around the auxiliary contact plug CP. At this time, the monitoring pattern (MP) may be formed by separating a predetermined section for the user's convenience. Alternatively, as shown in FIG. 4B, the surroundings of the auxiliary contact plugs CP may form a rectangular or square monitoring pattern MP. In this case, the monitoring pattern MP may be formed by separating a predetermined section.
In addition, as shown in FIG. 4C, a plurality of auxiliary contact plugs CP may be formed in the non-driving area, and in this case, the monitoring pattern MP may be formed to include all of the auxiliary contact plugs CP. . As such, when a plurality of auxiliary contact plugs CP are formed and thus the monitoring pattern MP is formed, the degree of inclination of the mask pattern during the etching process along with alignment errors with respect to the X and Y axes after the etching process is formed. Can also be determined.
As described above, the alignment error generation range of the pattern formed by the etching process may be monitored using the auxiliary contact plug CP and the monitoring pattern MP. Thereby, since the error range can be reduced in the subsequent process or the manufacturing process of another semiconductor substrate, the reliability of a semiconductor element can be improved.
Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.
Claims (14)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020080017201A KR20090091957A (en) | 2008-02-26 | 2008-02-26 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020080017201A KR20090091957A (en) | 2008-02-26 | 2008-02-26 | Semiconductor device and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20090091957A true KR20090091957A (en) | 2009-08-31 |
Family
ID=41209149
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020080017201A KR20090091957A (en) | 2008-02-26 | 2008-02-26 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20090091957A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10567688B2 (en) | 2018-01-10 | 2020-02-18 | Samsung Electronics Co., Ltd. | Image sensor with test light shielding pattern, imaging device, and method of manufacturing image sensor chip package |
-
2008
- 2008-02-26 KR KR1020080017201A patent/KR20090091957A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10567688B2 (en) | 2018-01-10 | 2020-02-18 | Samsung Electronics Co., Ltd. | Image sensor with test light shielding pattern, imaging device, and method of manufacturing image sensor chip package |
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| WITN | Withdrawal due to no request for examination |