KR101043411B1 - A method for forming a metal line of a semiconductor device - Google Patents

A method for forming a metal line of a semiconductor device Download PDF

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KR101043411B1
KR101043411B1 KR1020040051118A KR20040051118A KR101043411B1 KR 101043411 B1 KR101043411 B1 KR 101043411B1 KR 1020040051118 A KR1020040051118 A KR 1020040051118A KR 20040051118 A KR20040051118 A KR 20040051118A KR 101043411 B1 KR101043411 B1 KR 101043411B1
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bit line
forming
metal wiring
semiconductor device
insulating film
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KR1020040051118A
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Korean (ko)
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KR20060002181A (en
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김종수
김홍진
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H01L21/28141—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects insulating part of the electrode is defined by a sidewall spacer, e.g. dummy spacer, or a similar technique, e.g. oxidation under mask, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체소자의 금속배선 형성방법에 관한 것으로, 비트라인에 접속되는 금속배선의 콘택 공정시 비트라인 주변의 하부구조물 손상을 방지할 수 있도록 하기 위하여, 비트라인 측벽에 절연막 스페이서를 두껍게 형성하여 금속배선의 콘택 식각공정시 비트라인에 이웃하는 하부구조물의 손상을 방지할 수 있어 반도체소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 공정 마진을 향상시킬 수 있도록 하는 기술이다. The present invention relates to a method for forming a metal wiring of a semiconductor device, in order to prevent damage to the lower structure around the bit line during the contact process of the metal wiring connected to the bit line, by forming a thick insulating film spacer on the sidewall of the bit line It is a technology to improve the characteristics and reliability of the semiconductor device and thereby improve the process margin of the semiconductor device by preventing damage to the underlying structure adjacent to the bit line during the contact etching process of the metal wiring.

Description

반도체소자의 금속배선 형성방법{A method for forming a metal line of a semiconductor device}A method for forming a metal line of a semiconductor device

도 1 은 종래기술에 반도체소자의 금속배선 형성방법을 도시한 평면도 및 단면도.1 is a plan view and a cross-sectional view showing a metal wiring formation method of a semiconductor device in the prior art.

도 2 는 종래기술에 따라 비트라인에 콘택되는 금속배선 콘택영역을 도시한 평면도.2 is a plan view illustrating a metallization contact region contacted to a bit line according to the related art.

도 3 및 도 4 는 금속배선의 콘택 공정시 유발되는 문제점을 도시한 단면 및 평면 사진.3 and 4 are cross-sectional and planar photographs showing the problems caused during the contact process of metallization.

도 5 및 도 6 은 본 발명에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도.5 and 6 are cross-sectional views showing a metal wiring forming method of a semiconductor device according to the present invention.

도 7 은 상기 도 5를 도시한 평면 사진.7 is a plan view of FIG. 5.

< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>

11,41 : 반도체기판 13 : 게이트 도전층11,41: semiconductor substrate 13: gate conductive layer

15,25,45 : 하드마스크층 17,27 : 절연막 스페이서15,25,45: hard mask layer 17,27: insulating film spacer

19 : 랜딩 플러그 21 : 하부절연층19: landing plug 21: lower insulating layer

22 : 비트라인 콘택플러그 23,43 : 비트라인 도전층22: bit line contact plug 23,43: bit line conductive layer

29 : 저장전극 콘택홀 31 : 보호막 29 storage electrode contact hole 31 protective film                 

33 : 층간절연막 35 : 저장전극 콘택플러그33: interlayer insulating film 35: storage electrode contact plug

47 : 제1절연막 스페이서 49 : 제2절연막 스페이서47: first insulating film spacer 49: second insulating film spacer

51 : 제1층간절연막 53 : 감광막패턴51: first interlayer insulating film 53: photosensitive film pattern

55 : 제2층간절연막 57 : 금속배선 콘택플러그55: Second interlayer insulating film 57: Metal wiring contact plug

본 발명은 반도체소자의 금속배선 형성방법에 관한 것으로, 특히 주변회로부의 구비되는 섬형태의 비트라인에 금속배선을 콘택할 때 공정 마진을 확보할 수 있도록 하는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wiring of a semiconductor device, and more particularly, to a technique for securing a process margin when contacting a metal wiring with an island-type bit line provided in a peripheral circuit portion.

일반적으로 반도체소자를 구동하기 위하여, 이들을 전기적으로 동작시킬 수 있는 회로를 구성하여야 한다. In general, in order to drive semiconductor devices, a circuit capable of electrically operating them should be configured.

상기한 회로는 소자의 주변회로부에서 반도체소자의 각각 구성물을 전기적으로 콘택하는 금속배선을 예정된 형태로 형성한 것이다.The circuit described above is formed in a predetermined shape with a metal wiring for electrically contacting each component of the semiconductor device in the peripheral circuit portion of the device.

도 1 내지 도 3 은 종래기술에 따른 반도체소자의 금속배선 형성방법을 도시한 것이다. 1 to 3 illustrate a metal wiring forming method of a semiconductor device according to the prior art.

도 1 은 셀부 및 주변회로부에 형성되는 저장전극 콘택까지의 공정을 도시한 단면도로서, 상기 셀부는 X 축 및 Y 축 방향의 단면을 도시한 것이다. 1 is a cross-sectional view showing a process up to a storage electrode contact formed in a cell portion and a peripheral circuit portion, wherein the cell portion shows cross sections in the X-axis and Y-axis directions.

도 1을 참조하면, 반도체기판(11)에 활성영역을 정의하는 소자분리막(미도시)을 형성한다. Referring to FIG. 1, an isolation layer (not shown) defining an active region is formed on the semiconductor substrate 11.                         

상기 반도체기판(11) 상부에 게이트산화막(미도시), 게이트 도전층(13) 및 하드마스크층(15)인 질화막을 적층한다. A nitride film, which is a gate oxide film (not shown), a gate conductive layer 13, and a hard mask layer 15, is stacked on the semiconductor substrate 11.

게이트 마스크(미도시)를 이용한 사진식각공정으로 상기 적층구조를 식각하여 게이트를 형성한다. The stacked structure is etched by a photolithography process using a gate mask (not shown) to form a gate.

상기 게이트 측벽에 절연막 스페이서(17)를 형성한다. 이때, 상기 절연막 스페이서(17)는 질화막으로 형성한다. An insulating film spacer 17 is formed on the sidewall of the gate. At this time, the insulating film spacer 17 is formed of a nitride film.

상기 게이트 사이의 활성영역을 매립하는 랜딩 플러그(19)가 셀부에 형성된 하부절연층(21)을 전체표면상부에 형성한다. A lower insulating layer 21 having a landing plug 19 filling the active region between the gates is formed over the entire surface.

그 다음, 비트라인 콘택마스크를 이용하여 상기 셀부의 랜딩플러그(19)와 상기 주변회로부의 반도체기판(11)이나 게이트 도전층(13)에 접속되는 비트라인 콘택플러그(22)를 형성한다. Next, a bit line contact plug 22 connected to the landing plug 19 of the cell unit and the semiconductor substrate 11 or the gate conductive layer 13 of the peripheral circuit unit is formed using a bit line contact mask.

상기 비트라인 콘택플러그(22)에 접속되는 비트라인 도전층(23) 및 하드마스크층(25)을 적층하고 비트라인 마스크를 이용하여 패터닝함으로써 비트라인을 형성한다. The bit line is formed by stacking the bit line conductive layer 23 and the hard mask layer 25 connected to the bit line contact plug 22 and patterning the same using a bit line mask.

그 다음, 상기 비트라인의 측벽에 절연막 스페이서(27)를 질화막으로 형성하고 전체표면상부에 층간절연막(33)을 형성한다. Next, an insulating film spacer 27 is formed of a nitride film on the sidewall of the bit line, and an interlayer insulating film 33 is formed on the entire surface.

그리고, 저장전극 콘택마스크(미도시)를 이용한 사진식각공정으로 상기 셀부의 랜딩플러그(19)를 노출시키는 저장전극 콘택홀(29)을 형성하고 그 측벽에 보호막(31)을 형성한다. In addition, a storage electrode contact hole 29 exposing the landing plug 19 of the cell part is formed by a photolithography process using a storage electrode contact mask (not shown), and a protective layer 31 is formed on the sidewall thereof.

그 다음, 상기 저장전극 콘택홀(29)을 매립하는 저장전극 콘택플러그(35)를 셀부에만 형성한다. Then, the storage electrode contact plug 35 filling the storage electrode contact hole 29 is formed only in the cell portion.

후속 공정으로, 캐패시터를 형성하고 상기 주변회로부의 비트라인에 콘택되는 금속배선을 형성한다. 이때, 상기 주변회로부의 비트라인은 섬형태로 패터닝되어 금속배선의 콘택 패드 형태로 사용되는 것이다.In a subsequent process, a capacitor is formed and a metal wiring contacting the bit line of the peripheral circuit portion is formed. In this case, the bit line of the peripheral circuit part is patterned in an island shape to be used as a contact pad of a metal wire.

도 2 는 상기 도 1 의 비트라인 도전층(23)에 전기적으로 접속되는 금속배선 콘택홀(35)을 도시한 평면도이다. FIG. 2 is a plan view illustrating a metal wiring contact hole 35 electrically connected to the bit line conductive layer 23 of FIG. 1.

도 3 는 상기 도 2 와 같은 금속배선의 콘택 공정시 오정렬이 유발되어 비트라인 영역 바깥쪽까지 형성된 것을 도시한 단면 사진이다. FIG. 3 is a cross-sectional photograph illustrating that misalignment is caused during a contact process of a metal wiring as shown in FIG. 2 to the outside of the bit line region.

여기서, 상기 금속배선의 콘택 공정은 반도체소자의 고집적화에 따라 비트라인의 선폭이 감소되어 콘택 영역보다 그 크기가 작기 때문에 오정렬이 아니어도 비트라인 주변의 하부구조물이 식각되는 문제점이 유발된다. In this case, the contact process of the metal wiring has a problem that the lower structure of the bit line is etched even if not aligned because the width of the bit line is reduced and the size of the bit line is smaller than that of the contact area due to the high integration of the semiconductor device.

도 4 는 비트라인의 선폭보다 금속배선의 콘택 직경이 더 크게 형성된 것을 도시한 평면 사진이다. 4 is a planar photograph showing that a contact diameter of a metal wiring is formed larger than a line width of a bit line.

상기한 바와 같이 종래기술에 따른 반도체소자의 금속배선 형성방법은, 반도체소자의 고집적화에 따라 주변회로부의 비트라인 선폭이 금속배선 콘택영역의 직경보다 작아 중첩마진을 감소시키고 그에 따른 반도체소자의 수율을 저하시키는 문제점이 있다. As described above, in the method of forming a metal wiring of a semiconductor device according to the related art, the bit line line width of a peripheral circuit portion is smaller than the diameter of the metal wiring contact region according to the high integration of the semiconductor device, thereby reducing the overlap margin and thereby the yield of the semiconductor device. There is a problem of deterioration.

본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 주변회로부의 비트라인 측벽에 구비되는 절연막 스페이서의 선폭을 증가시켜 금속배선 콘택 공정과의 중첩마진을 확보할 수 있도록 하는 반도체소자의 금속배선 형성방법을 제공하는데 그 목적이 있다. In order to solve the above-mentioned problems of the related art, the metal wiring of the semiconductor device is formed to increase the line width of the insulating film spacer provided on the sidewall of the bit line of the peripheral circuit to ensure an overlap margin with the metal wiring contact process. The purpose is to provide a method.

이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 금속배선 형성방법은, In order to achieve the above object, a metal wiring forming method of a semiconductor device according to the present invention,

반도체기판 상에 비트라인을 형성하는 공정과,Forming a bit line on the semiconductor substrate;

상기 비트라인 측벽에 제1절연막 스페이서를 형성하는 공정과,Forming a first insulating film spacer on sidewalls of the bit lines;

반도체기판의 주변회로부의 비트라인 측벽에 상기 제1절연막 스페이서보다 두꺼운 제2절연막 스페이서를 형성하는 공정과,Forming a second insulating film spacer thicker than the first insulating film spacer on the bit line sidewalls of the peripheral circuit portion of the semiconductor substrate;

후속 공정으로 상기 비트라인 콘택되는 금속배선을 형성하는 공정을 포함하는 것과,Forming a metal wiring in which the bit line is contacted by a subsequent process;

상기 제1절연막 스페이서 및 제2절연막 스페이서는 질화막으로 형성하는 것을 특징으로 한다. The first insulating film spacer and the second insulating film spacer may be formed of a nitride film.

이하, 첨부된 도면을 참고로 하여 본 발명을 설명하면 다음과 같다. Hereinafter, the present invention will be described with reference to the accompanying drawings.

도 5 및 도 6 은 본 발명에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도 및 평면도로서, 주변회로부의 비트라인 측벽에 절연막 스페이서를 형성하고 상기 비트라인에 금속배선 콘택 공정을 실시하는 것이다. 5 and 6 are cross-sectional views and a plan view illustrating a method for forming a metal wiring of a semiconductor device according to the present invention, in which insulating film spacers are formed on sidewalls of bit lines and a metal wiring contact process is performed on the bit lines.

도 5 를 참조하면, 반도체기판(41)에 활성영역을 정의하는 소자분리막(미도시)을 형성한다. Referring to FIG. 5, an isolation layer (not shown) defining an active region is formed on the semiconductor substrate 41.

상기 반도체기판(41) 상부에 게이트산화막(미도시), 게이트 도전층(미도시) 및 하드마스크층(미도시)인 질화막을 적층한다. A nitride film, which is a gate oxide film (not shown), a gate conductive layer (not shown), and a hard mask layer (not shown), is stacked on the semiconductor substrate 41.

그 다음, 게이트 마스크(미도시)를 이용한 사진식각공정으로 상기 적층구조를 식각하여 게이트를 형성한다. Next, the stack structure is etched by a photolithography process using a gate mask (not shown) to form a gate.

상기 게이트 측벽에 절연막 스페이서를 형성하고, 후속 공정으로 상기 게이트 사이의 활성영역에 접속되는 랜딩 플러그(미도시)를 형성한다. An insulating film spacer is formed on the sidewall of the gate, and a landing plug (not shown) connected to an active region between the gates is formed in a subsequent process.

상기 랜딩 플러그에 접속되는 비트라인 도전층(49) 및 하드마스크층(45)의 적층구조를 형성한다. A stack structure of the bit line conductive layer 49 and the hard mask layer 45 connected to the landing plug is formed.

그 다음, 상기 비트라인 측벽에 제1절연막 스페이서(47)를 형성한다. 이때, 상기 제1절연막 스페이서(47)는 질화막으로 형성한다. Next, a first insulating layer spacer 47 is formed on the sidewalls of the bit line. In this case, the first insulating film spacer 47 is formed of a nitride film.

그 다음, 전체표면상부에 상기 제1절연막 스페이서(47)보다 두꺼운 제2절연막(미도시)을 증착한다.Next, a second insulating film (not shown) thicker than the first insulating film spacer 47 is deposited on the entire surface.

그리고, 셀 마스크(미도시)를 이용하여 셀부의 제2절연막을 제거하고 주변회로부의 제2절연막을 이방성식각하여 상기 비트라인 도전층(43) 및 하드마스크층(45)의 적층구조로 형성된 비트라인의 측벽에 제2절연막 스페이서(49)를 형성한다. The bit formed by stacking the bit line conductive layer 43 and the hard mask layer 45 by anisotropically etching the second insulating layer of the peripheral circuit part by using a cell mask (not shown). A second insulating film spacer 49 is formed on the sidewall of the line.

그 다음, 전체표면상부에 제1층간절연막(51)을 형성하고 이를 평탄화시킨다. Then, a first interlayer insulating film 51 is formed over the entire surface and planarized.

그리고, 상기 주변회로부만을 도포하는 감광막패턴(53)을 형성한다. Then, the photosensitive film pattern 53 for coating only the peripheral circuit portion is formed.

도 6을 참조하면, 상기 감광막패턴(53)을 마스크로 하여 셀부에 캐패시터를 형성하고, 상기 감광막패턴(53)을 제거한 다음, 전체표면상부를 평탄화시키는 제2층간절연막(55)을 형성한다. Referring to FIG. 6, a capacitor is formed in a cell portion using the photoresist pattern 53 as a mask, the photoresist pattern 53 is removed, and a second interlayer insulating layer 55 is formed to planarize the entire upper surface.                     

그 다음, 상기 비트라인의 비트라인 도전층(43)에 접속되는 금속배선 콘택플러그(57)를 형성한다. Next, a metal wiring contact plug 57 connected to the bit line conductive layer 43 of the bit line is formed.

이때, 금속배선 콘택 공정의 오정렬시에도 콘택 식각공정에 의한 하부구조물의 손상이 방지된다. In this case, even when the metal wiring contact process is misaligned, damage to the lower structure due to the contact etching process is prevented.

도 7 은 종래기술에 따라 형성된 반도체소자를 도시하는 도 4 의 비트라인 주변에 절연막 스페이서를 점선과 같은 크기로 형성하여 적어도 금속배선 콘택홀의 직경보다 같거나 큰 비트라인을 형성한 것을 도시하는 평면 사진이다. 7 is a planar photograph showing that an insulating film spacer is formed in the same size as a dotted line around a bit line of FIG. 4 showing a semiconductor device formed according to the prior art to form a bit line at least equal to or larger than the diameter of a metal wiring contact hole. to be.

이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 금속배선 형성방법은, 비트라인의 측벽에 절연막 스페이서를 두껍게 형성하여 상기 비트라인에 접속되는 금속배선 콘택 공정시 하부구조물이 식각되는 현상을 방지할 수 있도록 함으로써 반도체소자 제조공정의 마진을 확보할 수 있는 효과를 제공한다. As described above, in the method of forming metal wirings of the semiconductor device according to the present invention, a thick insulating film spacer is formed on the sidewalls of the bit lines to prevent the underlying structure from being etched during the metal wiring contact process connected to the bit lines. This provides an effect of securing a margin of the semiconductor device manufacturing process.

Claims (2)

반도체기판 상에 비트라인을 형성하는 공정과,Forming a bit line on the semiconductor substrate; 상기 비트라인 측벽에 제1절연막 스페이서를 형성하는 공정과,Forming a first insulating film spacer on sidewalls of the bit lines; 반도체기판의 주변회로부의 비트라인 측벽에 상기 제1절연막 스페이서보다 두꺼운 제2절연막 스페이서를 형성하는 공정과,Forming a second insulating film spacer thicker than the first insulating film spacer on the bit line sidewalls of the peripheral circuit portion of the semiconductor substrate; 후속 공정으로 상기 비트라인에 콘택되는 금속배선을 형성하는 공정을 포함하는 반도체소자의 금속배선 형성방법.And forming a metal wiring contacting the bit line in a subsequent process. 청구항 2은(는) 설정등록료 납부시 포기되었습니다.Claim 2 has been abandoned due to the setting registration fee. 제 1 항에 있어서, The method of claim 1, 상기 제1절연막 스페이서 및 제2절연막 스페이서는 질화막으로 형성하는 것을 특징으로 하는 반도체소자의 금속배선 형성방법.And the first insulating layer spacer and the second insulating layer spacer are formed of a nitride film.
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Citations (2)

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Publication number Priority date Publication date Assignee Title
KR20040002302A (en) * 2002-06-29 2004-01-07 주식회사 하이닉스반도체 Method for manufacturing a semiconductor device
KR20040008767A (en) * 2002-07-19 2004-01-31 주식회사 하이닉스반도체 A method for forming a semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040002302A (en) * 2002-06-29 2004-01-07 주식회사 하이닉스반도체 Method for manufacturing a semiconductor device
KR20040008767A (en) * 2002-07-19 2004-01-31 주식회사 하이닉스반도체 A method for forming a semiconductor device

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