KR101119156B1 - Semiconductor device and method for forming the same - Google Patents

Abstract

The semiconductor device of the present invention includes a semiconductor substrate including an active region defined as an isolation layer, a line type interlayer insulating film provided on the semiconductor substrate and spaced apart from each other by a first width and a second width on the same line, A spacer formed on sidewalls of the interlayer insulating layer spaced apart by one width and embedded between the interlayer insulating layers spaced apart by the second width, thereby effectively increasing an area where a storage electrode contact is connected to an active region, Increasing the overall cross section reduces the bit line resistance provides an effect of improving the characteristics of the semiconductor device.

Description

Semiconductor device and method for forming the same

The present invention relates to a semiconductor device and a method of forming the same, and more particularly, to a semiconductor device and a method of forming the semiconductor device and a method for forming a margin between the storage electrode contact and the active region and to prevent the neighboring storage electrode contact from being bridged. .

Most modern electronic appliances are equipped with semiconductor devices. The semiconductor device includes electronic elements such as transistors, resistors, and capacitors, which are designed to perform partial functions of the electronic products and then integrated on a semiconductor substrate. For example, electronic products such as a computer or a digital camera include semiconductor devices such as a memory chip for storing information and a processing chip for controlling information, and the memory chip and the processing chip are semiconductors. And the electronic components integrated on a substrate.

On the other hand, the semiconductor devices need to be increasingly integrated in order to meet the excellent performance and low price required by the consumer. As the degree of integration of semiconductor memory devices increases, design rules decrease, and the pattern of semiconductor devices becomes smaller. As miniaturization and high integration of a semiconductor device progresses, the overall chip area increases in proportion to an increase in memory capacity, but the area of a cell area where a semiconductor device pattern is formed is actually decreasing. Therefore, in order to secure a desired memory capacity, more patterns must be formed in a limited cell region, so that a fine pattern with a reduced critical dimension of the pattern must be formed.

A method of forming a fine pattern includes a method of using a phase shift mask as an exposure mask or a method of forming a separate thin film on the wafer to improve image contrast. a contrast enhancement layer (CEL) method, a tri layer resister (hereinafter referred to as a TLR) method having an intermediate layer such as spin on glass (SOG) between two layers of photoresist, or an upper side of the photoresist. Silicate methods for selectively injecting silicon have been developed to lower the resolution limit.

On the other hand, the contact connecting the upper and lower conductive wiring is significantly affected by the design rule compared to the line / space pattern. In other words, as the device becomes highly integrated, as the size of the device decreases and the distance between the peripheral wiring decreases, the aspect ratio, which is a ratio of the diameter and the depth of the contact, increases, thereby forming a contact. It is important in the method of forming the device. Therefore, in the highly integrated semiconductor device having the multilayer conductive wiring, a precise and strict alignment between the masks is required in the contact forming process, so that the process margin is reduced or the process must be performed without margin.

In particular, in semiconductor devices including buried gates, various methods have been proposed to increase contact resistance and to secure a margin by reducing the area where the storage electrode contact is connected to the active region due to high integration. After forming, there is a method of expanding the width of the storage electrode contact hole by performing wet etching. However, there is a problem that the storage inter-electrode contact membrane may be damaged by the wet etchant, thereby causing the bridge between the storage electrode contacts.

1A and 1B are cross-sectional views illustrating a method of forming a semiconductor device according to the prior art.

As shown in FIG. 1A, a buried gate predetermined region (not shown) is formed in the semiconductor substrate 10 on which the active region 14 defined by the device isolation layer 12 is formed. Subsequently, after depositing an oxide film on the entire surface, the gate electrode 16 is deposited on the entire surface including the oxide film. In this case, the gate electrode 16 is deposited such that the buried gate predetermined region (not shown) is buried. Next, the interlayer insulating layer 18 is formed on the entire surface, and the photoresist layer pattern (not shown) defining the bit line contact region (not shown) is used as an etch mask to expose the active region 14. Etch Subsequently, a bit line contact spacer 20 is formed on the sidewall of the interlayer insulating layer 18, and a polysilicon layer 28 is deposited on the entire surface including the bit line contact predetermined region (not shown) to form the bit line contact 22. ).

As shown in FIG. 1B, the bit line electrode 24 and the hard mask layer 26 are formed over the entirety including the bit line contact 22. Subsequently, a photoresist pattern (not shown) defining a bit line is patterned with an etching mask to form a bit line. Subsequently, after the interlayer insulating layer (not shown) is formed over the entirety including the bit lines, the interlayer insulating layer (not shown) is etched using a photoresist pattern (not shown) defining the storage electrode contact hole as an etch mask, thereby storing the storage electrode. The contact hole 28 is formed. Here, the storage electrode contact hole 28 is formed to secure the overlap margin of the active region and the storage electrode contact, and then wet etching is performed to extend the lower portion of the storage electrode contact hole 28. In this case, when the over-etching is performed during the wet etching, the interlayer insulating layer 18 is etched to cause the low electrode contact hole 28 to be bridged as in 'A'.

The present invention is to solve the problem of deterioration of the semiconductor device by increasing the resistance of the storage electrode contact by reducing the area is connected to the storage electrode contact and the active region due to the high integration.

The semiconductor device of the present invention includes a semiconductor substrate including an active region defined as an isolation layer, a line type interlayer insulating film provided on the semiconductor substrate and spaced apart from each other by a first width and a second width on the same line, And spacers formed on sidewalls of the interlayer insulating layer spaced apart by one width and embedded between the interlayer insulating layers spaced apart by the second width.

In this case, the area spaced apart from the first width may be connected to the active area.

The region spaced apart from the second width may be connected to the device isolation layer.

The first width is larger than the second width.

The spacer is characterized in that it comprises a nitride film.

The semiconductor device may further include a buried gate provided in the semiconductor substrate.

The semiconductor device may further include bit line contacts embedded between spacers formed on the sidewalls of the interlayer insulating layer spaced apart from the first width.

And a bit line connected to the bit line contact.

A method of forming a semiconductor device according to the present invention includes forming an active region defined as an isolation layer in a semiconductor substrate, and forming an interlayer insulating film of a line type spaced apart from each other by a first width and a second width on the same line on the semiconductor substrate. And forming spacers formed on sidewalls of the interlayer insulating layer spaced apart from the first width and buried between the interlayer insulating layers spaced apart from the second width.

The method may further include forming a buried gate after the forming of the active region.

The forming of the line type interlayer insulating film spaced apart from the first width and the second width may include forming an interlayer insulating film on the semiconductor substrate and connecting the active region on the same line on the interlayer insulating film. And forming a photoresist pattern spaced apart from the first width and connected to the device isolation layer to be spaced apart from the second width, and etching the interlayer insulating layer using the photoresist pattern as an etch mask. do.

The etching of the interlayer dielectric layer using the photoresist pattern as an etch mask may define a bit line contact region of a dogbone shape.

The first width may be larger than the second width.

The forming of the spacers may include forming a nitride film.

And forming a bit line contact by filling a polysilicon layer between spacers formed on sidewalls of the interlayer insulating layer spaced apart from the first width after the forming of the spacers.

The method may further include forming a bit line connected to the bit line contact after the forming of the bit line contact.

The method may further include forming a storage electrode contact hole connected to the active region after the forming of the bit line.

The method may further include performing wet etching on the storage electrode contact hole after the forming of the storage electrode contact hole.

The present invention provides an effect of effectively increasing the area where the storage electrode contact is connected to the active region and increasing the overall cross section of the bit line to reduce the bit line resistance to improve the characteristics of the semiconductor device.

1A and 1B are cross-sectional views illustrating a method of forming a semiconductor device according to the prior art.
2 is a cross-sectional view showing a semiconductor device according to the present invention.
3A and 3B are cross-sectional views illustrating a method of forming a semiconductor device in accordance with the present invention.

Hereinafter, with reference to the accompanying drawings in accordance with an embodiment of the present invention will be described in detail.

2 is a cross-sectional view illustrating a semiconductor device according to the present invention, and FIGS. 3A and 3B are cross-sectional views illustrating a method of forming a semiconductor device according to the present invention.

As shown in FIG. 2, a semiconductor device according to the present invention includes a first width W1 and a second width W on a semiconductor substrate 100 including an active region 104 defined by an isolation layer 102. A bit line interposed between the interlayer insulating film 108 spaced apart from W2) and the interlayer insulating film 108 formed on the sidewalls of the interlayer insulating film 108 spaced apart from the first width W1 and spaced apart from the second width W2. And a contact spacer 110. The bit line contact 112 and the bit line contact 112 defined by polysilicon embedded between the bit line contact spacers 110 formed on the sidewalls of the interlayer insulating layer 108 spaced apart from the first width W1 are formed. And a bit line connected to the storage line and a storage electrode contact plan region 118 connected to the active region 104. Here, the storage electrode contact planar region 118 is spaced apart by the bit line contact spacers 110 embedded in the pattern having the second width W2 to perform wet cleaning to expand the storage electrode contact planar region 118. In this case, it may be prevented from being excessively etched by the bit line contact spacers 110 to be bridged between neighboring storage electrode contact planar regions 118.

As shown in FIG. 3A, a buried gate predetermined region (not shown) is formed in the semiconductor substrate 100 on which the active region 104 defined by the device isolation layer 102 is formed. Subsequently, after the oxide film is deposited on the entire surface, the gate electrode 106 is deposited on the entire surface including the oxide film. In this case, the gate electrode 106 is deposited such that the buried gate predetermined region (not shown) is buried.

Next, the interlayer insulating film 108 is formed over the entire surface and the photoresist pattern (not shown) defining a bit line contact region (not shown) is used as an etch mask to expose the active region 104. Etch In this case, the bit line contact region is preferably formed in a line type. More specifically, it is preferable that it is a line type of dog bone form. Here, the dog bone shape refers to a pattern in which a pattern having a first width W1 and a pattern having a second width W2 and W2 <W1 having a width smaller than the first width W1 are continuously arranged. The pattern having the width W1 is preferably provided to be connected to the active region, and the pattern having the second width W2 is preferably provided to be connected to the device isolation film.

Next, a bit line contact spacer 110 is formed on the upper portion of the interlayer insulating layer 108. In this case, the bit line contact spacer 110 may be a nitride film. Here, when the bit line contact spacer 110 is formed in the interlayer insulating film 108 spaced apart from the first width W1, the bit line contact spacer 110 may be formed only on the sidewall of the interlayer insulating film 108, and the second width W2 may be used. In the case of the interlayer insulating film 108 spaced apart from each other, it is preferable to be entirely embedded in portions spaced apart from the second width W2. That is, since the second width W2 is smaller than the first width W1, the second width W2 is preferably filled by the bit line contact spacer 110. Subsequently, the bit line contact spacer 110 is etched to expose the active region 104 through spacer etching. It is preferable that only the bit line contact spacer 110 remaining on the semiconductor substrate is removed through the spacer etching process. That is, in the case of the bit line contact spacers 110 formed on the interlayer insulating layer 108 spaced apart from the first width W1, the bit line contact spacers 110 remain only on the sidewalls of the interlayer insulating layer 108. Preferably, the bit line contact spacers 110 formed in the interlayer insulating layer 108 spaced apart from each other by the second width W2 are partially etched and buried as 'B'. Subsequently, after the polysilicon layer is deposited on the entire surface including the bit line contact region (not shown), the planar etching process is performed to form the bit line contact 112.

As shown in FIG. 3B, the bit line electrode 114 and the hard mask layer 116 are formed over the entire area including the bit line contact 112. Subsequently, a photoresist pattern (not shown) defining a bit line is patterned with an etching mask to form a bit line. Subsequently, after the interlayer insulating layer (not shown) is formed over the entirety including the bit lines, the interlayer insulating layer (not shown) is etched using a photoresist pattern (not shown) defining the storage electrode contact hole as an etch mask, thereby storing the storage electrode. The contact hole 118 is formed. In addition, wet etching is performed to secure an overlap margin between the active region and the storage electrode contact to extend a lower portion of the storage electrode contact hole 118. In the present invention, even if wet etching is performed to secure overlap margin between the active region and the storage electrode contact, the neighboring storage electrode contacts are adjacent to each other by the bit line contact spacer 110 embedded in the line type bit line contact predetermined region. It can fundamentally prevent it from being bridged.

As described above, in the formation of a semiconductor device including a buried gate, a bit line contact formed as a line type even when wet etching is performed to improve overlap margin between the active region and the storage electrode contact during the storage electrode contact. It is not excessively etched by the bit line spacer embedded in the predetermined region, thereby providing an effect of fundamentally preventing a problem of neighboring storage electrode contacts being bridged.

Claims (18)

A semiconductor substrate including an active region defined as an isolation layer;
A line type interlayer insulating film provided on the semiconductor substrate and spaced apart from each other by a first width and a second width on the same line; And
A spacer formed on sidewalls of the interlayer insulating layer spaced apart from the first width, and embedded between the interlayer insulating layers spaced apart from the second width;
And a bit line contact buried between spacers formed on sidewalls of the interlayer insulating layer spaced apart from the first width. Claim 2 has been abandoned due to the setting registration fee. The method according to claim 1,
The area spaced by the first width
And a semiconductor device connected to the active region. Claim 3 was abandoned when the setup registration fee was paid. The method according to claim 1,
The area spaced apart by the second width
And a device connected to the device isolation film. Claim 4 was abandoned when the registration fee was paid. The method according to claim 1,
And the first width is greater than the second width. Claim 5 was abandoned upon payment of a set-up fee. The method according to claim 1,
The spacer
A semiconductor device comprising a nitride film. Claim 6 was abandoned when the registration fee was paid. The method according to claim 1,
And a buried gate provided in the semiconductor substrate. delete Claim 8 was abandoned when the registration fee was paid. The method according to claim 1,
And a bit line connected to the bit line contact. Forming an active region defined as an isolation layer in the semiconductor substrate;
Forming an interlayer insulating film of a line type spaced apart from each other by a first width and a second width on the same line on the semiconductor substrate; And
Forming spacers formed on sidewalls of the interlayer insulating layer spaced apart from the first width and buried between the interlayer insulating layers spaced apart from the second width;
After forming the spacer
And forming a bit line contact by filling a polysilicon layer between spacers formed on the sidewalls of the interlayer insulating layer spaced apart from the first width. Claim 10 was abandoned upon payment of a setup registration fee. The method according to claim 9,
After forming the active region
Forming a buried gate further comprises the step of forming a semiconductor device. Claim 11 was abandoned upon payment of a setup registration fee. The method according to claim 9,
Forming a line type interlayer insulating film spaced apart from the first width and the second width is
Forming an interlayer insulating film on the semiconductor substrate;
Forming a photoresist pattern on the interlayer insulating layer, the photosensitive layer pattern being connected to the active region on the same line and spaced apart from the first width, and connected to the device isolation layer and spaced apart from the second width; And
And etching the interlayer dielectric layer using the photoresist pattern as an etch mask. Claim 12 is abandoned in setting registration fee. The method of claim 11,
Etching the interlayer dielectric layer using the photoresist pattern as an etch mask
A method of forming a semiconductor device, characterized in that a bit line contact region of a dogbone shape is defined. Claim 13 was abandoned upon payment of a registration fee. The method according to claim 9,
And the first width is greater than the second width. Claim 14 has been abandoned due to the setting registration fee. The method according to claim 9,
Forming the spacer
A method of forming a semiconductor device, characterized in that formed from a nitride film. delete Claim 16 has been abandoned due to the setting registration fee. The method according to claim 9,
After forming the bitline contact
Forming a bit line connected to the bit line contact. Claim 17 has been abandoned due to the setting registration fee. The method according to claim 16,
After forming the bit line
And forming a storage electrode contact hole connected to the active region. Claim 18 was abandoned upon payment of a set-up fee. 18. The method of claim 17,
After forming the storage electrode contact hole
And performing a wet etching on the storage electrode contact hole.

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