CN104701250A - Manufacturing method of array substrate and array substrate - Google Patents
Manufacturing method of array substrate and array substrate Download PDFInfo
- Publication number
- CN104701250A CN104701250A CN201510094449.3A CN201510094449A CN104701250A CN 104701250 A CN104701250 A CN 104701250A CN 201510094449 A CN201510094449 A CN 201510094449A CN 104701250 A CN104701250 A CN 104701250A
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- CN
- China
- Prior art keywords
- via hole
- hole
- array base
- base palte
- manufacture method
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Manufacture Of Switches (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The invention discloses a manufacturing method of an array substrate. The method comprises the steps of pre-etching, namely, etching to form a through hole from the first layer of the upper surface of the substrate to the array substrate until the through hole extends to metal layer which is to be electrically connected; etching for the second time, namely, etching the through hole for the second time to enable at least one side edge of the through hole to extend until crossing one side edge of the metal layer so as to form a through hole; depositing an electrode layer, and connecting the metal layer with the corresponding metal part. The invention further discloses an array substrate manufactured by the method. According to the method, at least one side edge of the through hole in the array substrate extends until crossing one side edge of the metal layer so as to form the through hole, liquid in the through hole is easily blown out through an air knife without residue; the electrode layer in depositing can be in complete contact with the metal layer, and therefore, unqualified products can be avoided.
Description
Technical field
The present invention relates to display floater and manufacture field, particularly relate to a kind of manufacture method and array base palte of array base palte.
Background technology
In the array base palte preparation technology of display panels, via hole technique is a very important technique, usually various level exposed metal/bare metal will be positioned at by via hole technique in array base palte, then ITO (tin indium oxide) material is utilized to be connected by the exposed part being positioned at various level metal by subsequent technique, the metal that maybe will be positioned at same level connects, the formation etc. of the matrix structure of such as, connection between the gate line of array base palte and data wire, the connection between data wire and pixel electrode and public electrode wire.The quality of via hole technique directly has influence on the yield of product and the correlated performance of final panel.
The design of current design via hole is all dug a hole formula, as depicted in figs. 1 and 2, the surrounding of via hole 1 has silicon nitride enclosure wall 2 to block, in wet process process, air knife not easily dries up via hole 1 like this, as shown in Figure 3, easily at the position residual liquid of via hole 1, during ITO one-tenth ito film 3, the metal level (in figure data layer and data line layer) of ito film 3 with lower floor separates by residual liquid 4, and the phenomenon causing ito film 3 and metal level to disconnect, causes the display of panel bad.
Summary of the invention
In view of the deficiency that prior art exists, the invention provides a kind of manufacture method and array base palte of the array base palte bad because of liquid residue generation Display panel.
In order to realize above-mentioned object, present invention employs following technical scheme:
A manufacture method for array base palte, comprising:
Pre-etching, carries out etching from the ground floor array substrate of upper surface of base plate and forms via hole, until described via hole extends to the metal level needing electrical connection;
Secondarily etched, described via hole is etched again, makes at least one edge of described via hole extend beyond an edge of described metal level, form through hole;
Depositing electrode layers, connects described metal level and corresponding metallic member.
Wherein, described via hole comprises at least two elongated slots or elongated hole intersected.
Wherein, described via hole is " ten " font groove or hole of intersecting.
Wherein, described via hole is multiple.
Wherein, described metal level is data wire metal layer.
Wherein, the opening of described via hole broadens to end face gradually from bottom surface.
Wherein, the sidewall of described ground floor is run through at least one end of described via hole.
Present invention also offers a kind of array base palte, use above-mentioned manufacture method manufacture to form.
At least one edge of the via hole of array base palte is extended beyond an edge of metal level by the present invention, form through hole, liquid does not easily produce residual through air knife blowout two in via hole content, can guarantee contact completely with metal level in electrode layer deposition process, avoid the generation of defective products.
Accompanying drawing explanation
Fig. 1 is the array base-plate structure schematic diagram of prior art.
Fig. 2 is a cross-sectional view of Fig. 1.
Fig. 3 be the via hole of Fig. 1 bad time structural representation.
Fig. 4 is the manufacture method schematic diagram of the array base palte of the embodiment of the present invention one
Fig. 5 is the array base-plate structure schematic diagram of the embodiment of the present invention one.
Fig. 6 is a cross-sectional view of the array base palte of Fig. 5.
Fig. 7 is the cross-sectional view of the array base palte of the embodiment of the present invention two.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is described in more detail.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
Embodiment one
Composition graphs 4 ~ Fig. 6, the manufacture method of array base palte of the present invention, comprises the steps:
S01: etch in advance, carries out etching from ground floor 12 array substrate of upper surface of base plate and forms via hole 11, until via hole 11 extends to the metal level 10 needing electrical connection;
S02: secondarily etched, etches again to via hole 11, makes at least one edge of via hole 11 extend beyond an edge of metal level 10, forms through hole;
S03: depositing electrode layers 13, connection metal layer 10 and corresponding metallic member.Here, electrode layer 13 is ito thin film layer.
Because the via hole 11 of the present embodiment is through hole, in air knife air blowing process, gas enters from via hole 11 upper surface, then blow out from via hole 11 lower surface, residual liquid in via hole 11 is blown out thereupon, thus be easy to air-dry, can not cause producing in the process of depositing electrode layers 13 bad due to liquid residue.
In order to ensure that the Liquid Residue physical efficiency in wet process process in via hole 11 blows out better, via hole 11 comprises at least two elongated slots or elongated hole that intersect, and the via hole 11 of the present embodiment is " ten " font intersected.Like this, in air knife air blowing process, the liquid in via hole 11 can blow out from via hole 11 lower surface on the one hand, on the other hand, and can also from the different sides blowout of " ten " word groove of via hole 11.
In order to realize the electrical connection of different metal part, via hole 11 can be multiple.The metal level 10 of the present embodiment is data wire metal layer.
Further, the opening of via hole 11 can be set to broaden gradually to end face from bottom surface.The air that air knife is blown into can be blown into along the hole wall tilted better, and meanwhile, residual liquid oppositely can also blow out along the hole wall tilted by the gas be blown into, and reaches the effect thoroughly removed.
The present embodiment additionally provides a kind of array base palte, utilizes above-mentioned manufacture method manufacture to form, and effectively prevent the residual of liquid in via hole 11, reduces the fraction defective of substrate and display floater.
Embodiment two
As shown in Figure 7, with embodiment one unlike, the sidewall of ground floor 12 is run through at least one end of the via hole 11 of the present embodiment, and the Liquid Residue physical efficiency in via hole 11 flows out from the side run through along air-flow.
Below be only the embodiment of the application; it should be pointed out that for those skilled in the art, under the prerequisite not departing from the application's principle; can also make some improvements and modifications, these improvements and modifications also should be considered as the protection range of the application.
Claims (8)
1. a manufacture method for array base palte, is characterized in that, comprising:
Pre-etching, carries out etching from ground floor (12) array substrate of upper surface of base plate and forms via hole (11), until described via hole (11) extends to the metal level (10) needing electrical connection;
Secondarily etched, described via hole (11) is etched again, makes at least one edge of described via hole (11) extend beyond an edge of described metal level (10), form through hole;
Depositing electrode layers (13), connects described metal level (10) and corresponding metallic member.
2. the manufacture method of array base palte according to claim 1, is characterized in that, described via hole (11) comprises at least two elongated slots or elongated hole that intersect.
3. the manufacture method of array base palte according to claim 2, is characterized in that, described via hole (11) is " ten " font groove or hole of intersecting.
4. the manufacture method of array base palte according to claim 1, is characterized in that, described via hole (11) is for multiple.
5. the manufacture method of array base palte according to claim 1, is characterized in that, described metal level (10) is data wire metal layer.
6. the manufacture method of array base palte according to claim 1, is characterized in that, the opening of described via hole (11) broadens to end face gradually from bottom surface.
7., according to the manufacture method of the arbitrary described array base palte of claim 1-6, it is characterized in that, the sidewall of described ground floor (12) is run through at least one end of described via hole (11).
8. an array base palte, is characterized in that, uses the arbitrary described manufacture method manufacture of claim 1-7 to form.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510094449.3A CN104701250B (en) | 2015-03-03 | 2015-03-03 | The preparation method and array base palte of a kind of array base palte |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510094449.3A CN104701250B (en) | 2015-03-03 | 2015-03-03 | The preparation method and array base palte of a kind of array base palte |
Publications (2)
| Publication Number | Publication Date |
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| CN104701250A true CN104701250A (en) | 2015-06-10 |
| CN104701250B CN104701250B (en) | 2018-01-16 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109643657A (en) * | 2017-06-22 | 2019-04-16 | 深圳市柔宇科技有限公司 | The production method of the making apparatus and array substrate of array substrate |
| CN110676264A (en) * | 2019-09-09 | 2020-01-10 | 深圳市华星光电技术有限公司 | Pixel electrode contact hole design |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01274451A (en) * | 1988-04-26 | 1989-11-02 | Nec Ic Microcomput Syst Ltd | Semiconductor integrated circuit |
| US20050231674A1 (en) * | 2004-04-15 | 2005-10-20 | Joji Nishimura | Liquid crystal display device, method of manufacturing the same, and electronic apparatus |
| US20100127263A1 (en) * | 2008-11-26 | 2010-05-27 | Chang-Deok Lee | Liquid crystal display device and method of manufacturing the same |
-
2015
- 2015-03-03 CN CN201510094449.3A patent/CN104701250B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01274451A (en) * | 1988-04-26 | 1989-11-02 | Nec Ic Microcomput Syst Ltd | Semiconductor integrated circuit |
| US20050231674A1 (en) * | 2004-04-15 | 2005-10-20 | Joji Nishimura | Liquid crystal display device, method of manufacturing the same, and electronic apparatus |
| US20100127263A1 (en) * | 2008-11-26 | 2010-05-27 | Chang-Deok Lee | Liquid crystal display device and method of manufacturing the same |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109643657A (en) * | 2017-06-22 | 2019-04-16 | 深圳市柔宇科技有限公司 | The production method of the making apparatus and array substrate of array substrate |
| CN109643657B (en) * | 2017-06-22 | 2022-08-16 | 深圳市柔宇科技股份有限公司 | Manufacturing equipment and manufacturing method of array substrate |
| CN110676264A (en) * | 2019-09-09 | 2020-01-10 | 深圳市华星光电技术有限公司 | Pixel electrode contact hole design |
| CN110676264B (en) * | 2019-09-09 | 2021-11-23 | Tcl华星光电技术有限公司 | Pixel electrode contact hole design |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104701250B (en) | 2018-01-16 |
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