CN104701250B - The preparation method and array base palte of a kind of array base palte - Google Patents
The preparation method and array base palte of a kind of array base palte Download PDFInfo
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- CN104701250B CN104701250B CN201510094449.3A CN201510094449A CN104701250B CN 104701250 B CN104701250 B CN 104701250B CN 201510094449 A CN201510094449 A CN 201510094449A CN 104701250 B CN104701250 B CN 104701250B
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- Prior art keywords
- array base
- base palte
- metal level
- preparation
- edge
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- 238000002360 preparation method Methods 0.000 title claims abstract description 18
- 239000002184 metal Substances 0.000 claims abstract description 32
- 229910052751 metal Inorganic materials 0.000 claims abstract description 32
- 238000005530 etching Methods 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000000151 deposition Methods 0.000 claims abstract description 5
- 239000007788 liquid Substances 0.000 abstract description 12
- 238000000034 method Methods 0.000 abstract description 10
- 230000002950 deficient Effects 0.000 abstract description 3
- 238000005137 deposition process Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 238000007664 blowing Methods 0.000 description 2
- 230000000875 corresponding effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910003437 indium oxide Inorganic materials 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical class [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Manufacture Of Switches (AREA)
Abstract
The invention discloses a kind of preparation method of array base palte, including：Pre-etching, perform etching to form via from the first layer array substrate of upper surface of base plate, until the via extends to the metal level for needing to electrically connect；It is secondarily etched, the via is etched again, at least one edge of the via is extended beyond an edge of the metal level, forms through hole；Depositing electrode layer, connect the metal level and corresponding metal part.The invention also discloses a kind of array base palte manufactured using this method.The present invention extends beyond at least one edge of the via of array base palte at one edge of metal level, form through hole, liquid does not easily produce residual in via content by air knife blowout two, it can be ensured that can be completely attached in electrode layer deposition process with metal level, avoid the generation of defective products.
Description
Technical field
The present invention relates to the preparation method and array base palte of display panel manufacturing field, more particularly to a kind of array base palte.
Background technology
In the array base palte preparation technology of liquid crystal display panel, via technique is a critically important technique, array base
ITO (indium oxides are then utilized by subsequent technique by positioned at the exposed metal/bare metal of different levels generally by via technique in plate
Tin) material is by the exposed part connection positioned at the metal of different levels, or will be connected positioned at the metal of same level, such as array
The matrix of connection between connection, data wire and pixel electrode and public electrode wire between the gate line and data wire of substrate
Formation of structure etc..The quality of via technique directly influences the yield of product and the correlated performance of final panel.
The design of design via is all dug a hole formula at present, and as depicted in figs. 1 and 2, the surrounding of via 1 has silicon nitride to enclose
Wall 2 blocks, and air knife is not easy to dry up via 1 so during wet process, as shown in figure 3, easily in the position Liquid Residue of via 1
Body, when ITO is into ito film 3, residual liquid 4 separates ito film 3 and the metal level (data layers are data line layer in figure) of lower floor, leads
The phenomenon for causing ito film 3 to be disconnected with metal level, causes the display of panel bad.
The content of the invention
In view of the shortcomings of the prior art, the invention provides a kind of because liquid residue produces the bad battle array of Display panel
The preparation method and array base palte of row substrate.
In order to realize above-mentioned purpose, present invention employs following technical scheme：
A kind of preparation method of array base palte, including：
Pre-etching, perform etching to form via from the first layer array substrate of upper surface of base plate, until the via prolongs
Extend the metal level for needing to electrically connect；
It is secondarily etched, the via is etched again, at least one edge of the via is extended beyond institute
An edge of metal level is stated, forms through hole；
Depositing electrode layer, connect the metal level and corresponding metal part.
Wherein, the via includes the elongated slot or elongated hole of at least two intersections.
Wherein, the via is " ten " font groove intersected or hole.
Wherein, the via is multiple.
Wherein, the metal level is data wire metal layer.
Wherein, the opening of the via gradually broadens from bottom surface to top surface.
Wherein, the side wall of the first layer is run through at least one end of the via.
Present invention also offers a kind of array base palte, is fabricated using above-mentioned preparation method.
The present invention extends beyond at least one edge of the via of array base palte at one edge of metal level, is formed logical
Hole, liquid easily do not produce residual in via content by air knife blowout two, it can be ensured that energy and metal in electrode layer deposition process
Layer completely attaches to, and avoids the generation of defective products.
Brief description of the drawings
Fig. 1 is the array base-plate structure schematic diagram of prior art.
Fig. 2 is a Fig. 1 cross-sectional view.
Fig. 3 is structural representation when Fig. 1 via is bad.
Fig. 4 is the preparation method schematic diagram of the array base palte of the embodiment of the present invention one
Fig. 5 is the array base-plate structure schematic diagram of the embodiment of the present invention one.
Fig. 6 is a cross-sectional view of Fig. 5 array base palte.
Fig. 7 is the cross-sectional view of the array base palte of the embodiment of the present invention two.
Embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, it is right below in conjunction with drawings and Examples
The present invention is further described.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and do not have to
It is of the invention in limiting.
Embodiment one
With reference to Fig. 4~Fig. 6, the preparation method of array base palte of the invention, comprise the following steps：
S01：Pre-etching, perform etching to form via 11 from the array substrate of first layer 12 of upper surface of base plate, until mistake
Hole 11 extends to the metal level 10 for needing to electrically connect；
S02：It is secondarily etched, via 11 is etched again, at least one edge of via 11 is extended beyond gold
Belong to an edge of layer 10, form through hole；
S03：Depositing electrode layer 13, connect metal level 10 and corresponding metal part.Here, electrode layer 13 is ito thin film
Layer.
Because the via 11 of the present embodiment is through hole, in air knife air blowing process, gas enters from the upper surface of via 11, then
Blown out from the lower surface of via 11, the residual liquid in via 11 is blown out therewith, will not be residual due to liquid so as to be easy to air-dry
Stay and cause to produce during depositing electrode layer 13 bad.
In order to ensure preferably to blow out in the residual liquid during wet process in via 11, via 11 includes at least two
The elongated slot or elongated hole that bar intersects, the via 11 of the present embodiment are " ten " font intersected.So, in air knife air blowing process, mistake
On the one hand liquid in hole 11 can blow out from the lower surface of via 11, another aspect, moreover it is possible to from " ten " the word groove of via 11 not
Homonymy is blown out.
In order to realize the electrical connection of different metal part, via 11 can be multiple.The metal level 10 of the present embodiment is number
According to line metal level.
Further, the opening of via 11 could be arranged to gradually broaden from bottom surface to top surface.The air that air knife is blown into can
To be preferably blown into along inclined hole wall, meanwhile, the gas being blown into can also be reverse by the liquid of residual along inclined hole wall
Blowout, the effect of reaching thorough removing.
The present embodiment additionally provides a kind of array base palte, is fabricated using above-mentioned preparation method, effectively prevent via
The residual of liquid in 11, reduce the fraction defective of substrate and display panel.
Embodiment two
As shown in fig. 7, unlike embodiment one, at least one end of the via 11 of the present embodiment is through first layer 12
Side wall, residual liquid in via 11 can along air-flow from through side outflow.
It the above is only the embodiment of the application, it is noted that come for those skilled in the art
Say, on the premise of the application principle is not departed from, some improvements and modifications can also be made, these improvements and modifications also should be regarded as
The protection domain of the application.
Claims (7)
- A kind of 1. preparation method of array base palte, it is characterised in that including：Pre-etching, perform etching to form via (11) from first layer (12) array substrate of upper surface of base plate, until the mistake Hole (11) extends to the metal level (10) for needing to electrically connect；It is secondarily etched, the via (11) is etched again, at least one edge of the via (11) is extended to more An edge of the metal level (10) is crossed, forms through hole, and makes at least one edge of the via (11) through described The side wall of first layer (12)；Depositing electrode layer (13), connect the metal level (10) and corresponding metal part.
- 2. the preparation method of array base palte according to claim 1, it is characterised in that the via (11) includes at least two The elongated slot or elongated hole that bar intersects.
- 3. the preparation method of array base palte according to claim 2, it is characterised in that the via (11) is intersection " ten " font groove or hole.
- 4. the preparation method of array base palte according to claim 1, it is characterised in that the via (11) is multiple.
- 5. the preparation method of array base palte according to claim 1, it is characterised in that the metal level (10) is data wire Metal level.
- 6. the preparation method of array base palte according to claim 1, it is characterised in that the opening of the via (11) is the bottom of from Face gradually broadens to top surface.
- 7. a kind of array base palte, it is characterised in that usage right requires that any described preparation methods of 1-6 are fabricated.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510094449.3A CN104701250B (en) | 2015-03-03 | 2015-03-03 | The preparation method and array base palte of a kind of array base palte |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510094449.3A CN104701250B (en) | 2015-03-03 | 2015-03-03 | The preparation method and array base palte of a kind of array base palte |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104701250A CN104701250A (en) | 2015-06-10 |
| CN104701250B true CN104701250B (en) | 2018-01-16 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201510094449.3A Active CN104701250B (en) | 2015-03-03 | 2015-03-03 | The preparation method and array base palte of a kind of array base palte |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018232698A1 (en) * | 2017-06-22 | 2018-12-27 | 深圳市柔宇科技有限公司 | Apparatus for manufacturing array substrate and method for manufacturing array substrate |
| CN110676264B (en) * | 2019-09-09 | 2021-11-23 | Tcl华星光电技术有限公司 | Pixel electrode contact hole design |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01274451A (en) * | 1988-04-26 | 1989-11-02 | Nec Ic Microcomput Syst Ltd | Semiconductor integrated circuit |
| JP4293038B2 (en) * | 2004-04-15 | 2009-07-08 | セイコーエプソン株式会社 | Liquid crystal device and electronic device |
| KR101392268B1 (en) * | 2008-11-26 | 2014-05-08 | 엘지디스플레이 주식회사 | Pad array of liquid crystal display device |
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| CN104701250A (en) | 2015-06-10 |
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