CN111463243A - Array substrate and preparation method thereof - Google Patents

Abstract

The present invention provides an array substrate and a preparation method thereof. The array substrate includes a display area and a non-display area surrounding the display area, the non-display area has a bending area, and the array substrate further includes a flexible substrate, a buffer layer, a thin film transistor structure layer, a groove, a via hole, a metal trace and a flat layer, wherein a part of the metal trace is filled in the via hole and extends from the side of the thin film transistor structure layer away from the buffer layer, Forming source and drain lines; part of the metal lines covering the groove walls of the grooves and extending the side of the thin film transistor structure layer away from the buffer layer to form source and drain lines.

Description

Array substrate and preparation method thereof

technical field

The present application relates to the field of display technology, and in particular, to an array substrate and a preparation method thereof.

Background technique

OLED (Organic Light-Emitting Diode, Organic Light Emitting Diode) is a display technology developed in recent years. Compared with liquid crystal displays, it has high contrast ratio, high response, low energy consumption, flexibility, self-luminescence, wide viewing angle and response speed. It has a wide range of application prospects and has important research significance. AMOLED (ActiveMatrix/Organic Light Emitting Diode) has become an outstanding representative of the next-generation display technology with its advantages of being thin, flexible, non-fragile, and wearable.

In order to improve the bending performance of the bending area of the display panel, the inorganic film layer is often removed in the industry, and correspondingly, an organic film layer with less stress is used to improve the bending performance of the product.

Specifically, the display panel includes an array substrate, and the array substrate includes a display area (Active Area, AA area) and a non-display area, wherein the non-display area includes a bending area, that is, a terminal area (pad area). A deep hole area (Deep Hole, DH) is provided in the terminal area, and the DH hole is filled with organic materials, so that the terminal area is easy to bend. However, in order to prevent the deep hole area (DH) from being too deep and the taper angle (taper) being too steep, the source and drain traces (SD) at the edge of the bending area are at risk of breakage or residual risk. In the area, the inorganic film layer is removed by multi-step etching, and a retardation layer is formed at the taper to prevent the SD trace from breaking.

At present, in order to realize the design of two tapers in the pad area, two mask processes are needed to realize the DH groove with a slope, and a mask needs to be used to fill the DH groove with organic materials. Therefore, the formation of the existing array substrate requires an etching process shielded by multiple masks, which is complicated in process, high in cost and low in productivity.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide an array substrate and a preparation method thereof, so as to solve the technical problems of complicated formation process, high cost and low productivity of the existing array substrate.

In order to achieve the above object, the present invention provides an array substrate including a display area and a non-display area surrounding the display area, the non-display area has a bending area, and a flexible substrate extending from the display area to the non-display area; a buffer layer disposed on the flexible substrate and extending from the display area to the non-display area; a thin film transistor structure layer disposed on the buffer layer and extending from the display area the thin film transistor structure layer has a groove, which is arranged in the bending region and extends from the side of the thin film transistor structure layer away from the buffer layer into the buffer layer; and a via hole, which is arranged in the display area and extends from the side of the thin film transistor structure layer away from the buffer layer into the thin film transistor structure layer; metal wiring, wherein part of the metal wiring is filled in the through hole In the hole and extending the side of the thin film transistor structure layer away from the buffer layer, a source and drain are formed; part of the metal traces cover the groove wall of the groove and extend the thin film transistor structure layer away from the buffer layer. On one side, source and drain traces are formed; and the array substrate further includes a flat layer covering the side of the thin film transistor structure layer away from the buffer layer and filling the groove.

Further, the depth of the groove is

Further, the flexible substrate includes: a first PI substrate; a first barrier layer disposed on the first PI substrate; a second PI substrate disposed on the first barrier layer; and a second barrier layer, arranged on the second PI substrate.

Further, the thickness of the second barrier layer is

Further, the thin film transistor structure layer includes: a first gate insulating layer disposed on the buffer layer and the active layer and extending from the display area to the non-display area; a first gate electrode , disposed on the first gate insulating layer and located in the display area; the second gate insulating layer, disposed on the first gate insulating layer and the first gate, from the display region extending to the non-display region; a second gate electrode disposed on the second gate insulating layer and located in the display region; and a dielectric layer disposed on the second gate insulating layer and the display region on the second gate, extending from the display area to the non-display area.

In order to achieve the above object, the present invention also provides a preparation method of an array substrate, comprising a display area and a non-display area surrounding the display area, the non-display area has a bending area, and the preparation method of the array substrate includes: The steps are as follows: forming a flexible substrate, the flexible substrate extending from the display area to the non-display area; forming a buffer layer on the flexible substrate, the buffer layer extending from the display area to the non-display area ; forming a thin film transistor structure layer on the buffer layer, the thin film transistor structure layer extending from the display area to the non-display area; forming a groove and a via hole, the groove is provided in the bending area , and extend from the side of the thin film transistor structure layer away from the buffer layer into the buffer layer; the via hole is arranged in the display area and extends from the upper surface of the thin film transistor structure layer to the buffer layer. In the thin film transistor structure layer; form metal traces, and some of the metal traces are filled in the via holes and extend the side of the thin film transistor structure layer away from the buffer layer to form a source and drain; some metal traces are covered on The groove wall of the groove extends the side of the thin film transistor structure layer away from the buffer layer to form source and drain traces; and a flat layer is formed, and the flat layer covers the upper surface of the thin film transistor structure layer and filled in the groove.

Further, in the step of forming grooves and via holes, a photomask is used to etch the thin film transistor structure layer to form the via holes and the grooves.

Further, the depth of the groove is

Further, the step of forming a flexible substrate further includes: forming a first PI substrate; forming a first barrier layer on the first PI substrate; forming a second PI substrate on the first barrier layer; and forming a second barrier layer on the second PI substrate; wherein the thickness of the second barrier layer is

Further, the step of forming a thin film transistor structure layer on the buffer layer includes: forming a first gate insulating layer on the buffer layer and the active layer, the first gate insulating layer extending from the display area to the non-display area; forming a first gate electrode on the first gate insulating layer, the first gate electrode being located in the display area; forming a second gate insulating layer on the On the first gate insulating layer and the first gate, the second gate insulating layer extends from the display area to the non-display area; forming a second gate on the second gate insulation layer, the second gate is located in the display area; and a dielectric layer is formed on the second gate insulating layer and the second gate, the dielectric layer extends from the display area to the non-display area.

The technical effect of the present invention is to provide an array substrate and a preparation method thereof. By thinning the second barrier layer and the dielectric layer, the overall film thickness of the array substrate is reduced, and a mask is used to cover the thin film transistors. Form vias and grooves on the structural layer, remove the organic materials in the existing grooves, and directly fill the grooves with a flat layer on the metal traces, which can make the metal traces closer to the neutral plane, which is beneficial to the terminal area bending performance. The manufacturing process of the array substrate is simpler, the consumption of raw materials is saved, and the production capacity is saved, which is favorable for mass production in the future and reduces the production cost.

Description of drawings

The technical solutions and other beneficial effects of the present application will be apparent through the detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings.

FIG. 1 is a schematic structural diagram of a conventional array substrate.

FIG. 2 is a schematic structural diagram of an array substrate according to an embodiment of the present application.

FIG. 3 is a flowchart of a method for fabricating an array substrate according to an embodiment of the present application.

FIG. 4 is a schematic structural diagram of an electronic device provided in an embodiment of the present application in a folded state.

FIG. 5 is a flow chart of forming a flexible substrate according to an embodiment of the present application.

FIG. 6 is a schematic structural diagram of a flat layer according to an embodiment of the present application.

FIG. 7 is a schematic structural diagram of the formation of the groove according to the embodiment of the present application.

The components in the drawings of the existing array substrate are identified as follows:

100 Existing array substrate; 1001 display area; 1002 bending area;

101 first PI substrate; 102 first barrier layer; 103 second PI substrate; 104 second barrier layer;

105 buffer layer; 106 thin film transistor structure layer; 107 flat layer;

108 anode layers; 109 pixel definition layers;

1061 first gate insulating layer; 1062 second gate insulating layer; 1063 dielectric layer;

111 active layer; 112 first gate; 113 second gate; 114 source and drain;

115 groove; 116 organic film layer; 117 metal trace;

115a is the first deep hole; 115b is the second deep hole.

The components in the drawings of the array substrate of the present application are identified as follows:

201 Display area; 202 Non-display area; 203 Bending area;

11 flexible substrate; 12 buffer layer; 13 thin film transistor structure layer; 14 via hole;

15 groove; 16 metal trace; 161 source and drain; 162 source and drain trace; 18 flat layer;

19 anodes; 20 pixel definition layers;

1101 the first PI substrate; 1102 the first barrier layer;

1103 second PI substrate; 1104 second barrier layer;

131 first gate insulating layer; 132 second gate insulating layer; 133 dielectric layer;

21 active layer; 22 first gate; 23 second gate; 24 support layer; 180 flat layer through hole.

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

The following disclosure provides many different embodiments or examples for implementing different structures of the present application. To simplify the disclosure of the present application, the components and arrangements of specific examples are described below. Of course, they are only examples and are not intended to limit the application. Furthermore, this application may repeat reference numerals and/or reference letters in different instances for the purpose of simplicity and clarity, and does not in itself indicate a relationship between the various embodiments and/or arrangements discussed. In addition, this application provides examples of various specific processes and materials, but one of ordinary skill in the art will recognize the application of other processes and/or the use of other materials.

As shown in FIG. 1 , the conventional array substrate 100 includes a display area 1001 and a bending area 1002 , and the bending area 1002 is a pad area. The existing array substrate 100 includes a first PI substrate 101, a first barrier layer 102, a second PI substrate 103, a second barrier layer 104, a buffer layer 105, a thin film transistor structure layer 106, a flat layer 107, Anode layer 108 , pixel definition layer 109 . The thin film transistor structure layer 106 includes a first gate insulating layer 1061 , a second gate insulating layer 1062 and a dielectric layer 1063 . The conventional array substrate 100 further includes an active layer 111 disposed on the buffer layer 105; a first gate 112 disposed on the first gate insulating layer 1061; and a second gate 113 disposed on the second gate insulating layer On; the source and drain electrodes 114 penetrate through the thin film transistor structure layer 106 and are connected to the active layer 111 . The existing array substrate 100 further includes a groove 115 , which penetrates through the thin film transistor structure layer 106 , the buffer layer 105 , and the second barrier layer 104 . The groove 115 includes a first deep hole 115a and a second deep hole 115b, and the two deep holes and part of the second PI substrate form the groove 115. In the process of preparing the grooves 115, after the buffer layer 105 is prepared, the buffer layer 105 and the second barrier layer 104 are etched with a first mask to form a first deep hole 115a, which penetrates the buffer layer 105 and the second barrier layer 104 ; after the thin film transistor structure layer 103 is prepared, a second mask is used to etch the thin film transistor structure layer 103 to form a second deep hole 115 b , which penetrates the insulating layer 106 . Therefore, the first deep hole 115 a and the second deep hole 115 b are combined to form the groove 115 . After the organic film layer 116 is formed by depositing an organic material in the groove 115, a third mask is used to mask the thin film transistor structure layer 106 to form a via hole, which penetrates to the active layer 111, and then a fourth mask is used to The metal material is deposited in the via hole and on the upper surface of part of the organic film layer 116 , the metal material forms the source and drain electrodes 114 in the via hole, and the metal material forms metal traces 117 on the upper surface of part of the organic film layer 116 . In general, the existing array substrate 100 includes at least 11 masking processes, specifically: the formation of the active layer 111 requires one masking process, and the formation of the first gate 112 and the second gate 113 requires two Masking process, the formation of the first deep hole 115a and the second deep hole 115b requires two masking processes, the formation of vias requires one masking process, and the formation of the source and drain 114 and the metal traces 117 requires one masking process , a mask process is required to form the through hole on the flat layer 107 , a mask process is required to form the anode layer 108 , and a mask process is required to form the pixel definition layer 109 . It can be seen that the process of the existing array substrate 100 is complicated and the productivity is low.

Therefore, the present embodiment provides an array substrate and a manufacturing method thereof to solve the above problems.

As shown in FIG. 2 , the array substrate 200 includes a display area 201 and a non-display area 202 surrounding the display area 201 . The non-display area has a bending area 203 , and the bending area 203 is a terminal area. The array substrate 200 further includes a flexible substrate 11 , a buffer layer 12 , a thin film transistor structure layer 13 , vias 14 , grooves 15 , metal traces 16 , a flat layer 18 , an anode 19 and a pixel definition layer 20 .

(埃)，优选为

(埃)，使得第二屏障层1104的厚度小于或等于现有第二屏障层的厚度的一半。另外，使得第二屏障层1104的从单层的氧化硅变更为氮化硅(SiNx)和氧化硅(SiO₂)的叠层结构，优选地，本实施例的第二屏障层1104的结构为氮化硅-氧化硅-氮化硅的叠层结构。因此，通过减薄第二屏障层1104的厚度以及变更其结构，可以使得阵列基板200对减小电性的影响。The flexible substrate 11 extends from the display area 201 to the non-display area 202 . The flexible substrate 11 includes a first PI substrate 1101 , a first barrier layer 1102 , a second PI substrate 1103 and a second barrier layer 1104 . Specifically, the first barrier layer 1102 , the second PI substrate 1103 , and the second barrier layer 1104 are sequentially disposed on the first PI substrate 1101 . In the prior art, the thickness of the second barrier layer of the array substrate is generally greater than or equal to 6000A, and its structure is a single layer of silicon oxide. In this embodiment, the thickness of the second barrier layer 1104 is

(Angstroms), preferably

(Angstroms), so that the thickness of the second barrier layer 1104 is less than or equal to half of the thickness of the existing second barrier layer. In addition, the second barrier layer 1104 is changed from a single layer of silicon oxide to a stacked structure of silicon nitride (SiNx) and silicon oxide (SiO ₂ ). Preferably, the structure of the second barrier layer 1104 in this embodiment is as follows Stacked structure of silicon nitride-silicon oxide-silicon nitride. Therefore, by reducing the thickness of the second barrier layer 1104 and changing its structure, the influence of the array substrate 200 on the electrical properties can be reduced.

The buffer layer 12 extends from the display area 201 to the non-display area 202 and is disposed on the flexible substrate 11 . The material of the buffer layer 12 is an inorganic material, such as silicon nitride, silicon oxide, and the like.

The thin film transistor structure layer 13 extends from the display area 201 to the non-display area 202 and is disposed on the buffer layer 12 . The thin film transistor structure layer 13 includes a first gate insulating layer 131 , a second gate insulating layer 132 and a dielectric layer 133 . The first gate insulating layer 131 , the second gate insulating layer 132 , and the dielectric layer 133 are sequentially disposed on the buffer layer 12 . In this embodiment, the array substrate 200 further includes an active layer 21 , a first gate electrode 22 and a second gate electrode 23 . The active layer 21 is arranged on the upper surface of the buffer layer 12 and is located in the display area 201; the first gate 22 is arranged on the upper surface of the first gate insulating layer 131 and located in the display area 201, and is arranged opposite to the active layer 21; The second gate 23 is disposed on the upper surface of the second gate insulating layer 132 and located in the display area 201 , and is projected on the upper surface of the first gate insulating layer 131 to overlap with the second gate 23 . Further, the existing dielectric layer is a stacked structure of silicon nitride and silicon oxide. In this embodiment, the silicon nitride is removed from the dielectric layer 133 to form a single-layer silicon oxide structure. Therefore, it can be Reduce the electrical influence of the array substrate.

(埃)。The thin film transistor structure layer 13 has via holes 14 and grooves 15 . The via hole 14 is located in the display area 201 and penetrates part of the thin film transistor structure layer 13 . Specifically, the via hole 14 penetrates through the second gate insulating layer 132 , the dielectric layer 133 and part of the first gate insulating layer 131 . The groove 15 is located in the bending region 203 , penetrates through the thin film transistor structure layer 13 and the buffer layer 12 , and is recessed on the upper surface of the flexible substrate 11 . The depth of the groove 15 is

(Egypt).

Part of the metal traces 16 are disposed on the thin film transistor structure layer 13 and in the via hole 14 to form source and drain electrodes 161 , and the source and drain electrodes 161 are electrically connected to the active layer 21 . Part of the metal traces 16 are disposed on the thin film transistor structure layer 13 and in the grooves 15 to form source and drain traces 162 . Specifically, the source and drain traces 162 extend from the surface of part of the thin film transistor structure layer 13 to the sidewalls and the bottom wall of the groove 13 . The source-drain traces 162 are designed in a straight line without openings, which is more conducive to the design of improving the PPI of the display panel in the future. Specifically, the neutral plane simulated by the full-module display panel is from the first PI layer 1101, which is the bottom layer of the array substrate. The closer the source and drain traces 162 are to the neutral plane, the more The smaller the force on the wire 162, the lower the risk of wire breakage, which is more conducive to stability. For example: Suppose that openings need to be arranged on the source-drain traces 162, the width of the source-drain traces 162 needs to be greater than 10um, and the gap between two adjacent traces is 4um, then the source-drain traces The combined pitch distance of 162 and the gap is 14um. However, in this embodiment, it is not necessary to set the openings on the source-drain traces 162, and the pure width of the source-drain traces 162 can be set to 4um, and the gap between the two lines is 4um, then the source-drain traces The total pitch distance of the traces 162 and the gap is 8um. Therefore, when the overall width of the array substrate is fixed, more metal traces can be arranged in the bending area 203, which is beneficial to improve the PPI of the display panel.

The flat layer 18 is located in the display area 201 and the bending area 203 , is disposed on the thin film transistor structure layer 13 , and fills the groove 15 . The material of the flat layer 18 is an inorganic material, which may be silicon oxide or silicon nitride, which is not particularly limited in this embodiment. Compared with the prior art, in this embodiment, the organic material is removed from the groove 15, and the material of the flat layer 18 is directly used to fill the groove 15, so that the source and drain traces 162 are close to the neutral layer, and the stress Smaller, more conducive to improving the bending performance of the bending region 203 .

The anode 19 is located in the display region 201 , is disposed on the upper surface of the flat layer 18 , and is connected to the source and drain electrodes 161 .

The pixel definition layer 20 is located in the display area 201 and the bending area 203 , and is disposed on the upper surface of the flat layer 18 and the upper surface of part of the anode 19 .

The array substrate 200 further includes a support layer 24 located in the display area 201 and disposed on the upper surface of the pixel definition layer 20 at intervals.

This embodiment provides an array substrate. The second barrier layer and the dielectric layer are thinned, so that the overall film thickness of the array substrate is reduced, and the electrical properties of the array substrate are less affected. In this embodiment, the metal wiring adopts straight lines. Design, and use the material of the flat layer to fill the groove without depositing organic materials, which can make the metal traces closer to the neutral plane, which is beneficial to the bending performance of the bending area. Further, the structure of the array substrate has no effect on the slope of the metal traces in the grooves, and does not cause disconnection or residual risk, which can save costs and improve productivity.

As shown in FIG. 3 , this embodiment also provides a method for preparing an array substrate, including a display area and a non-display area surrounding the display area, the non-display area has a bending area, and the preparation of the array substrate The method includes the following steps S1)-S9).

S1) forming a flexible substrate extending from the display area to the non-display area.

As shown in FIG. 4 , the step of forming the flexible substrate specifically includes the following steps S11)-S14).

(埃)，使得第二屏障层1104的厚度为现有第二屏障层的厚度的一半。另外，使得第二屏障层1104的从单层的氧化硅变更为氮化硅(SiNx)和氧化硅(SiO₂)的叠层结构，优选地，本实施例的第二屏障层1104的结构为氮化硅-氧化硅-氮化硅的叠层结构。因此，通过减薄第二屏障层1104的厚度以及变更其结构，可以使得阵列基板200对减小电性的影响。As shown in FIG. 5, S11) forming the first PI substrate. A polyimide material is deposited to form the first PI substrate 1101 . S12) forming a first barrier layer on the first PI substrate. An inorganic material is deposited on the first PI substrate 1101 to form a first barrier layer 1102 . S13) forming a second PI substrate on the first barrier layer. A polyimide material is deposited on the first barrier layer 1102 to form a second PI substrate 1103 . S14) forming a second barrier layer on the second PI substrate. An inorganic material is deposited on the second PI substrate 1103 to form a second barrier layer 1104 . In this embodiment, the thickness of the second barrier layer 1104 is 2800-3200A, preferably

(Angstroms), so that the thickness of the second barrier layer 1104 is half of the thickness of the existing second barrier layer. In addition, the second barrier layer 1104 is changed from a single layer of silicon oxide to a stacked structure of silicon nitride (SiNx) and silicon oxide (SiO ₂ ). Preferably, the structure of the second barrier layer 1104 in this embodiment is as follows Stacked structure of silicon nitride-silicon oxide-silicon nitride. Therefore, by reducing the thickness of the second barrier layer 1104 and changing its structure, the influence of the array substrate 200 on the electrical properties can be reduced.

S2) forming a buffer layer on the flexible substrate, the buffer layer extending from the display area to the non-display area. As shown in FIG. 5 , an inorganic material is deposited on the surface of the second barrier layer 1104 to form the buffer layer 12 , and the inorganic material may be silicon nitride, silicon oxide, etc., but not limited thereto.

S3) forming a thin film transistor structure layer on the buffer layer, the thin film transistor structure layer extending from the display area to the non-display area.

As shown in FIG. 6 , the step of forming a thin film transistor structure layer on the buffer layer includes the following steps S31)-S33).

As shown in FIG. 5 , step S31 ) forming a first gate insulating layer 131 on the buffer layer 12 , the first gate insulating layer 131 extending from the display area 201 to the non-display area 202 . Before forming the first gate insulating layer 131 , the method further includes, using a first mask to form an active layer 21 on the upper surface of the buffer layer 12 , and the active layer 21 is located in the display area 201 . The first gate insulating layer 131 is disposed on the upper surfaces of the buffer layer 12 and the active layer 21 . After forming the first gate insulating layer 131 , the method further includes forming a first gate electrode 22 on the upper surface of the first gate insulating layer 131 by using a second mask. The first gate 22 is disposed opposite to the active layer 21 .

S32) A second gate insulating layer 132 is formed on the first gate insulating layer 131 , and the second gate insulating layer 132 extends from the display area 201 to the non-display area 202 . After the second gate insulating layer 132 is formed, the method further includes forming a second gate 23 on the upper surface of the second gate insulating layer 132 by using a third mask. The projection of the second gate 23 on the upper surface of the first gate insulating layer 131 overlaps with the second gate 23 .

S33 ) forming a dielectric layer 133 on the second gate insulating layer 132 , the dielectric layer 133 extending from the display area 201 to the non-display area 202 . The existing dielectric layer is a stacked structure of silicon nitride and silicon oxide. In this embodiment, the silicon nitride is removed from the dielectric layer 133 to form a single-layer silicon oxide structure. Therefore, the array can be reduced in size. Electrical effects of the substrate.

S4) forming grooves and via holes, the grooves are arranged in the bending region and extend from the side of the thin film transistor structure layer away from the buffer layer into the buffer layer; the via holes are arranged in the buffer layer The display area extends from the upper surface of the thin film transistor structure layer into the thin film transistor structure layer. As shown in FIG. 7 , the TFT structure layer 13 is etched with a fourth mask, so that the via hole 14 and the groove 15 are formed under the same mask, wherein the fourth mask is an MCD mask . In this embodiment, the same mask is used to form the via hole and the groove in one process, so that the groove 15 needs to be prepared twice and the process of forming the via hole separately is avoided. Compared with the preparation process of the existing array substrate, this embodiment can save two mask processes, and form a taper in the groove 15, and forming a taper in the groove 15 will not cause defects of the array substrate. Therefore, in this embodiment, the thickness of the barrier layer and the dielectric layer is reduced to ensure the performance of the array substrate.

S5) forming metal layer metal traces, wherein some metal traces are filled in the via holes and extend the side of the thin film transistor structure layer away from the buffer layer to form source and drain; some metal traces are covered on the The groove wall of the groove extends the side of the thin film transistor structure layer away from the buffer layer to form source and drain traces. As shown in FIG. 7 , a fifth mask is used to deposit metal material in the via hole 14 to form the source and drain electrodes 161 and deposit metal material in the groove 15 to form the source and drain lines 162 . The source-drain traces 162 are attached to the sidewalls and bottom walls of the groove 15 . The source-drain traces 162 are source-drain metal traces (SD metal traces), which are designed with straight lines without openings, which is more conducive to the future. Improve the design of the PPI of the display panel. Specifically, the neutral plane simulated by the full-module display panel is from the first PI layer 1101, which is the bottom layer of the array substrate. The closer the source and drain traces 162 are to the neutral plane, the more The smaller the force on the wire 162, the lower the risk of wire breakage, which is more conducive to stability. For example: Suppose that openings need to be arranged on the source-drain traces 162, the width of the source-drain traces 162 needs to be greater than 10um, and the gap between two adjacent traces is 4um, then the source-drain traces The combined pitch distance of 162 and the gap is 14um. However, in this embodiment, it is not necessary to set the openings on the source-drain traces 162, and the pure width of the source-drain traces 162 can be set to 4um, and the gap between the two lines is 4um, then the source-drain traces The total pitch distance of the traces 162 and the gap is 8um. Therefore, when the overall width of the array substrate is fixed, more metal traces can be arranged in the bending area 203, which is beneficial to improve the PPI of the display panel.

S6) forming a flat layer covering the upper surface of the thin film transistor structure layer and filling the groove. As shown in FIG. 2 , an inorganic material is used to form a flat layer 18 on the thin film transistor structure layer 13 , the source and drain electrodes 161 and the source and drain lines 162 , and the flat layer 18 fills the grooves 15 . The material of the flat layer 18 is an inorganic material, which may be silicon oxide or silicon nitride, which is not particularly limited in this embodiment. Compared with the prior art, in this embodiment, the organic material is removed from the groove 15, and the material of the flat layer 18 is directly used to fill the groove 15, so that the source and drain traces 162 are close to the neutral layer, and the stress Smaller, more conducive to improving the bending performance of the bending region 203 .

S7) forming a flat layer through hole. As shown in FIG. 2 , the sixth mask is used to etch the flat layer 18 to form a flat layer through hole 180 in the display area 201 .

S8) forming an anode, the anode fills the through hole of the flat layer and extends to the upper surface of the flat layer. As shown in FIG. 2 , the through hole 180 of the flat layer is filled with metal material using a seventh mask to form the anode 19 .

S9) forming a pixel definition layer and a support layer on the flat layer. As shown in FIG. 2 , the pixel defining layer 19 and the supporting layer 24 are formed on the flat layer 18 by using an eighth mask.

In this embodiment, the entire process of the array substrate adopts 8 photomask mask processes, mainly using a photomask to form vias and grooves in one step process, and removes the need for photomask masks for organic material film formation process, thus saving the use of three masks. However, the existing array substrate requires 11 photomask mask processes. Therefore, the manufacturing method of the array substrate provided in this embodiment has a simpler manufacturing process, saves consumption of raw materials, and saves production capacity, which is beneficial to mass production in the future and reduces production costs.

This embodiment provides a method for preparing an array substrate. By thinning the second barrier layer and the dielectric layer, the overall film thickness of the array substrate is reduced, and the electrical properties of the array substrate are less affected; The groove is changed from two tapers to a single taper, and grooves and vias are formed through a one-step etching process. Metal traces with a straight line design are attached to the side walls and bottom walls of the groove, and the flat layer connects the groove. Filling up and removing the organic material in the existing groove can make the metal trace closer to the neutral plane, which is beneficial to the bending performance of the bending area.

An array substrate and a preparation method thereof provided by the embodiments of the present application have been described in detail above. The principles and implementations of the present application are described with specific examples in this article. The technical solution of the application and its core idea; those of ordinary skill in the art should understand that: it can still make modifications to the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements to some of the technical features; and these modifications or replacements, The essence of the corresponding technical solutions does not deviate from the scope of the technical solutions of the embodiments of the present application.

Claims (10)

1. An array substrate comprising a display region and a non-display region surrounding the display region, the non-display region having a bending region therein, comprising:

a flexible substrate extending from the display region to the non-display region;

the buffer layer is arranged on the flexible substrate and extends from the display area to the non-display area;

the thin film transistor structure layer is arranged on the buffer layer and extends from the display area to the non-display area; the thin film transistor structure layer has

The groove is arranged in the bending area and extends into the buffer layer from one surface, far away from the buffer layer, of the thin film transistor structure layer; and

the through hole is arranged in the display area and extends into the thin film transistor structure layer from one surface, far away from the buffer layer, of the thin film transistor structure layer;

the metal routing is filled in the through hole and extends one surface of the thin film transistor structure layer far away from the buffer layer to form a source drain electrode; part of metal wires cover the groove wall of the groove and extend to one surface of the thin film transistor structure layer far away from the buffer layer to form source drain electrode wires; and

the array substrate further comprises a flat layer which covers one surface of the thin film transistor structure layer, which is far away from the buffer layer, and the flat layer is filled in the groove.

2. The array substrate of claim 1,

the depth of the groove is

3. The array substrate of claim 1,

the flexible substrate includes:

a first PI substrate;

a first barrier layer disposed on the first PI substrate;

a second PI substrate arranged on the first barrier layer; and

and the second barrier layer is arranged on the second PI substrate.

4. The array substrate of claim 3,

the second barrier layer has a thickness of

5. The array substrate of claim 1,

the thin film transistor structure layer includes:

a first gate insulating layer disposed on the buffer layer and the active layer and extending from the display region to the non-display region;

the first grid electrode is arranged on the first grid electrode insulating layer and is positioned in the display area;

the second grid electrode insulating layer is arranged on the first grid electrode insulating layer and the first grid electrode and extends from the display area to the non-display area;

the second grid electrode is arranged on the second grid electrode insulating layer and is positioned in the display area; and

and the dielectric layer is arranged on the second grid electrode insulating layer and the second grid electrode and extends from the display area to the non-display area.

6. A preparation method of an array substrate comprises a display area and a non-display area surrounding the display area, wherein the non-display area is provided with a bending area, and the preparation method is characterized by comprising the following steps:

forming a flexible substrate extending from the display area to the non-display area;

forming a buffer layer on the flexible substrate, the buffer layer extending from the display region to the non-display region;

forming a thin film transistor structure layer on the buffer layer, wherein the thin film transistor structure layer extends from the display area to the non-display area;

forming a groove and a via hole, wherein the groove is arranged in the bending region and extends into the buffer layer from one surface, far away from the buffer layer, of the thin film transistor structure layer; the through hole is arranged in the display area and extends into the thin film transistor structure layer from the upper surface of the thin film transistor structure layer;

forming metal wires, wherein part of the metal wires are filled in the via holes and extend to one surface of the thin film transistor structure layer far away from the buffer layer to form a source drain electrode; part of metal wires cover the groove wall of the groove and extend to one surface of the thin film transistor structure layer far away from the buffer layer to form source drain electrode wires; and

and forming a flat layer, wherein the flat layer covers the upper surface of the thin film transistor structure layer and is filled in the groove.

7. The method of claim 6, wherein the step of forming the array substrate comprises the steps of,

in the step of forming the via holes and the grooves, a photomask is adopted to etch the thin film transistor structure layer to form the via holes and the grooves.

8. The method of claim 6, wherein the step of forming the array substrate comprises the steps of,

the depth of the groove is

9. The method of claim 6, wherein the step of forming the array substrate comprises the steps of,

in the step of forming a flexible substrate, the method further includes:

forming a first PI substrate;

forming a first barrier layer on the first PI substrate;

forming a second PI substrate on the first barrier layer; and

forming a second barrier layer on the second PI substrate;

wherein the second barrier layer has a thickness of

10. The method of claim 6, wherein the step of forming the array substrate comprises the steps of,

the step of forming the thin film transistor structure layer on the buffer layer includes:

forming a first gate insulating layer on the buffer layer and the active layer, the first gate insulating layer extending from the display region to the non-display region;

forming a first gate on the first gate insulating layer, the first gate being located in the display region;

forming a second gate insulating layer on the first gate insulating layer and the first gate, the second gate insulating layer extending from the display region to the non-display region;

forming a second gate on the second gate insulating layer, the second gate being located in the display region; and

and forming a dielectric layer on the second gate insulating layer and the second gate, wherein the dielectric layer extends from the display region to the non-display region.

Images