CN111463243A - Array substrate and preparation method thereof - Google Patents
Array substrate and preparation method thereof Download PDFInfo
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- CN111463243A CN111463243A CN202010273154.3A CN202010273154A CN111463243A CN 111463243 A CN111463243 A CN 111463243A CN 202010273154 A CN202010273154 A CN 202010273154A CN 111463243 A CN111463243 A CN 111463243A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
- G09F9/301—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements flexible foldable or roll-able electronic displays, e.g. thin LCD, OLED
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
Abstract
The invention provides an array substrate and a preparation method thereof, wherein the array substrate comprises a display area and a non-display area surrounding the display area, wherein the non-display area is provided with a bending area, the array substrate also comprises a flexible substrate, a buffer layer, a thin film transistor structure layer, a groove, a via hole, a metal wire and a flat layer, wherein part of the metal wire is filled in the via hole and extends to one surface of the thin film transistor structure layer far away from the buffer layer to form a source electrode and a drain electrode; and part of metal wires cover the groove wall of the groove and extend to one surface of the thin film transistor structure layer far away from the buffer layer to form source and drain wires.
Description
Technical Field
The application relates to the technical field of display, in particular to an array substrate and a preparation method thereof.
Background
The O L ED (Organic L light-Emitting Diode) is a display technology developed in recent years, and compared with a liquid crystal display, because the Organic light-Emitting Diode has the advantages of high contrast, high response, low energy consumption, flexibility, self-luminescence, wide viewing angle, high response speed and the like, the Organic light-Emitting Diode has a wide application prospect and has important research significance, and the AMO L ED (active matrix/Organic L light-Emitting Diode) becomes a prominent representative of the next generation of display technologies due to the advantages of lightness, thinness, flexibility, non-fragility, wearability and the like.
In order to improve the bending performance of the bending area (bending area) of the display panel, the inorganic film layer is often removed in the industry, and an organic film layer with smaller stress is correspondingly used for replacement, so that the bending performance of the product is improved.
Specifically, the display panel includes an array substrate, and the array substrate includes a display Area (AA Area) and a non-display Area, where the non-display Area includes a bending Area, that is, a terminal Area (pad Area). Deep Hole regions (DH) are provided in the terminal regions, which DH holes are filled with an organic material, so that the terminal regions are easy to bend. However, in order to prevent the Deep Hole region (Deep Hole, DH) from being too Deep and the risk of breaking or remaining of the source and Drain traces (SD) at the edge of the bonding region due to too steep taper angle (taper), the industry often removes the inorganic film layer in the pad region by using a multi-step etching method, and forms a retardation layer at the taper to prevent the SD traces from breaking.
At present, in order to realize the design of two tabs in a pad area, two mask (mask) processes are needed to realize a DH slot with a slope, and one mask is needed to fill an organic material into the DH slot. Therefore, the existing array substrate needs to be subjected to an etching process shielded by a plurality of photomasks, and the process is complicated, the cost is high, and the productivity is low.
Disclosure of Invention
The invention aims to provide an array substrate and a preparation method thereof, and aims to solve the technical problems of complex forming process, high cost and low productivity of the conventional array substrate.
In order to achieve the above object, the present invention provides an array substrate, including a display area and a non-display area surrounding the display area, wherein the non-display area has a bending area therein, further including: a flexible substrate extending from the display region to the non-display region; the buffer layer is arranged on the flexible substrate and extends from the display area to the non-display area; the thin film transistor structure layer is arranged on the buffer layer and extends from the display area to the non-display area; the thin film transistor structure layer is provided with a groove, is arranged in the bending area and extends into the buffer layer from one surface, far away from the buffer layer, of the thin film transistor structure layer; the through hole is arranged in the display area and extends into the thin film transistor structure layer from one surface, far away from the buffer layer, of the thin film transistor structure layer; the metal routing is filled in the through hole and extends one surface of the thin film transistor structure layer far away from the buffer layer to form a source drain electrode; part of metal wires cover the groove wall of the groove and extend to one surface of the thin film transistor structure layer far away from the buffer layer to form source drain electrode wires; the array substrate further comprises a flat layer which covers one surface of the thin film transistor structure layer, which is far away from the buffer layer, and the flat layer is filled in the groove.
Further, the depth of the groove is
Further, the flexible substrate includes: a first PI substrate; a first barrier layer disposed on the first PI substrate; a second PI substrate arranged on the first barrier layer; and a second barrier layer disposed on the second PI substrate.
Further, the second barrier layer has a thickness of
Further, the thin film transistor structure layer includes: a first gate insulating layer disposed on the buffer layer and the active layer and extending from the display region to the non-display region; the first grid electrode is arranged on the first grid electrode insulating layer and is positioned in the display area; the second grid electrode insulating layer is arranged on the first grid electrode insulating layer and the first grid electrode and extends from the display area to the non-display area; the second grid electrode is arranged on the second grid electrode insulating layer and is positioned in the display area; and a dielectric layer disposed on the second gate insulating layer and the second gate, and extending from the display region to the non-display region.
In order to achieve the above object, the present invention further provides a method for manufacturing an array substrate, including a display area and a non-display area surrounding the display area, the non-display area having a bending area therein, the method including the steps of: forming a flexible substrate extending from the display area to the non-display area; forming a buffer layer on the flexible substrate, the buffer layer extending from the display region to the non-display region; forming a thin film transistor structure layer on the buffer layer, wherein the thin film transistor structure layer extends from the display area to the non-display area; forming a groove and a via hole, wherein the groove is arranged in the bending region and extends into the buffer layer from one surface, far away from the buffer layer, of the thin film transistor structure layer; the through hole is arranged in the display area and extends into the thin film transistor structure layer from the upper surface of the thin film transistor structure layer; forming metal wires, wherein part of the metal wires are filled in the via holes and extend to one surface of the thin film transistor structure layer far away from the buffer layer to form a source drain electrode; part of metal wires cover the groove wall of the groove and extend to one surface of the thin film transistor structure layer far away from the buffer layer to form source drain electrode wires; and forming a flat layer, wherein the flat layer covers the upper surface of the thin film transistor structure layer and is filled in the groove.
Further, in the step of forming the groove and the via hole, a light cover is adopted to etch the thin film transistor structure layer to form the via hole and the groove.
Further, the depth of the groove is
Further, the step of forming a flexible substrate further includes: forming a first PI substrate; forming a first barrier layer on the first PI substrate; forming a second PI substrate on the first barrier layer; and forming a second barrier layer on the second PI substrate; wherein the second barrier layer has a thickness of
Further, the step of forming the thin film transistor structure layer on the buffer layer includes: forming a first gate insulating layer on the buffer layer and the active layer, the first gate insulating layer extending from the display region to the non-display region; forming a first gate on the first gate insulating layer, the first gate being located in the display region; forming a second gate insulating layer on the first gate insulating layer and the first gate, the second gate insulating layer extending from the display region to the non-display region; forming a second gate on the second gate insulating layer, the second gate being located in the display region; and forming a dielectric layer on the second gate insulating layer and the second gate, the dielectric layer extending from the display region to the non-display region.
The invention has the technical effects that the second barrier layer and the dielectric layer are thinned, so that the overall film thickness of the array substrate is reduced, a photomask is adopted to form a through hole and a groove on the thin film transistor structure layer, organic materials in the existing groove are removed, the groove is directly filled with a flat layer on the metal routing, the metal routing is closer to a neutral surface, and the bending performance of a terminal area is facilitated. The array substrate is simpler in manufacturing process, raw material consumption and productivity are saved, mass production in the future is facilitated, and production cost is reduced.
Drawings
The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a conventional array substrate.
Fig. 2 is a schematic structural diagram of an array substrate according to an embodiment of the present application.
Fig. 3 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the present disclosure.
Fig. 4 is a schematic structural diagram of an electronic device in a folded state according to an embodiment of the present application.
Fig. 5 is a flowchart illustrating a flexible substrate forming process according to an embodiment of the present disclosure.
Fig. 6 is a schematic structural diagram of a planarization layer according to an embodiment of the present disclosure.
Fig. 7 is a schematic structural diagram illustrating formation of a groove according to an embodiment of the present disclosure.
The attached components of the prior array substrate are identified as follows:
100 a conventional array substrate; 1001 display area; 1002 a bending area;
101 a first PI substrate; 102 a first barrier layer; 103 a second PI substrate; 104 a second barrier layer;
105 a buffer layer; 106 thin film transistor structure layers; 107 a planar layer;
108 an anode layer; 109 pixel definition layer;
1061 a first gate insulating layer; 1062 a second gate insulation layer; 1063 a dielectric layer;
111 an active layer; 112 a first gate; 113 a second gate; 114 source and drain electrodes;
115 grooves; 116 an organic film layer; 117 metal routing;
115a first deep hole; 115b, a second deep hole.
The parts of the array substrate in the application are marked as follows:
201 a display area; 202 a non-display area; 203 a bending region;
11 a flexible substrate; 12 a buffer layer; 13 thin film transistor structure layer; 14 through holes;
15, grooves; 16 metal routing lines; 161 source and drain electrodes; 162 routing a source drain electrode; 18 a planar layer;
19 an anode; a 20 pixel definition layer;
1101 a first PI substrate; 1102 a first barrier layer;
1103 second PI substrate; 1104 a second barrier layer;
131 a first gate insulating layer; 132 a second gate insulating layer; 133 a dielectric layer;
21 an active layer; 22 a first gate electrode; 23 a second gate; 24 a support layer; 180 planar layer vias.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.
As shown in fig. 1, the conventional array substrate 100 includes a display area 1001 and a bending area 1002, and the bending area 1002 is a terminal area (pad area). The conventional array substrate 100 includes, in order from bottom to top, a first PI substrate 101, a first barrier layer 102, a second PI substrate 103, a second barrier layer 104, a buffer layer 105, a thin film transistor structure layer 106, a planarization layer 107, an anode layer 108, and a pixel definition layer 109. The thin film transistor structure layer 106 includes a first gate insulating layer 1061, a second gate insulating layer 1062, and a dielectric layer 1063. The conventional array substrate 100 further includes an active layer 111 disposed on the buffer layer 105; a first gate 112 disposed on the first gate insulating layer 1061; a second gate electrode 113 disposed on the second gate insulating layer; the source and drain electrodes 114 penetrate the thin film transistor structure layer 106 and are connected to the active layer 111. The conventional array substrate 100 further includes a groove 115 penetrating the thin film transistor structure layer 106, the buffer layer 105, and the second barrier layer 104. The recess 115 comprises a first recess 115a and a second recess 115b, which together with a part of the second PI-substrate form the recess 115. In the process of preparing the groove 115, after the buffer layer 105 is prepared, a first deep hole 115a is formed by etching the buffer layer 105 and the second barrier layer 104 using a first mask and penetrates through the buffer layer 105 and the second barrier layer 104; after the thin film transistor structure layer 103 is prepared, the thin film transistor structure layer 103 is etched by using a second mask to form a second deep hole 115b, and the second deep hole penetrates through the insulating layer 106. Thus, the first deep hole 115a and the second deep hole 115b combine to form the groove 115. After depositing an organic material in the groove 115 to form an organic film layer 116, performing masking processing on the thin film transistor structure layer 106 by using a third mask plate to form a via hole penetrating to the active layer 111, then depositing a metal material in the via hole and on the upper surface of part of the organic film layer 116 by using a fourth mask plate, wherein the metal material forms a source/drain 114 in the via hole, and the metal material forms a metal trace 117 on the upper surface of part of the organic film layer 116. In summary, the conventional array substrate 100 at least includes 11 mask processes, specifically: the formation of the active layer 111 requires one mask process, the formation of the first gate 112 and the second gate 113 requires two mask processes, the formation of the first deep hole 115a and the second deep hole 115b requires two mask processes, the formation of the via hole requires one mask process, the formation of the source drain 114 and the metal trace 117 requires one mask process, the formation of the via hole on the planar layer 107 requires one mask process, the formation of the anode layer 108 requires one mask process, and the formation of the pixel definition layer 109 requires one mask process. Therefore, the conventional array substrate 100 has a complicated process and a low throughput.
Therefore, the present embodiment provides an array substrate and a method for manufacturing the same to solve the above problems.
As shown in fig. 2, the array substrate 200 includes a display region 201 and a non-display region 202 surrounding the display region 201, the non-display region has a bending region 203, and the bending region 203 is a terminal region. The array substrate 200 further includes a flexible substrate 11, a buffer layer 12, a thin film transistor structure layer 13, a via 14, a groove 15, a metal trace 16, a planarization layer 18, an anode 19, and a pixel definition layer 20.
The flexible substrate 11 extends from the display area 201 to the non-display area 202. The flexible substrate 11 includes a first PI substrate 1101, a first barrier layer 1102, a second PI substrate 1103, and a second barrier layer 1104. Specifically, the first barrier layer 1102, the second PI substrate 1103, and the second barrier layer 1104 are sequentially disposed on the first PI substrateOn a plate 1101. In the prior art, the thickness of the second barrier layer of the array substrate is generally greater than or equal to 6000A, and the second barrier layer is a single layer of silicon oxide. In this embodiment, the thickness of the second barrier layer 1104 is
(Angstrom), preferably
(angstroms) such that the thickness of the second barrier layer 1104 is less than or equal to half the thickness of existing second barrier layers. In addition, the second barrier layer 1104 is changed from a single layer of silicon oxide to silicon nitride (SiNx) and silicon oxide (SiO)2) Preferably, the structure of the second barrier layer 1104 in this embodiment is a stacked structure of silicon nitride-silicon oxide-silicon nitride. Therefore, by reducing the thickness of the second barrier layer 1104 and changing the structure thereof, the array substrate 200 can have a reduced electrical effect.
The buffer layer 12 extends from the display region 201 to the non-display region 202 and is disposed on the flexible substrate 11. The buffer layer 12 is made of an inorganic material such as silicon nitride or silicon oxide.
The thin film transistor structure layer 13 extends from the display region 201 to the non-display region 202, and is disposed on the buffer layer 12. The thin film transistor structure layer 13 includes a first gate insulating layer 131, a second gate insulating layer 132, and a dielectric layer 133. The first gate insulating layer 131, the second gate insulating layer 132, and the dielectric layer 133 are sequentially disposed on the buffer layer 12. In this embodiment, the array substrate 200 further includes an active layer 21, a first gate 22 and a second gate 23. The active layer 21 is arranged on the upper surface of the buffer layer 12 and is positioned in the display area 201; the first gate 22 is disposed on the upper surface of the first gate insulating layer 131, is located in the display region 201, and is opposite to the active layer 21; the second gate 23 is disposed on the upper surface of the second gate insulating layer 132, and is located in the display region 201, and the projection of the second gate 23 on the upper surface of the first gate insulating layer 131 coincides with the second gate 23. Further, the conventional dielectric layer is a silicon nitride-silicon oxide stacked structure, and in this embodiment, the dielectric layer 133 is formed by removing silicon nitride, so that the single-layer silicon oxide structure is formed, and therefore, the electrical influence of the array substrate can be reduced.
The thin film transistor structure layer 13 has a via hole 14 and a groove 15. The via hole 14 is located in the display area 201 and penetrates through a portion of the thin film transistor structure layer 13. Specifically, the via 14 penetrates the second gate insulating layer 132, the dielectric layer 133, and a portion of the first gate insulating layer 131. The groove 15 is located in the bending region 203, penetrates through the thin film transistor structure layer 13 and the buffer layer 12, and is recessed in the upper surface of the flexible substrate 11. The depth of the groove 15 is
(angstroms).
Part of the metal trace 16 is disposed on the thin film transistor structure layer 13 and in the via hole 14, and a source drain 161 is formed, and the source drain 161 is electrically connected to the active layer 21. Part of the metal traces 16 are disposed on the thin film transistor structure layer 13 and in the groove 15 to form source/drain traces 162. Specifically, the source/drain trace 162 extends from the surface of a portion of the thin film transistor structure layer 13 to the sidewall and the bottom wall of the recess 13. The source/drain routing line 162 is designed to be straight without opening a hole, which is more beneficial to improving the design of the PPI of the display panel in the future. Specifically, the neutral plane simulated by the display panel (panel) in the full module form is the first PI layer 1101, that is, the bottom layer of the array substrate, and the closer the source/drain trace 162 is to the neutral plane, the smaller the stress of the source/drain trace 162 is, the lower the risk of wire breakage is, and the better the stability is. By way of example: if the source/drain trace 162 needs to be opened, the width of the source/drain trace 162 needs to be greater than 10um, and the gap between two adjacent lines is 4um, so that the pitch distance between the source/drain trace 162 and the gap is 14 um. However, in this embodiment, it is not necessary to open the hole on the source/drain trace 162, and the pure width of the source/drain trace 162 may be set to 4um, and the gap between the two lines is 4um, so that the pitch distance between the source/drain trace 162 and the gap is 8um, and therefore, under the condition that the overall width of the array substrate is fixed, more metal traces can be arranged in the bending region 203, thereby facilitating the improvement of the PPI of the display panel.
The planarization layer 18 is disposed on the tft structure layer 13 in the display region 201 and the bending region 203, and fills the recess 15. The material of the planarization layer 18 is an inorganic material, and may be silicon oxide or silicon nitride, and this embodiment is not particularly limited. Compared with the prior art, in the embodiment, the organic material is removed from the groove 15, and the groove 15 is filled with the material of the flat layer 18, so that the source/drain routing 162 is close to the neutral layer, the stress is smaller, and the improvement of the bending performance of the bending region 203 is facilitated.
The anode 19 is located in the display region 201, disposed on the upper surface of the planarization layer 18, and connected to the source/drain 161.
The pixel defining layer 20 is disposed in the display region 201 and the bending region 203, and is disposed on the upper surface of the planarization layer 18 and a portion of the upper surface of the anode electrode 19.
The array substrate 200 further includes a supporting layer 24 disposed in the display area 201 and spaced apart from the upper surface of the pixel defining layer 20.
In the present embodiment, the second barrier layer and the dielectric layer are thinned, so that the overall film thickness of the array substrate is reduced and the electrical influence is small; the metal wiring in this embodiment adopts the straight line design to adopt the material of flat layer to fill the recess, need not deposit organic material, can make the metal wiring more be close to the neutral face, be favorable to the bending performance in bending zone. Furthermore, the structure of the array substrate has no influence on the gradient of the metal wiring in the groove, so that the wire breakage or the residual risk can not be caused, the cost can be saved, and the productivity can be improved.
As shown in fig. 3, this embodiment further provides a method for manufacturing an array substrate, including a display area and a non-display area surrounding the display area, where the non-display area has a bending area therein, and the method includes the following steps S1) -S9).
S1) forming a flexible substrate extending from the display area to the non-display area.
As shown in fig. 4, the step of forming the flexible substrate specifically includes the following steps S11) -S14).
As shown in fig. 5, S11) forms a first PI substrate. A polyimide material is deposited to form a first PI substrate 1101. S12) forming a first barrier layer on the first PI substrate. Depositing inorganic materialsA first barrier layer 1102 is formed on the first PI substrate 1101. S13) forming a second PI substrate on the first barrier layer. A polyimide material is deposited on the first barrier layer 1102 to form a second PI substrate 1103. S14) forming a second barrier layer on the second PI substrate. An inorganic material is deposited on the second PI substrate 1103 to form a second barrier layer 1104. In this embodiment, the thickness of the second barrier layer 1104 is 2800-
(angstroms) such that the thickness of the second barrier layer 1104 is half the thickness of the existing second barrier layer. In addition, the second barrier layer 1104 is changed from a single layer of silicon oxide to silicon nitride (SiNx) and silicon oxide (SiO)2) Preferably, the structure of the second barrier layer 1104 in this embodiment is a stacked structure of silicon nitride-silicon oxide-silicon nitride. Therefore, by reducing the thickness of the second barrier layer 1104 and changing the structure thereof, the array substrate 200 can have a reduced electrical effect.
S2) forming a buffer layer on the flexible substrate, the buffer layer extending from the display region to the non-display region. As shown in fig. 5, an inorganic material, such as, but not limited to, silicon nitride, silicon oxide, etc., is deposited on the upper surface of the second barrier layer 1104 to form the buffer layer 12.
S3) forming a thin film transistor structure layer on the buffer layer, the thin film transistor structure layer extending from the display region to the non-display region.
As shown in fig. 6, the step of forming a tft structure layer on the buffer layer includes the following steps S31) -S33).
As shown in fig. 5, S31) a first gate insulating layer 131 is formed on the buffer layer 12, the first gate insulating layer 131 extending from the display region 201 to the non-display region 202. Before forming the first gate insulating layer 131, forming an active layer 21 on the upper surface of the buffer layer 12 by using a first mask, wherein the active layer 21 is located in the display region 201. The first gate insulating layer 131 is disposed on the upper surfaces of the buffer layer 12 and the active layer 21. After the first gate insulating layer 131 is formed, a first gate 22 is formed on the upper surface of the first gate insulating layer 131 by using a second mask. The first gate 22 is disposed opposite to the active layer 21.
S32) forming a second gate insulating layer 132 on the first gate insulating layer 131, the second gate insulating layer 132 extending from the display region 201 to the non-display region 202. After forming the second gate insulating layer 132, a second gate 23 is formed on the upper surface of the second gate insulating layer 132 by using a third mask. Wherein, the projection of the second gate 23 is overlapped with the second gate 23 on the upper surface of the first gate insulating layer 131.
S33) forming a dielectric layer 133 on the second gate insulating layer 132, the dielectric layer 133 extending from the display region 201 to the non-display region 202. In the present embodiment, the dielectric layer 133 is formed by removing silicon nitride to form a single-layer silicon oxide structure, so that the electrical influence of the array substrate can be reduced.
S4) forming a groove and a via hole, wherein the groove is arranged in the bending region and extends into the buffer layer from the surface, far away from the buffer layer, of the thin film transistor structure layer; the through hole is arranged in the display area and extends into the thin film transistor structure layer from the upper surface of the thin film transistor structure layer. As shown in fig. 7, a fourth mask is used to perform an etching process on the thin film transistor structure layer 13, so that the via hole 14 and the groove 15 are formed under the same mask, wherein the fourth mask is an MCD mask. In the embodiment, the same photomask is adopted to form the via hole and the groove in one process, so that the groove 15 is prevented from being prepared by twice photomasks and formed by the via hole independently. Compared with the existing array substrate preparation process, the embodiment can save two photomask processes, and a taper angle (taper) is formed in the groove 15, and a taper formed in the groove 15 does not cause the array substrate to be bad, so that the performance of the array substrate is ensured by reducing the thicknesses of the barrier layer and the dielectric layer in the embodiment.
S5) forming metal layer metal wires, wherein part of the metal wires are filled in the via holes and extend to one surface of the thin film transistor structure layer far away from the buffer layer to form source and drain electrodes; and part of metal wires cover the groove wall of the groove and extend to one surface of the thin film transistor structure layer far away from the buffer layer to form source and drain wires. As shown in fig. 7, a fifth mask is used to deposit a metal material in the via 14 to form a source drain 161 and to deposit a metal material in the recess 15 to form a source drain trace 162. The source/drain traces 162 are attached to the sidewalls and the bottom wall of the recess 15, and the source/drain traces 162 are source/drain metal traces (SD metal traces) and are designed to have no straight line opening, which is more favorable for improving the design of the PPI of the display panel in the future. Specifically, the neutral plane simulated by the display panel (panel) in the full module form is the first PI layer 1101, that is, the bottom layer of the array substrate, and the closer the source/drain trace 162 is to the neutral plane, the smaller the stress of the source/drain trace 162 is, the lower the risk of wire breakage is, and the better the stability is. By way of example: if the source/drain trace 162 needs to be opened, the width of the source/drain trace 162 needs to be greater than 10um, and the gap between two adjacent lines is 4um, so that the pitch distance between the source/drain trace 162 and the gap is 14 um. However, in this embodiment, it is not necessary to open the hole on the source/drain trace 162, and the pure width of the source/drain trace 162 may be set to 4um, and the gap between the two lines is 4um, so that the pitch distance between the source/drain trace 162 and the gap is 8um, and therefore, under the condition that the overall width of the array substrate is fixed, more metal traces can be arranged in the bending region 203, thereby facilitating the improvement of the PPI of the display panel.
S6) forming a flat layer which covers the upper surface of the thin film transistor structure layer and is filled in the groove. As shown in fig. 2, an inorganic material is used to form a planarization layer 18 on the thin film transistor structure layer 13, the source/drain 161 and the source/drain trace 162, and the planarization layer 18 fills the recess 15. The material of the planarization layer 18 is an inorganic material, and may be silicon oxide or silicon nitride, and this embodiment is not particularly limited. Compared with the prior art, in the embodiment, the organic material is removed from the groove 15, and the groove 15 is filled with the material of the flat layer 18, so that the source/drain routing 162 is close to the neutral layer, the stress is smaller, and the improvement of the bending performance of the bending region 203 is facilitated.
S7) forming a planarization layer via. As shown in fig. 2, the planarization layer 18 is etched using the sixth mask to form a planarization layer via 180 in the display area 201.
S8) forming an anode, wherein the anode fills the through hole of the planarization layer and extends to the upper surface of the planarization layer. As shown in fig. 2, the planarization via 180 is filled with a metal material using a seventh mask to form the anode 19.
S9) forming a pixel defining layer and a supporting layer on the planarization layer. As shown in fig. 2, a pixel defining layer 19 and a supporting layer 24 are formed on the planarization layer 18 using an eighth mask.
In this embodiment, the entire process of the array substrate adopts 8 photomask masking processes, mainly one photomask is used to form the via holes and the grooves in one step, and the process of the photomask masking for film formation of the organic material is removed, so that the use of three photomasks is saved. The existing array substrate needs 11 mask processes, so the manufacturing process of the preparation method of the array substrate provided by the embodiment is simpler, the raw material consumption is reduced, the productivity is saved, the future mass production is facilitated, and the production cost is reduced.
In the method for manufacturing an array substrate according to the present invention, the second barrier layer and the dielectric layer are thinned, so that the overall film thickness of the array substrate is reduced and the electrical influence is small; two tapers of the groove of the bending area are changed into a single taper, a groove and a via hole are formed through a one-step etching process, the metal wiring adopting a linear design is attached to the side wall and the bottom wall of the groove, the groove is filled with the flat layer, organic materials in the existing groove are removed, the metal wiring can be closer to a neutral surface, and the bending performance of the bending area is facilitated.
The array substrate and the manufacturing method thereof provided by the embodiments of the present application are described in detail above, and the principle and the implementation manner of the present application are explained in the present application by applying specific examples, and the description of the embodiments above is only used to help understanding the technical scheme and the core idea of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.
Claims (10)
1. An array substrate comprising a display region and a non-display region surrounding the display region, the non-display region having a bending region therein, comprising:
a flexible substrate extending from the display region to the non-display region;
the buffer layer is arranged on the flexible substrate and extends from the display area to the non-display area;
the thin film transistor structure layer is arranged on the buffer layer and extends from the display area to the non-display area; the thin film transistor structure layer has
The groove is arranged in the bending area and extends into the buffer layer from one surface, far away from the buffer layer, of the thin film transistor structure layer; and
the through hole is arranged in the display area and extends into the thin film transistor structure layer from one surface, far away from the buffer layer, of the thin film transistor structure layer;
the metal routing is filled in the through hole and extends one surface of the thin film transistor structure layer far away from the buffer layer to form a source drain electrode; part of metal wires cover the groove wall of the groove and extend to one surface of the thin film transistor structure layer far away from the buffer layer to form source drain electrode wires; and
the array substrate further comprises a flat layer which covers one surface of the thin film transistor structure layer, which is far away from the buffer layer, and the flat layer is filled in the groove.
2. The array substrate of claim 1,
the depth of the groove is
3. The array substrate of claim 1,
the flexible substrate includes:
a first PI substrate;
a first barrier layer disposed on the first PI substrate;
a second PI substrate arranged on the first barrier layer; and
and the second barrier layer is arranged on the second PI substrate.
4. The array substrate of claim 3,
the second barrier layer has a thickness of
5. The array substrate of claim 1,
the thin film transistor structure layer includes:
a first gate insulating layer disposed on the buffer layer and the active layer and extending from the display region to the non-display region;
the first grid electrode is arranged on the first grid electrode insulating layer and is positioned in the display area;
the second grid electrode insulating layer is arranged on the first grid electrode insulating layer and the first grid electrode and extends from the display area to the non-display area;
the second grid electrode is arranged on the second grid electrode insulating layer and is positioned in the display area; and
and the dielectric layer is arranged on the second grid electrode insulating layer and the second grid electrode and extends from the display area to the non-display area.
6. A preparation method of an array substrate comprises a display area and a non-display area surrounding the display area, wherein the non-display area is provided with a bending area, and the preparation method is characterized by comprising the following steps:
forming a flexible substrate extending from the display area to the non-display area;
forming a buffer layer on the flexible substrate, the buffer layer extending from the display region to the non-display region;
forming a thin film transistor structure layer on the buffer layer, wherein the thin film transistor structure layer extends from the display area to the non-display area;
forming a groove and a via hole, wherein the groove is arranged in the bending region and extends into the buffer layer from one surface, far away from the buffer layer, of the thin film transistor structure layer; the through hole is arranged in the display area and extends into the thin film transistor structure layer from the upper surface of the thin film transistor structure layer;
forming metal wires, wherein part of the metal wires are filled in the via holes and extend to one surface of the thin film transistor structure layer far away from the buffer layer to form a source drain electrode; part of metal wires cover the groove wall of the groove and extend to one surface of the thin film transistor structure layer far away from the buffer layer to form source drain electrode wires; and
and forming a flat layer, wherein the flat layer covers the upper surface of the thin film transistor structure layer and is filled in the groove.
7. The method of claim 6, wherein the step of forming the array substrate comprises the steps of,
in the step of forming the via holes and the grooves, a photomask is adopted to etch the thin film transistor structure layer to form the via holes and the grooves.
8. The method of claim 6, wherein the step of forming the array substrate comprises the steps of,
the depth of the groove is
9. The method of claim 6, wherein the step of forming the array substrate comprises the steps of,
in the step of forming a flexible substrate, the method further includes:
forming a first PI substrate;
forming a first barrier layer on the first PI substrate;
forming a second PI substrate on the first barrier layer; and
forming a second barrier layer on the second PI substrate;
wherein the second barrier layer has a thickness of
10. The method of claim 6, wherein the step of forming the array substrate comprises the steps of,
the step of forming the thin film transistor structure layer on the buffer layer includes:
forming a first gate insulating layer on the buffer layer and the active layer, the first gate insulating layer extending from the display region to the non-display region;
forming a first gate on the first gate insulating layer, the first gate being located in the display region;
forming a second gate insulating layer on the first gate insulating layer and the first gate, the second gate insulating layer extending from the display region to the non-display region;
forming a second gate on the second gate insulating layer, the second gate being located in the display region; and
and forming a dielectric layer on the second gate insulating layer and the second gate, wherein the dielectric layer extends from the display region to the non-display region.
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