CN112309988A - Display panel and manufacturing method thereof - Google Patents
Display panel and manufacturing method thereof Download PDFInfo
- Publication number
- CN112309988A CN112309988A CN202011138885.3A CN202011138885A CN112309988A CN 112309988 A CN112309988 A CN 112309988A CN 202011138885 A CN202011138885 A CN 202011138885A CN 112309988 A CN112309988 A CN 112309988A
- Authority
- CN
- China
- Prior art keywords
- layer
- groove
- display panel
- interlayer dielectric
- organic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 36
- 239000010410 layer Substances 0.000 claims abstract description 310
- 229910052751 metal Inorganic materials 0.000 claims abstract description 64
- 239000002184 metal Substances 0.000 claims abstract description 64
- 239000011229 interlayer Substances 0.000 claims abstract description 54
- 238000000034 method Methods 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 230000008569 process Effects 0.000 claims abstract description 11
- 239000002346 layers by function Substances 0.000 claims abstract description 7
- 238000009413 insulation Methods 0.000 claims abstract description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 52
- 239000000463 material Substances 0.000 claims description 21
- 238000005530 etching Methods 0.000 claims description 8
- 230000001678 irradiating effect Effects 0.000 claims description 7
- 238000010438 heat treatment Methods 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 239000011733 molybdenum Substances 0.000 claims description 3
- 238000007790 scraping Methods 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 239000010408 film Substances 0.000 description 6
- -1 polyethylene terephthalate Polymers 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 239000004698 Polyethylene Substances 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 4
- 239000012044 organic layer Substances 0.000 description 4
- 229920000573 polyethylene Polymers 0.000 description 4
- 229920000139 polyethylene terephthalate Polymers 0.000 description 4
- 239000005020 polyethylene terephthalate Substances 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 3
- 230000004308 accommodation Effects 0.000 description 3
- 238000005452 bending Methods 0.000 description 3
- 229910017604 nitric acid Inorganic materials 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 239000004743 Polypropylene Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 229910010272 inorganic material Inorganic materials 0.000 description 2
- 239000011147 inorganic material Substances 0.000 description 2
- 239000011368 organic material Substances 0.000 description 2
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 229920000058 polyacrylate Polymers 0.000 description 2
- 239000004417 polycarbonate Substances 0.000 description 2
- 229920000515 polycarbonate Polymers 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229920001155 polypropylene Polymers 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 2
- 239000011787 zinc oxide Substances 0.000 description 2
- 229910001928 zirconium oxide Inorganic materials 0.000 description 2
- 239000002253 acid Substances 0.000 description 1
- 230000002378 acidificating effect Effects 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/1201—Manufacture or treatment
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electroluminescent Light Sources (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The invention discloses a display panel and a manufacturing method thereof, wherein the manufacturing method of the display panel comprises the following steps: sequentially forming a buffer layer, an inorganic layer, a first grid insulating layer, a second grid insulating layer and an interlayer dielectric layer on the first surface of the substrate layer; processing the buffer layer, the inorganic layer, the first gate insulating layer, the second gate insulating layer and the interlayer dielectric layer by using a yellow light process to form at least one groove, wherein the bottom of the groove is positioned on the first surface; forming an organic filling layer in the groove, wherein the first surface of the organic filling layer is flush with the opening of the groove; forming a metal wire on the first surface of the organic filling layer and a part of one surface of the interlayer dielectric layer, which is far away from the second grid insulation layer; and forming a light-emitting functional layer on the interlayer dielectric layer.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display panel and a manufacturing method thereof.
Background
An Organic Light-Emitting Diode (OLED) display panel has the advantages of low voltage requirement, high power saving efficiency, fast response, Light weight, thin thickness, simple structure, low cost, wide viewing angle, almost infinite contrast, low power consumption, and high response speed, and is one of the most important display technologies today.
Flexible display panels have been developed rapidly in recent years due to their advantages of being light, thin, bendable, and foldable. Especially foldable display panels, have been identified as an important direction for future development. Since the foldable display panel has a certain Shift (Shift) at the folding position after being folded many times, in order to reduce the Shift of the electrical property of the display panel caused by folding, the known technology sets a groove in the display panel and fills the groove with an organic photoresist material, which aims to release the stress during folding and reduce the influence on the electrical property of the display panel.
However, after the grooves are filled with the organic photoresist material, the organic photoresist material may overflow to a certain extent, so that the slope of the organic photoresist material at the grooves is high, and the metal layer is prone to have a risk of line thinning or even line breakage at the grooves.
Therefore, a new technical solution is needed to solve the above technical problems.
Disclosure of Invention
The embodiment of the invention provides a display panel and a manufacturing method thereof, which are used for avoiding the risk of line thinning and even line breaking of metal wires caused by overflow of organic photoresist materials at grooves.
The embodiment of the invention provides a manufacturing method of a display panel, which comprises the following steps:
step A: sequentially forming a buffer layer, an inorganic layer, a first grid insulating layer, a second grid insulating layer and an interlayer dielectric layer on the first surface of the substrate layer;
and B: processing the buffer layer, the inorganic layer, the first gate insulating layer, the second gate insulating layer and the interlayer dielectric layer by using a yellow light process to form at least one groove, wherein the bottom of the groove is positioned on the first surface;
and C: forming an organic filling layer in the groove, wherein the first surface of the organic filling layer is flush with the opening of the groove;
step D: forming a metal wire on the first surface of the organic filling layer and a part of one surface of the interlayer dielectric layer, which is far away from the second grid insulation layer;
step E: and forming a light-emitting functional layer on the interlayer dielectric layer.
In the method for manufacturing a display panel according to the embodiment of the present invention, the step C includes:
step c 11: filling organic photoresist material in the groove;
step c 12: and irradiating or heating the organic photoresist material by using ultraviolet rays, so that the organic photoresist material is cured to form the organic filling layer.
In the manufacturing method of the display panel provided in the embodiment of the present invention, after the step c12, the method further includes:
step c 13: scraping the organic filling layer on the opening by using a scraper so that the first surface of the organic filling layer is flush with the opening.
In the manufacturing method of the display panel provided in the embodiment of the present invention, the step D includes:
step d 11: forming a metal layer on the first surface of the organic filling layer and the surface, far away from the second grid electrode insulating layer, of the interlayer dielectric layer;
step d 12: forming a photoresist layer on the metal layer;
step d 13: setting a mask plate on the photoresist layer, wherein the mask plate comprises a light-transmitting part and a light-tight part, the light-tight part corresponds to the organic filling layer and a part of the interlayer medium layer, and the width of the light-tight part corresponding to the organic filling layer is larger than that of the light-tight part corresponding to the interlayer medium layer;
step d 14: irradiating the mask plate with ultraviolet rays;
step d 15: stripping the photoresist layer corresponding to the light-transmitting part;
step d 16: etching the metal layer corresponding to the light-transmitting part to form the metal routing;
step d 17: and stripping the photoresist layer corresponding to the opaque part.
In the manufacturing method of the display panel provided by the embodiment of the invention, the width of the metal wire on the first surface of the organic filling layer is greater than the width of the metal wire on the first surface of the interlayer dielectric layer.
In the method for manufacturing a display panel provided in the embodiment of the present invention, after step B, the method further includes:
step E: and detecting the accommodating space of each groove, and adjusting the accommodating space of each groove to ensure that the accommodating space of each groove is the same or approximately the same.
An embodiment of the present invention further provides a display panel, where the display panel includes:
a substrate layer;
the buffer layer, the inorganic layer, the first grid insulating layer, the second grid insulating layer and the interlayer dielectric layer are sequentially stacked on the first surface of the substrate layer;
the groove penetrates through the buffer layer, the inorganic layer, the first grid electrode insulating layer, the second grid electrode insulating layer and the interlayer dielectric layer, wherein the bottom of the groove is positioned on the first surface;
the organic filling layer is arranged in the groove, and the first surface of the organic filling layer is flush with the opening of the groove;
the metal wire is arranged on the first surface of the organic filling layer and covers a part of one surface of the interlayer dielectric layer, which is far away from the second grid electrode insulating layer;
and the light-emitting functional layer is arranged on one surface of the interlayer dielectric layer, which is far away from the second grid insulation layer.
In the display panel provided in the embodiment of the present invention, the width of the metal trace on the first surface of the organic filling layer is greater than the width of the metal trace on the first surface of the interlayer dielectric layer.
In the display panel provided in the embodiment of the present invention, the material of the metal trace includes one or a stacked combination of at least two of copper, aluminum, molybdenum, and titanium.
In the display panel provided by the embodiment of the invention, each groove has the same or approximately the same accommodating space.
In the manufacturing method of the display panel provided by the embodiment of the invention, the first surface of the organic filling layer formed by curing the organic photoresist material is flush with the first surface of the groove by reducing the coating amount of the organic photoresist material, so that the organic filling layer is prevented from overflowing, and the risk of fine wires and even broken wires of metal wires positioned above the organic filling layer is avoided.
In addition, in the manufacturing method of the display panel provided by the embodiment of the invention, the width of the metal wire arranged on the organic filling layer is larger than the width of the metal wire arranged on the interlayer dielectric layer, and the arrangement mode is further used for preventing the risk of line thinning and even line breakage of the metal wire above the organic filling layer.
In order to make the aforementioned and other objects of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1 is a flowchart illustrating steps of a method for manufacturing a display panel according to an embodiment of the present invention;
fig. 2 is a schematic diagram of step S1 in the method for manufacturing a display panel according to the embodiment of the invention;
fig. 3 is a schematic diagram of step S2 in the method for manufacturing a display panel according to the embodiment of the invention;
fig. 4 is a flowchart illustrating a step S3 in the method for manufacturing a display panel according to the embodiment of the present invention;
fig. 5 is a flowchart illustrating another step of step S3 in the method for manufacturing a display panel according to the embodiment of the present invention;
fig. 6 is a schematic diagram of step S3 in the method for manufacturing a display panel according to the embodiment of the present invention;
fig. 7 is a flowchart illustrating a step S4 in the method for manufacturing a display panel according to the embodiment of the present invention;
fig. 8 is a schematic diagram of step S4 in the method for manufacturing a display panel according to the embodiment of the present invention;
FIG. 9 is a top view of the masking plate of FIG. 8;
fig. 10 is a schematic view of the display panel manufacturing method according to the embodiment of the invention after step S4 is completed;
FIG. 11 is a top view of the metal trace of FIG. 10;
fig. 12 is a schematic structural diagram of a display panel according to an embodiment of the present invention.
Detailed Description
For purposes of clarity, technical solutions and advantages of the present invention, the present invention will be described in further detail with reference to the accompanying drawings, wherein like reference numerals represent like elements, and the following description is based on the illustrated embodiments of the present invention and should not be construed as limiting the other embodiments of the present invention which are not described in detail herein. The word "embodiment" as used herein means an example, instance, or illustration.
In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
Referring to fig. 1, an embodiment of the invention provides a method for manufacturing a display panel, including the following steps:
step S1: sequentially forming a buffer layer, an inorganic layer, a first grid insulating layer, a second grid insulating layer and an interlayer dielectric layer on the first surface of the substrate layer;
the substrate layer 101 includes a first flexible substrate layer 101a, a barrier layer 101b, and a second flexible substrate layer 101c, which are stacked in sequence.
Specifically, referring to fig. 2, in step S1, a buffer layer 102, an inorganic layer 103, a first gate insulating layer 104, a second gate insulating layer 105, and an interlayer dielectric layer 106 are sequentially deposited on the first surface 1011.
Step S1 further includes: an active layer 110a, a first gate electrode 110b, and a second gate electrode 110c are formed. The active layer 110a is disposed on the first surface 1011. The first gate electrode 110b is disposed on a side of the first gate insulating layer 104 away from the inorganic layer 103. The second gate 110c is disposed on a side of the second gate insulating layer 105 away from the first gate insulating layer 104.
Step S2: processing the buffer layer, the inorganic layer, the first gate insulating layer, the second gate insulating layer and the interlayer dielectric layer by using a yellow light process to form at least one groove, wherein the bottom of the groove is positioned on the first surface;
referring to fig. 3, in step S2, an organic photoresist layer is first formed on the interlayer dielectric layer 106, and then the buffer layer 102, the inorganic layer 103, the first gate insulating layer 104, the second gate insulating layer 105 and the corresponding portion of the interlayer dielectric layer 106 are processed by an exposure process, a development process and an etching process to form a groove 107. It should be noted that the number of the grooves in this embodiment is at least one.
Optionally, in some embodiments, step S2 further includes: forming a first via hole 111 and a second via hole 112, wherein the first via hole 111 and the second via hole 112 and the groove 107 can be formed by the same photolithography process.
In some embodiments, the groove 107 is inverted trapezoidal, and the sides of the groove 107 are "zigzag".
Optionally, in some embodiments, after step S2, the method further includes:
the accommodation space of each of the grooves 107 is detected, and the accommodation space of the grooves 107 is adjusted so that the accommodation spaces of the grooves 107 are the same or substantially the same. For example, the accommodating space of each of the grooves 107 is detected by a detector, and if the accommodating spaces of the grooves 107 are not consistent, the accommodating spaces are adjusted by an etching process so that the accommodating spaces of the grooves 107 are the same or substantially the same. It should be noted that the accommodating space in the embodiment of the present invention may be an accommodating volume.
Step S3: forming an organic filling layer in the groove, wherein the first surface of the organic filling layer is flush with the opening of the groove;
referring to fig. 4, fig. 4 is a flowchart illustrating a step S3 in the method for manufacturing a display panel. Specifically, step S3 includes:
step S31: filling organic photoresist material in the groove;
step S32: and irradiating or heating the organic photoresist material by using ultraviolet rays, so that the organic photoresist material is cured to form the organic filling layer.
Specifically, referring to fig. 6, an organic photoresist is coated in the groove 107, and then the organic photoresist is cured by irradiating or heating with ultraviolet rays to form the organic filling layer 108.
It should be noted that, in some embodiments, since the amount of the organic photoresist coating is difficult to control, the slope of the organic filling layer 108 formed by curing is so high that the metal trace on the organic filling layer 108 is prone to have a risk of wire thinning or even wire breakage in the subsequent metal trace fabrication. The overflow of the organic filling layer 108 formed by curing can be prevented by controlling the number of times of coating the organic photoresist, for example, the volume of the organic photoresist coated for the first time is smaller than the volume of the groove 107, and then the organic photoresist coated for the first time is irradiated or heated by ultraviolet rays to form a first organic filling layer; next, an organic photoresist is coated on the first organic filling layer, the upper surface of the organic photoresist is controlled to be flush or approximately flush with the opening of the groove 107, and then the organic photoresist coated for the second time is irradiated or heated by ultraviolet rays to form a second organic filling layer.
Optionally, referring to fig. 5, bubbles may occur during the curing of the organic photoresist, which may cause the cured organic photoresist to overflow, resulting in a higher slope of the organic photoresist in the groove 107. In order to prevent the metal trace from being easily thinned or even broken in the subsequent process of the metal trace, the method further includes, after step S32:
step S33: scraping the organic filling layer on the opening by using a scraper so that the first surface of the organic filling layer is flush with the opening.
It should be noted that, in the embodiment of the present invention, the first surface 108a of the organic filling layer 108 is flush with the opening 107a, which means that the difference between the height of the organic filling layer 108 and the height of the groove 107 is between-10% and 10%.
Step S4: forming a metal wire on the first surface of the organic filling layer and a part of one surface of the interlayer dielectric layer, which is far away from the second grid insulation layer;
referring to fig. 7, step S4 includes the following steps:
step S41: forming a metal layer on the first surface of the organic filling layer and the surface, far away from the second grid electrode insulating layer, of the interlayer dielectric layer;
specifically, please refer to fig. 8. First, in step S41, a metal layer 113 is deposited on the first surface 108a of the organic filling layer 108 and the surface of the interlayer dielectric layer 106 away from the second gate insulating layer 105 by using a sputtering method or a physical vapor deposition method.
Step S42: forming a photoresist layer on the metal layer;
a photoresist layer 114 is formed on the metal layer 113, and the material of the photoresist layer 114 may be a positive organic photoresist or a negative organic photoresist.
Step S43: setting a mask plate on the photoresist layer, wherein the mask plate comprises a light-transmitting part and a light-tight part, the light-tight part corresponds to the organic filling layer and a part of the interlayer medium layer, and the width of the light-tight part corresponding to the organic filling layer is larger than that of the light-tight part corresponding to the interlayer medium layer;
referring to fig. 8 and 9, fig. 9 is a top view of the mask M in fig. 8. The mask M is mounted on the photoresist layer 114, and the distance between the mask M and the photoresist layer 114 is greater than zero. The mask M comprises a light-transmitting portion M1 and a light-proof portion M2, wherein the light-proof portion M2 corresponds to the organic filling layer 108 and a part of the interlayer medium layer 106, and the width W1 of the light-proof portion M2 corresponding to the organic filling layer 108 is larger than the width W2 of the light-proof portion M2 corresponding to the interlayer medium layer 106.
Step S44: irradiating the mask plate with ultraviolet rays;
the mask plate M is irradiated with ultraviolet rays, so that the light blocking layer 114 corresponding to the light transmitting portion M1 is softened.
Step S45: stripping the photoresist layer corresponding to the light-transmitting part;
specifically, a developing solution is sprayed onto the photoresist layer 114 corresponding to the light-transmitting portion M1 to remove the photoresist layer 114 corresponding to the light-transmitting portion M1.
Step S46: etching the metal layer corresponding to the light-transmitting part to form the metal routing;
and etching the metal layer 113 corresponding to the light-transmitting portion M1 by using an acidic etching solution to form a metal trace 109. The acid etching liquid comprises a combination of hydrofluoric acid and nitric acid, a combination of hydrochloric acid and nitric acid, a combination of phosphoric acid and nitric acid and the like.
Step S47: and stripping the photoresist layer corresponding to the opaque part.
The photoresist layer 114 corresponding to the opaque portion M2 is stripped, please refer to fig. 10.
Referring to fig. 10 and fig. 11, fig. 11 is a top view of the metal trace in fig. 10. The width W3 of the metal trace 109 on the first side 108a of the organic filling layer 108 is greater than the width W4 of the metal trace 109 on the interlayer dielectric layer 106. In this embodiment, the width W3 of the metal trace 109 disposed on the organic filling layer 108 is greater than the width W4 of the metal trace 109 disposed on the interlayer dielectric layer 106, and this arrangement is used to prevent the risk of line thinning or even line breakage of the metal trace 109 above the organic filling layer 108.
With continued reference to fig. 11, step S4 further includes: forming a source 110d and a drain 110e, wherein the source 110d is electrically connected with the active layer 110a through a first via hole 111; the drain electrode 110e is electrically connected to the active layer 110a through a second via 112. The source 110d and the drain 110e are formed during the process of forming the metal trace 109, that is, the same mask plate may be used to form the source 110d, the drain 110e and the metal trace 109.
Step S5: and forming a light-emitting functional layer on the interlayer dielectric layer.
Referring to fig. 12, the method for manufacturing the display panel further includes forming a planarization layer 204, wherein the planarization layer 204 is disposed on the interlayer dielectric layer 106, and the source 110d, the drain 110e and the metal trace 109 are covered by the planarization layer 204. The light emitting function layer 20 includes an anode layer 201, a light emitting layer 202, and a cathode layer 203. The anode layer 201 is disposed on the planarization layer 204 and electrically connected to the drain 110e through the via hole. The light emitting layer 202 is defined within an opening of the pixel defining layer 205. The cathode layer 203 covers the light emitting layer and the pixel defining layer 205.
In this embodiment, after step S5, the method may further include: an encapsulation layer is formed covering the cathode layer 203. The packaging layer comprises at least one inorganic layer and at least one organic layer which are alternately stacked. The inorganic layer may be selected from inorganic materials of alumina, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, titanium oxide, zirconium oxide, zinc oxide, and the like. The organic layer is an organic material selected from epoxy resin, Polyimide (PI), polyethylene terephthalate (PET), Polycarbonate (PC), Polyethylene (PE), polyacrylate, and the like. For example, the encapsulation layer has a laminated structure of an alumina film, a polypropylene film, and a silicon nitride film, which are laminated in this order.
Referring to fig. 12, an embodiment of the invention further provides a display panel, wherein the display panel 100 is manufactured by the above-mentioned manufacturing method of the display panel.
Specifically, the display panel 10 includes a substrate layer 101, a buffer layer 102, an inorganic layer 103, a first gate insulating layer 104, a second gate insulating layer 105, an interlayer dielectric layer 106, at least one groove 107, an organic filling layer 108, a metal trace 109, and a light emitting functional layer 20, which are sequentially stacked on a first surface 1011 of the substrate layer 101.
Specifically, the substrate layer 101 includes a first flexible base layer 101a, a barrier layer 101b, and a second flexible base layer 101c, which are sequentially stacked.
The thin film transistor includes an active layer 110a, a first gate electrode 110b, a second gate electrode 110c, a source electrode 110d, and a drain electrode 110 e. The active layer 110a is disposed on the first surface 1011. The first gate electrode 110b is disposed on a side of the first gate insulating layer 104 away from the inorganic layer 103. The second gate 110c is disposed on a side of the second gate insulating layer 105 away from the first gate insulating layer 104. The source 110d is electrically connected to the active layer 110a through a first via; the drain electrode 110e is electrically connected to the active layer 110a through a second via hole.
The groove 107 penetrates through the buffer layer 102, the inorganic layer 103, the first gate insulating layer 104, the second gate insulating layer 105 and the interlayer dielectric layer 106, wherein the bottom of the groove 107 is located on the first surface 1011.
The organic filling layer 108 is disposed in the groove 107, and a first surface 108a of the organic filling layer 108 is flush with the opening 107a of the groove 107. Each of the grooves 107 has the same or substantially the same receiving space.
The metal trace 109 is disposed on the first surface 108a of the organic filling layer 108 and covers a portion of a surface of the interlayer dielectric layer 106 away from the second gate insulating layer 105. Referring to fig. 11, the width W3 of the metal trace 109 on the first surface 108a of the organic filling layer 108 is greater than the width W4 of the metal trace 109 on the interlayer dielectric layer 106. In this embodiment, the width W3 of the metal trace 109 disposed on the organic filling layer 108 is greater than the width W4 of the metal trace 109 disposed on the interlayer dielectric layer 106, and this arrangement is used to prevent the risk of line thinning or even line breakage of the metal trace 109 above the organic filling layer 108. The metal routing wire is made of one or a stack combination of copper, aluminum, molybdenum and titanium.
The light emitting function layer 20 is disposed on a surface of the interlayer dielectric layer 106 away from the second gate insulating layer 105. The light emitting function layer 20 includes an anode layer 201, a light emitting layer 202, and a cathode layer 203. The anode layer 201 is disposed on the planarization layer 204 and electrically connected to the drain 110e through the via hole. The light emitting layer 202 is defined within an opening of the pixel defining layer 205. The cathode layer 203 covers the light emitting layer and the pixel defining layer 205.
Optionally, the display panel 100 may further include an encapsulation layer covering the cathode layer 203. The packaging layer comprises at least one inorganic layer and at least one organic layer which are alternately stacked. The inorganic layer may be selected from inorganic materials of alumina, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, titanium oxide, zirconium oxide, zinc oxide, and the like. The organic layer is an organic material selected from epoxy resin, Polyimide (PI), polyethylene terephthalate (PET), Polycarbonate (PC), Polyethylene (PE), polyacrylate, and the like. For example, the encapsulation layer has a laminated structure of an alumina film, a polypropylene film, and a silicon nitride film, which are laminated in this order.
In some embodiments, the display panel 100 includes a display region, a bending region and a peripheral region, wherein the thin film transistor is disposed at a portion corresponding to the display region, a groove is disposed at a portion corresponding to the bending region, and a groove is disposed at a portion corresponding to the peripheral region. And the accommodating space of the groove corresponding to the bending area is equal to the accommodating space of the groove corresponding to the peripheral area.
In the manufacturing method of the display panel provided by the embodiment of the invention, the first surface of the organic filling layer formed by curing the organic photoresist material is flush with the first surface of the groove by reducing the coating amount of the organic photoresist material, so that the organic filling layer is prevented from overflowing, and the risk of fine wires and even broken wires of metal wires positioned above the organic filling layer is avoided.
In addition, in the manufacturing method of the display panel provided by the embodiment of the invention, the width of the metal wire arranged on the organic filling layer is larger than the width of the metal wire arranged on the interlayer dielectric layer, and the arrangement mode is further used for preventing the risk of line thinning and even line breakage of the metal wire above the organic filling layer.
In summary, although the present invention has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, therefore, the scope of the present invention shall be determined by the appended claims.
Claims (10)
1. The manufacturing method of the display panel is characterized by comprising the following steps of:
step A: sequentially forming a buffer layer, an inorganic layer, a first grid insulating layer, a second grid insulating layer and an interlayer dielectric layer on the first surface of the substrate layer;
and B: processing the buffer layer, the inorganic layer, the first gate insulating layer, the second gate insulating layer and the interlayer dielectric layer by using a yellow light process to form at least one groove, wherein the bottom of the groove is positioned on the first surface;
and C: forming an organic filling layer in the groove, wherein the first surface of the organic filling layer is flush with the opening of the groove;
step D: forming a metal wire on the first surface of the organic filling layer and a part of one surface of the interlayer dielectric layer, which is far away from the second grid insulation layer;
step E: and forming a light-emitting functional layer on the interlayer dielectric layer.
2. The method for manufacturing a display panel according to claim 1, wherein the step C comprises:
step c 11: filling organic photoresist material in the groove;
step c 12: and irradiating or heating the organic photoresist material by using ultraviolet rays, so that the organic photoresist material is cured to form the organic filling layer.
3. The method for manufacturing a display panel according to claim 2, further comprising, after the step c 12:
step c 13: scraping the organic filling layer on the opening by using a scraper so that the first surface of the organic filling layer is flush with the opening.
4. The method for manufacturing a display panel according to claim 1, wherein the step D comprises:
step d 11: forming a metal layer on the first surface of the organic filling layer and the surface, far away from the second grid electrode insulating layer, of the interlayer dielectric layer;
step d 12: forming a photoresist layer on the metal layer;
step d 13: setting a mask plate on the photoresist layer, wherein the mask plate comprises a light-transmitting part and a light-tight part, the light-tight part corresponds to the organic filling layer and a part of the interlayer medium layer, and the width of the light-tight part corresponding to the organic filling layer is larger than that of the light-tight part corresponding to the interlayer medium layer;
step d 14: irradiating the mask plate with ultraviolet rays;
step d 15: stripping the photoresist layer corresponding to the light-transmitting part;
step d 16: etching the metal layer corresponding to the light-transmitting part to form the metal routing;
step d 17: and stripping the photoresist layer corresponding to the opaque part.
5. The method for manufacturing the display panel according to claim 4, wherein the width of the metal trace on the first side of the organic filling layer is greater than the width of the metal trace on the first side of the interlayer dielectric layer.
6. The method for manufacturing a display panel according to claim 1, further comprising, after the step B:
step E: and detecting the accommodating space of each groove, and adjusting the accommodating space of each groove to ensure that the accommodating space of each groove is the same or approximately the same.
7. A display panel, comprising:
a substrate layer;
the buffer layer, the inorganic layer, the first grid insulating layer, the second grid insulating layer and the interlayer dielectric layer are sequentially stacked on the first surface of the substrate layer;
the groove penetrates through the buffer layer, the inorganic layer, the first grid electrode insulating layer, the second grid electrode insulating layer and the interlayer dielectric layer, wherein the bottom of the groove is positioned on the first surface;
the organic filling layer is arranged in the groove, and the first surface of the organic filling layer is flush with the opening of the groove;
the metal wire is arranged on the first surface of the organic filling layer and covers a part of one surface of the interlayer dielectric layer, which is far away from the second grid electrode insulating layer;
and the light-emitting functional layer is arranged on one surface of the interlayer dielectric layer, which is far away from the second grid insulation layer.
8. The display panel of claim 7, wherein the width of the metal trace on the first side of the organic filling layer is greater than the width of the metal trace on the first side of the interlayer dielectric layer.
9. The display panel of claim 7, wherein the material of the metal trace comprises one or a stacked combination of at least two of copper, aluminum, molybdenum, and titanium.
10. The display panel according to claim 7, wherein each of the grooves has the same or substantially the same receiving space.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011138885.3A CN112309988B (en) | 2020-10-22 | 2020-10-22 | Display panel and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011138885.3A CN112309988B (en) | 2020-10-22 | 2020-10-22 | Display panel and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112309988A true CN112309988A (en) | 2021-02-02 |
| CN112309988B CN112309988B (en) | 2022-09-27 |
Family
ID=74326980
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011138885.3A Active CN112309988B (en) | 2020-10-22 | 2020-10-22 | Display panel and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112309988B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103219336A (en) * | 2013-03-29 | 2013-07-24 | 京东方科技集团股份有限公司 | Array substrate, display device and preparation method of array substrate |
| CN109599419A (en) * | 2018-10-23 | 2019-04-09 | 武汉华星光电半导体显示技术有限公司 | A kind of array substrate and its manufacturing method |
| CN110085553A (en) * | 2019-04-22 | 2019-08-02 | 武汉华星光电半导体显示技术有限公司 | OLED array and preparation method thereof |
| CN111063697A (en) * | 2019-12-11 | 2020-04-24 | 武汉华星光电半导体显示技术有限公司 | Array substrate, preparation method thereof and display panel |
| CN111463243A (en) * | 2020-04-09 | 2020-07-28 | 武汉华星光电半导体显示技术有限公司 | Array substrate and preparation method thereof |
-
2020
- 2020-10-22 CN CN202011138885.3A patent/CN112309988B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103219336A (en) * | 2013-03-29 | 2013-07-24 | 京东方科技集团股份有限公司 | Array substrate, display device and preparation method of array substrate |
| CN109599419A (en) * | 2018-10-23 | 2019-04-09 | 武汉华星光电半导体显示技术有限公司 | A kind of array substrate and its manufacturing method |
| CN110085553A (en) * | 2019-04-22 | 2019-08-02 | 武汉华星光电半导体显示技术有限公司 | OLED array and preparation method thereof |
| CN111063697A (en) * | 2019-12-11 | 2020-04-24 | 武汉华星光电半导体显示技术有限公司 | Array substrate, preparation method thereof and display panel |
| CN111463243A (en) * | 2020-04-09 | 2020-07-28 | 武汉华星光电半导体显示技术有限公司 | Array substrate and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112309988B (en) | 2022-09-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP3651002B1 (en) | Display device | |
| CN108123062B (en) | Organic light emitting display device | |
| CN108352457B (en) | Stacked pattern of OLED display | |
| CN111211145A (en) | Display device | |
| KR101373435B1 (en) | Display substrate, organic emitting diode display device having the same and method of manufacturing thereof | |
| CN108292712B (en) | Display substrate, display panel, display apparatus, and methods of manufacturing display substrate and display panel | |
| CN107994058B (en) | Display base plate and its manufacturing method, display panel and its packaging method | |
| CN111625130A (en) | Touch display panel and touch display device | |
| CN108962948B (en) | Array substrate and manufacturing method thereof | |
| CN108281475B (en) | Display panel, manufacturing method thereof and display device | |
| JP2018124504A (en) | Display device | |
| CN111602466B (en) | Display device and method for manufacturing display device | |
| CN102709243A (en) | Organic light-emitting diode display panel and manufacturing method thereof | |
| CN111081738B (en) | OLED display panel | |
| CN110246983B (en) | Organic light-emitting display panel, manufacturing method thereof and packaging film | |
| KR101984641B1 (en) | Substrate imprinted with a pattern for forming isolated device regions | |
| CN110649176A (en) | Anode plate, display panel and display device | |
| CN112309988B (en) | Display panel and manufacturing method thereof | |
| US11793027B2 (en) | Display panel and method for manufacturing the same, and display device | |
| JP2008112658A (en) | Electrooptical device, electronic equipment, color filter device, and image display equipment | |
| US20210359076A1 (en) | Organic electroluminescent device and method for producing same | |
| CN102479798A (en) | Organic light emitting display device and method for manufacturing the same | |
| CN112310327B (en) | Display panel and display device | |
| CN113270460A (en) | Display panel, preparation method thereof and display device | |
| CN108336098B (en) | Anti-static electrode structure and display panel |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |