CN103915450A - Array substrate, manufacturing method and display device - Google Patents

Array substrate, manufacturing method and display device Download PDF

Info

Publication number
CN103915450A
CN103915450A CN201410120715.0A CN201410120715A CN103915450A CN 103915450 A CN103915450 A CN 103915450A CN 201410120715 A CN201410120715 A CN 201410120715A CN 103915450 A CN103915450 A CN 103915450A
Authority
CN
China
Prior art keywords
wire
grid lead
via hole
grid
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201410120715.0A
Other languages
Chinese (zh)
Other versions
CN103915450B (en
Inventor
周纪登
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Hefei Xinsheng Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN201410120715.0A priority Critical patent/CN103915450B/en
Publication of CN103915450A publication Critical patent/CN103915450A/en
Application granted granted Critical
Publication of CN103915450B publication Critical patent/CN103915450B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Abstract

The invention relates to the technical field of display devices, and discloses an array substrate, a manufacturing method and a display device. The array substrate comprises a first grid lead, a second grid lead and a grid insulation layer, wherein the first grid lead and the second grid lead are arranged at the peripheral region of the array substrate, and the grid insulation layer is located between the first grid lead and the second grid lead. The array substrate further comprises a plurality of via holes formed in the first grid lead in an etching mode, the second grid lead is arranged in at least a part of each via hole in a penetrating mode, and first transparent conducting layers for conducting the first grid lead and the second grid lead are arranged in the via holes. The array substrate, the manufacturing method and the display device have the advantages that according to the via hole structure, conduction connection of the first grid lead and the second grid lead can be achieved through a single row of via holes, therefore, the width of the first gird lead can be reduced, the aperture ratio of the display device can be increased, and the display effect of the display device can be enhanced.

Description

A kind of array base palte, manufacture method and display unit
Technical field
The present invention relates to the technical field of display unit, refer more particularly to a kind of array base palte, manufacture method and display unit.
Background technology
On the array base palte of array base palte, have 8~10 layers of metal or insulating barrier at least, these metal levels and insulating barrier have guaranteed the TFT function normal operation on array base palte just, control array base palte and show according to set input signal.In order to make same layer metal, or different layers metallic communication, on the array base palte of TFT-LCD, needing a large amount of via holes, some via holes play the effect of lower metal layer conducting, and some via holes play the effect of bridge conducting same layer metal.Therefore in the structural design of array base palte, the structural design of via hole is extremely important.Improve the joint efficiency of via hole, reduce the quantity of via hole, not only can play the effect that increases array base palte aperture opening ratio, the space that can also save array substrate peripheral, also plays a role to the realization of narrow frame.
First grid lead-in wire on array base palte of the prior art and second grid lead-in wire connected mode are as depicted in figs. 1 and 2, accompanying drawing 1 shows the via hole between the lead-in wire of second grid in array base palte of the prior art and first grid lead-in wire, wherein 1 represents that first grid goes between; 2 represent first grid pilot protection layer; 3 represent second grid lead-in wire; 4 represent insulating barrier; 5 represent transparency conducting layer; 6-1 represents first grid lead-in wire via hole; 6-2 represents second grid lead-in wire via hole.From accompanying drawing 2, can find that first grid lead-in wire 1 and second grid lead-in wire 3 do not belong to same layer, have first grid pilot protection layer 2 between the two, and second grid lead-in wire 3 have insulating barrier above.In order to make 3 conductings that go between of first grid lead-in wire 1 and second grid, traditional Via Design is above first grid lead-in wire 1 and above second grid lead-in wire 3, to design via hole respectively, by out exposed in via hole separately first grid 1 metal and second grid 3 metals that go between that go between, finally by transparency conducting layer 5, first grid 1 via hole 6-1 and the second grid 3 via hole 6-2 that go between that go between are coupled together.The applicant finds, two via hole (6-1 of available technology adopting, 6-2) be communicated with first grid lead-in wire 1 and second grid lead-in wire 3, cause the width of first grid lead-in wire 1 larger, make the area of non-pixel region larger, and then have influence on the aperture opening ratio of display unit, reduce the display effect of display unit.
Summary of the invention
The invention provides a kind of array substrate manufacturing method and display unit, in order to improve the aperture opening ratio of display unit, and then the display effect of raising display unit.
The invention provides a kind of array base palte, this array base palte comprises: the first grid lead-in wire, second grid lead-in wire and the gate insulator between described first grid lead-in wire and second grid lead-in wire that are arranged on array base palte neighboring area, also comprise multiple via holes that are etched on described first grid lead-in wire, wherein, each via hole is at least partly through described second grid lead-in wire, and in each via hole, is provided with the first transparency conducting layer that first grid lead-in wire and second grid go between described in conducting.
In technique scheme, by changing the setting position of via hole, the first transparency conducting layer arranging in same via hole can be gone between first grid and the conducting of second grid lead-in wire, thereby reduce the horizontal number of via hole, and then reduce the width of first grid lead-in wire, thereby improve the aperture opening ratio of display unit, and then improved the display effect of display unit.
Preferably, described via hole is circular port, polygonal hole or irregularly-shaped hole.This via hole can be selected different shapes.
Preferably, described multiple via hole is along the single arrangement of length direction of described first grid lead-in wire.The width that has further reduced first grid lead-in wire, has improved the aperture opening ratio of display unit, and then has improved the display effect of display unit.
Preferably, also comprise the insulating barrier that is arranged at described second grid lead-in wire top, described via hole is through described insulating barrier.Go between by dielectric protection layer second grid.
Preferably, also comprise the organic film being arranged between described insulating barrier and described second grid lead-in wire, on described organic film, be provided with described and cross the through hole that axially bored line is identical, and the diameter of described via hole is not more than the diameter of described through hole.Reduce the load of second grid lead-in wire by organic film, improved the response speed of display unit.
Preferably, the diameter of described via hole is less than the diameter of described through hole.Improve the effect of exposure in via hole, be convenient to follow-up the first transparency conducting layer the effect that rear connection first grid goes between and second grid goes between is set.
The present invention also provides a kind of display unit, and this display unit comprises above-mentioned array base palte described in any.
In technique scheme, by changing the setting position of via hole, the first transparency conducting layer arranging in same via hole can be gone between first grid and the conducting of second grid lead-in wire, thereby reduce the horizontal number of via hole, and then reduce the width of first grid lead-in wire, thereby improve the aperture opening ratio of display unit, and then improved the display effect of display unit.
The present invention also provides a kind of manufacture method of array base palte, and the method comprises the following steps:
On stacked second grid lead-in wire and gate insulator, at least one part of etching is through the via hole of second grid lead-in wire, and this via etch to first grid goes between;
In each via hole, form the first transparency conducting layer that is communicated with first grid lead-in wire and second grid lead-in wire.
The array base palte of producing by aforementioned production method, has reduced the horizontal number of via hole, and then has reduced the width of first grid lead-in wire, thereby has improved the aperture opening ratio of display unit, and then has improved the display effect of display unit.
Preferably, after forming described via hole and before forming the first transparency conducting layer, also comprise:
On second grid lead-in wire, form organic film, and form the through hole being communicated with described via hole on described organic film.
The array base palte of making by said method, has reduced the load of second grid lead-in wire by organic film, improved the response speed of display unit.
Preferably, on organic film, form through hole after and in described via hole, form the first transparency conducting layer before also comprise:
On described organic film, form the second transparency conducting layer;
Exposure falls to be positioned at the second transparency conducting layer of through hole and via hole;
On organic film, form insulating barrier;
Etch away the insulating barrier that is positioned at through hole and via hole.
By said method, make array base palte with organic film in the time making, the photoresist in via hole can fully expose, the impact of avoiding residue to cause follow-up work.
Accompanying drawing explanation
Fig. 1 is the vertical view of the via hole of array base palte of the prior art;
Fig. 2 is the cutaway view that the A-A ' in Fig. 1 locates;
The vertical view of the via hole of the array base palte that Fig. 3 provides for the embodiment of the present invention;
Fig. 4 is the cutaway view that the B-B ' in Fig. 3 locates;
The vertical view of the via hole of the array base palte that Fig. 5 provides for the embodiment of the present invention;
Fig. 6 is the cutaway view that the C-C ' in Fig. 6 locates;
The vertical view of the shoulder hole on the array base palte that Fig. 7 provides for the embodiment of the present invention;
Fig. 8 is the cutaway view that the D-D ' in Fig. 7 locates;
The making flow chart of the array base palte that Fig. 9 a~Fig. 9 i provides for the embodiment of the present invention.
Reference numeral:
1-first grid lead-in wire 2-first grid pilot protection layer 3-second grid lead-in wire
4-insulating barrier 5-transparency conducting layer 6-1-first grid lead-in wire via hole
6-2-second grid lead-in wire via hole 10-first grid lead-in wire 20-gate insulator
30-second grid lead-in wire 40-insulating barrier 51-the second transparency conducting layer
52-the first transparency conducting layer 60-via hole 70-organic film
Embodiment
In order to improve the aperture opening ratio of display unit, and then the display effect of raising display unit, the embodiment of the present invention provides one to lead array base palte, manufacture method and display unit.In technical scheme of the present invention, by be communicated with first grid lead-in wire and second grid lead-in wire in a via hole, thereby reduce the width of first grid lead-in wire, and then improved the aperture opening ratio of display unit, improve the display effect of display unit.For making the object, technical solutions and advantages of the present invention clearer, below as an example of nonrestrictive embodiment example, the present invention is described in further detail.
As shown in Fig. 3, Fig. 4, Fig. 5 and Fig. 6, Fig. 3 and Fig. 5 show respectively the vertical view of the via hole 60 different setting positions of the array base palte that the present embodiment provides; Fig. 4 shows the cutaway view that in Fig. 3, B-B ' locates; Fig. 6 shows the cutaway view that in Fig. 5, C-C ' locates.
The embodiment of the present invention provides a kind of array base palte, this array base palte comprises: first grid lead-in wire 10, second grid lead-in wire 30 and the first grid between described first grid lead-in wire 10 and second grid lead-in wire 30 that is arranged on array base palte neighboring area 10 insulating barriers 40 that go between, also comprise multiple via holes 60 that are etched on described first grid lead-in wire 10, wherein, each via hole 60 is at least partly through described second grid lead-in wire 30, and in each via hole 60, is provided with the first transparency conducting layer 52 of first grid lead-in wire 10 and second grid lead-in wire 30 described in conducting.
In the above-described embodiments, etch via hole 60 by stacked position between second grid lead-in wire 30 and first grid lead-in wire 10, and via hole 60 has part at least through second grid lead-in wire 30, and be etched to first grid lead-in wire 10, thereby guarantee in the time of interior formation the first transparency conducting layer 52 of same via hole 60, the first transparency conducting layer 52 can go between first grid 10 and second grid 30 conductive communication that go between, go between to form in 30 via holes 60 the go between structure of 30 conductings of first grid lead-in wire 10 and second grid is compared at go between 10 via holes 60 and second grid of different first grids from first transparency conducting layer 52 that passes through of available technology adopting, via hole 60 structures that the present embodiment provides adopt single via hole 60 can realize second grid lead-in wire 30 to be connected with the conducting of first grid lead-in wire 10, thereby can reduce the width of first grid lead-in wire 10, and then can improve the aperture opening ratio of display unit, increase the display effect of display unit.
The setting position of its via hole 60 can be selected different positions, concrete, as shown in Figure 3, Fig. 3 shows in the time overlooking, structure when via hole 60 parts are positioned on first grid lead-in wire 10, as shown in Figure 5, Fig. 5 shows, the whole structure being positioned on first grid lead-in wire 10 of via hole 60, the via hole 60 that above-mentioned two diverse locations arrange, all can realize while forming the first transparency conducting layer 52, in the interior conductive communication that realizes first grid lead-in wire 10 and second grid lead-in wire 30 of same via hole 60.The shape that via hole 60 wherein forms can be determined according to actual situation, as: circular port, polygonal hole, slotted eye or irregularly-shaped hole.Its concrete shape can be determined according to need of production.
In order further to improve the aperture opening ratio of display unit, increase the display effect of display unit, preferably, multiple via holes 60 are along the single arrangement of length direction of described first grid lead-in wire 10.Thereby reduce to greatest extent the horizontal area that via hole 60 takies, thereby increased the aperture opening ratio of display unit, and then improved the display effect of whole display unit.
In addition; in order to protect second grid lead-in wire 30; the array base palte of the present embodiment also comprises and is arranged at the go between insulating barrier 40 of 30 tops of described second grid; now; in the time that via hole 60 is set, via hole 60 is through insulating barrier 40, concrete; forming after insulating barrier 40, etch away the insulating barrier 40 that is positioned at via hole 60.
The array array base palte that the present embodiment provides is in the time being provided with two-layer transparency conducting layer, two-layer transparency conducting layer is respectively the first transparency conducting layer 52 and the second transparency conducting layer 51, wherein, the second transparency conducting layer 51 is pixel electrode, should etch away at non-pixel region, the first transparency conducting layer 52 is for being communicated with the conductive layer of first grid lead-in wire 10 and second grid lead-in wire 30, in addition, this array base palte also comprises the organic film 70 being arranged between described insulating barrier 40 and described second grid lead-in wire 30, on organic film 70, be provided with the through hole identical with via hole 60 axis, and the diameter of via hole 60 is not more than the diameter of through hole.Reduce by organic film 70 coupling capacitance that second grid lead-in wire 30 and second grid go between between the public electrode of 30 tops, reduced the load of second grid lead-in wire 30, improved the response speed of display unit.But due to generally thicker (about 2um left and right) of organic film 70, its thickness is about 4~8 times of insulating barrier 40.Easily assemble thicker photoresist thereby cause in via hole 60, concrete, because via hole 60 degree of depth are larger, in the time of exposure, the shade that the sidewall of through hole and via hole 60 forms can shelter from a part of photoresist, causes photoresist residual, affects normally carrying out of subsequent technique.For fear of other retes in organic film 70 via holes 60 because of photoresist is residual cannot etching.Preferably, the diameter of this via hole 60 is less than the diameter of through hole, thereby forms a shoulder hole, wherein, the diameter of through hole is determined according to the degree of depth of the size of via hole 60, the degree of depth and through hole self, guarantees that the sidewall of through hole can not have influence on the photoresist in via hole 60 in the time of exposure.
Concrete, its structure can be with reference to figure 7 and Fig. 8; Fig. 7 shows the vertical view of the via hole 60 of the array base palte with organic film 70, and Fig. 8 shows the cutaway view that in Fig. 7, D-D ' locates.Adopt the structure of shoulder hole, in the time of etching the second transparency conducting layer 51, the shade of having avoided the sidewall of through hole and via hole 60 to form in exposure technology shelters from photoresist, thereby improve the exposure effect of photoresist, when having improved the first transparency conducting layer 52 and having formed, the effect of conducting first grid lead-in wire 10 and second grid lead-in wire 30.
In concrete production process, the particular location of the cascaded surface of shoulder hole directly has influence on the exposure effect of photoresist, its cascaded surface position can be positioned on organic film 70, be that through hole is shoulder hole, part organic film 70 is etched, or be positioned at the upper surface of second grid lead-in wire 30, or be positioned at the upper surface (via hole is shoulder hole) of gate insulator 20, or other position, its particular location is determined according to the size of shoulder hole and processing complexity, preferably, through hole is the clear opening that diameter is constant.The etching of being convenient to shoulder hole forms, and meanwhile, has also increased the contact area of the first transparency conducting layer 52 with the second grid lead-in wire 30 of follow-up formation, and then has increased the conductive communication effect of first grid lead-in wire 10 and second grid lead-in wire 30.
The embodiment of the present invention also provides a kind of display unit, and this display unit comprises above-mentioned array base palte described in any.
In the above-described embodiments, adopt above-mentioned any array base palte, make display unit can possess larger aperture opening ratio, increased the display effect of display unit.
The embodiment of the present invention also provides the manufacture method of array base palte, and the method comprises the following steps:
On stacked second grid lead-in wire 30 and first grid go between 10 insulating barriers 40, at least one part of etching is through the via hole 60 of second grid lead-in wire 30, and this via hole 60 is etched to first grid lead-in wire 10;
Be communicated with the first transparency conducting layer 52 of first grid lead-in wire 10 and second grid lead-in wire 30 in the interior formation of each via hole 60.
The array base palte that can form by said method has reduced the width of first grid lead-in wire 10, and then has improved the aperture opening ratio of display unit, has improved the display effect of display unit.
With specific embodiment, said method is described below.
Embodiment 1
Step 1, on substrate, form first grid lead-in wire 10; Concrete, by mask plate, by the go between photoresist exposure imaging in the region beyond 10 metals of first grid, metal etch first grid being gone between beyond 10 metals by wet etching falls, and leaves first grid 10 metals that go between;
Step 2, on first grid lead-in wire 10, form first grid 10 insulating barriers 40 that go between; Form by plasma enhanced chemical vapor deposition method Direct precipitation;
Step 3, by mask plate by the go between photoresist exposure imaging in the region beyond 30 metals of second grid, metal etch second grid being gone between beyond 30 metals by wet etching falls, and leaves second grid 30 metals that go between;
Step 4, form insulating barrier 40 by plasma enhanced chemical vapor deposition method deposition on first grid lead-in wire 10;
Step 5, by mask plate by the photoresist exposure imaging of via hole 60 positions, carve the insulating barrier 40 of via hole 60 positions and gate insulator 20 etchings by dry, now, go between 10 metals and second grid of first grid goes between 30 exposed metal/bare metals in same via hole 60;
Step 6, by ion sputtering, by the first transparency conducting layer 52 substrates on whole array base palte, then utilize mask plate by the photoresist exposure imaging beyond via hole 60, by wet etching, the first transparency conducting layer 52 of developing regional is etched away, leave the first transparency conducting layer 52 in via hole 60.
The array base palte that can form by said method has reduced the width of first grid lead-in wire 10, and then has improved the aperture opening ratio of display unit, has improved the display effect of display unit.
Embodiment 2
This array base palte is the array base palte with two-layer transparency conducting layer, and its manufacture method is:
Step 1, as shown in Fig. 9 a, on substrate, form first grid lead-in wire 10; Concrete, by mask plate, by the go between photoresist exposure imaging in the region beyond 10 metals of first grid, metal etch first grid being gone between beyond 10 metals by wet etching falls, and leaves first grid 10 metals that go between;
Step 2, as shown in Fig. 9 b, on first grid lead-in wire 10, form gate insulator 20; Form by plasma enhanced chemical vapor deposition method Direct precipitation;
Step 3, as shown in Fig. 9 c, by mask plate, by the go between photoresist exposure imaging in the region beyond 30 metals of second grid, metal etch second grid being gone between beyond 30 metals by wet etching falls, and leaves second grid 30 metals that go between;
Step 4, continuation are with reference to figure 9c, by mask plate by the photoresist exposure imaging of via hole 60 positions, carve the insulating barrier 40 of via hole 60 positions and gate insulator 20 etchings by dry, now, go between 10 metals and second grid of first grid goes between 30 exposed metal/bare metals in same via hole 60;
Step 5, as shown in Fig. 9 d, adopt Coating technique that organic film 70 is coated on substrate, first carry out soft baking processing successively, afterwards to its exposure imaging, form the through hole on organic film 70, the part not being developed stays and forms organic film 70 patterns, finally organic film 70 patterns that formed is cured to processing;
Step 6, as shown in Fig. 9 e, form the second transparency conducting layer 51, the second transparency conducting layer 51 is generally pixel electrode in pixel region, and the second transparency conducting layer 51 in non-pixel region must etch away, for forming conducting first grid lead-in wire 10 below and second grid lead-in wire 30 is prepared.
Step 6, as shown in Fig. 9 f, this figure is the situations after the second transparency conducting layer 51 etchings, can find that the second transparency conducting layer 51 in stair-stepping via hole 60 has been etched completely.
Step 7, as shown in Fig. 9 g, using plasma strengthen chemical vapour deposition technique technology directly on glass substrate deposition form insulating barrier 40;
Step 8, as shown in Fig. 9 h; for the formation of via hole 60; adopt mask plate by the locational photoresist developing exposure of organic film 70 via hole 60; then the dry insulating barrier 40 removed in via hole 60 and first grid 10 protective layers that go between of carving, allow go between 30 metals and first grid of second grid go between 10 exposed metal/bare metals out.
Step 9, as shown in Fig. 9 i, form the first transparency conducting layer 52, the first transparency conducting layers 52 be generally public electrode in pixel region.In non-pixel region, the function of the first transparency conducting layer 52 is herein conducting first grid 10 metals and second grid 30 metals that go between that go between, and the first transparency conducting layer 52 is at the interior connection first grid of same via hole 60 10 metals and second grid 30 metals that go between that go between.
The array base palte that can form by said method has reduced the width of first grid lead-in wire 10, improve the aperture opening ratio of display unit, improve the display effect of display unit, simultaneously, owing to adopting shoulder hole structure, avoided in the time forming the first transparency conducting layer 52, photoresist is above residual, has improved the effect of the first transparency conducting layer 52 conducting first grid lead-in wires 10 and second grid lead-in wire 30.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention the present invention.Like this, if within of the present invention these are revised and modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification interior.

Claims (10)

1. an array base palte, it is characterized in that, comprise: the first grid lead-in wire, second grid lead-in wire and the gate insulator between described first grid lead-in wire and second grid lead-in wire that are arranged on array base palte neighboring area, also comprise multiple via holes that are etched on described first grid lead-in wire, wherein, each via hole is at least partly through described second grid lead-in wire, and in each via hole, is provided with the first transparency conducting layer that first grid lead-in wire and second grid go between described in conducting.
2. array base palte as claimed in claim 1, is characterized in that, described via hole is circular port, polygonal hole or irregularly-shaped hole.
3. array base palte as claimed in claim 2, is characterized in that, described multiple via holes are along the single arrangement of length direction of described first grid lead-in wire.
4. the array base palte as described in claim 1~3 any one, is characterized in that, also comprises the insulating barrier that is arranged at described second grid lead-in wire top, and described via hole is through described insulating barrier.
5. array base palte as claimed in claim 4, it is characterized in that, also comprise the organic film being arranged between described insulating barrier and described second grid lead-in wire, on described organic film, be provided with described and cross the through hole that axially bored line is identical, and the diameter of described via hole is not more than the diameter of described through hole.
6. array base palte as claimed in claim 5, is characterized in that, the diameter of described via hole is less than the diameter of described through hole.
7. a display unit, is characterized in that, comprises the array base palte as described in claim 1~6 any one.
8. a manufacture method for array base palte, is characterized in that, comprises the following steps:
On stacked second grid lead-in wire and gate insulator, at least one part of etching is through the via hole of second grid lead-in wire, and this via etch to first grid goes between;
In each via hole, form the first transparency conducting layer that is communicated with first grid lead-in wire and second grid lead-in wire.
9. manufacture method as claimed in claim 8, is characterized in that, after forming described via hole and before forming the first transparency conducting layer, also comprises:
On second grid lead-in wire, form organic film, and form the through hole being communicated with described via hole on described organic film.
10. manufacture method as claimed in claim 9, is characterized in that, also comprises before forming the first transparency conducting layer on organic film after forming through hole and in described via hole:
On described organic film, form the second transparency conducting layer;
Exposure falls to be positioned at the second transparency conducting layer of through hole and via hole;
On organic film, form insulating barrier;
Etch away the insulating barrier that is positioned at through hole and via hole.
CN201410120715.0A 2014-03-27 2014-03-27 A kind of array base palte, preparation method and display device Active CN103915450B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201410120715.0A CN103915450B (en) 2014-03-27 2014-03-27 A kind of array base palte, preparation method and display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201410120715.0A CN103915450B (en) 2014-03-27 2014-03-27 A kind of array base palte, preparation method and display device

Publications (2)

Publication Number Publication Date
CN103915450A true CN103915450A (en) 2014-07-09
CN103915450B CN103915450B (en) 2017-10-24

Family

ID=51041015

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410120715.0A Active CN103915450B (en) 2014-03-27 2014-03-27 A kind of array base palte, preparation method and display device

Country Status (1)

Country Link
CN (1) CN103915450B (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105845692A (en) * 2016-03-25 2016-08-10 京东方科技集团股份有限公司 Display substrate, display apparatus and manufacture method of display substrate
WO2017140056A1 (en) * 2016-02-17 2017-08-24 京东方科技集团股份有限公司 Layer stack structure, array substrate and display device
WO2019056435A1 (en) * 2017-09-19 2019-03-28 武汉华星光电技术有限公司 Touch screen switch, touch screen and manufacturing method for touch screen switch
CN110634390A (en) * 2019-09-20 2019-12-31 武汉天马微电子有限公司 Display panel and display device
CN112015016A (en) * 2020-09-07 2020-12-01 厦门天马微电子有限公司 Array substrate, manufacturing method of array substrate and display panel

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040074770A (en) * 2003-02-18 2004-08-26 삼성전자주식회사 Method Of Forming Mo Thin Film Pattern And Method Of Manufacturing Thin Film Transistor Of Liquid Crystal Display Device Using The Same
CN101644866A (en) * 2009-09-03 2010-02-10 上海广电光电子有限公司 Film transistor array substrate
CN102023427A (en) * 2009-09-11 2011-04-20 北京京东方光电科技有限公司 TFT-LCD array substrate, and manufacturing and driving methods thereof
CN102033372A (en) * 2009-09-24 2011-04-27 北京京东方光电科技有限公司 TFT-LCD array substrate and manufacturing, detecting and driving methods thereof
US20120019759A1 (en) * 2010-07-21 2012-01-26 Kazuyuki Sunohara Liquid crystal display device
TW201303430A (en) * 2011-07-12 2013-01-16 Chimei Innolux Corp System for display images and fabrication method thereof
CN103117283A (en) * 2013-01-25 2013-05-22 京东方科技集团股份有限公司 Array substrate and manufacturing method thereof and display device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040074770A (en) * 2003-02-18 2004-08-26 삼성전자주식회사 Method Of Forming Mo Thin Film Pattern And Method Of Manufacturing Thin Film Transistor Of Liquid Crystal Display Device Using The Same
CN101644866A (en) * 2009-09-03 2010-02-10 上海广电光电子有限公司 Film transistor array substrate
CN102023427A (en) * 2009-09-11 2011-04-20 北京京东方光电科技有限公司 TFT-LCD array substrate, and manufacturing and driving methods thereof
CN102033372A (en) * 2009-09-24 2011-04-27 北京京东方光电科技有限公司 TFT-LCD array substrate and manufacturing, detecting and driving methods thereof
US20120019759A1 (en) * 2010-07-21 2012-01-26 Kazuyuki Sunohara Liquid crystal display device
TW201303430A (en) * 2011-07-12 2013-01-16 Chimei Innolux Corp System for display images and fabrication method thereof
CN103117283A (en) * 2013-01-25 2013-05-22 京东方科技集团股份有限公司 Array substrate and manufacturing method thereof and display device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017140056A1 (en) * 2016-02-17 2017-08-24 京东方科技集团股份有限公司 Layer stack structure, array substrate and display device
CN105845692A (en) * 2016-03-25 2016-08-10 京东方科技集团股份有限公司 Display substrate, display apparatus and manufacture method of display substrate
WO2019056435A1 (en) * 2017-09-19 2019-03-28 武汉华星光电技术有限公司 Touch screen switch, touch screen and manufacturing method for touch screen switch
CN110634390A (en) * 2019-09-20 2019-12-31 武汉天马微电子有限公司 Display panel and display device
CN112015016A (en) * 2020-09-07 2020-12-01 厦门天马微电子有限公司 Array substrate, manufacturing method of array substrate and display panel
CN112015016B (en) * 2020-09-07 2022-11-22 厦门天马微电子有限公司 Array substrate, manufacturing method of array substrate and display panel

Also Published As

Publication number Publication date
CN103915450B (en) 2017-10-24

Similar Documents

Publication Publication Date Title
US9552120B2 (en) Touch screen panel and method for fabricating the same
US9519392B2 (en) Touch screen panel fabrication method and touch screen panel
CN103456740B (en) Pixel cell and manufacture method, array base palte and display unit
CN103915450A (en) Array substrate, manufacturing method and display device
US8653378B2 (en) Structure of bridging electrode
WO2020113794A1 (en) Display panel and fabricating method therefor
CN103715138B (en) Array substrate and manufacturing method and display device thereof
CN103123911B (en) Pixel structure and manufacturing method thereof
CN104049430B (en) Array substrate, display device and manufacturing method of array substrate
CN108962955B (en) OLED panel and manufacturing method thereof
CN107844209B (en) Touch control display device
WO2016155168A1 (en) Manufacturing method for touch panel, touch panel and touch display device
CN104377207A (en) Display panel and method for manufacturing display panel
CN105655349B (en) Array substrate and preparation method thereof, display panel, display device
CN101488479B (en) Thin-film transistor array substrate and manufacturing method thereof
CN105590897A (en) Display panel and manufacturing method thereof
CN108649036A (en) A kind of array substrate and preparation method thereof
CN105355664A (en) Oxide thin-film transistor and manufacturing method thereof
CN109411518B (en) Organic light emitting diode display and manufacturing method thereof
CN107910351A (en) The production method of TFT substrate
CN104299942A (en) Via hole manufacturing method, array substrate manufacturing method, array substrate and display device
CN103941448B (en) A kind of thin-film transistor array base-plate and preparation method thereof, liquid crystal display
CN203312295U (en) Signal substrate of naked-eye 3D functional panel and display device
CN107564854B (en) OLED backboard manufacturing method
CN109727912A (en) A kind of embedded touch array substrate and its manufacturing method

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant