CN103915450B - A kind of array base palte, preparation method and display device - Google Patents
A kind of array base palte, preparation method and display device Download PDFInfo
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- CN103915450B CN103915450B CN201410120715.0A CN201410120715A CN103915450B CN 103915450 B CN103915450 B CN 103915450B CN 201410120715 A CN201410120715 A CN 201410120715A CN 103915450 B CN103915450 B CN 103915450B
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Abstract
The present invention relates to the technical field of display device, a kind of array base palte, preparation method and display device are disclosed, the array base palte includes：It is arranged on the first grid lead of array base palte neighboring area, second grid lead and the gate insulator between the first grid lead and second grid lead, also include multiple vias being etched on the first grid lead, wherein, each via is provided with the first transparency conducting layer for turning on the first grid lead and second grid lead at least partially across the second grid lead in the via.Beneficial effects of the present invention are：The via structure that the present embodiment is provided is the conducting connection that second grid lead and first grid lead can be achieved using single via, so as to reduce the width of first grid lead, and then the aperture opening ratio of display device can be improved, increase the display effect of display device.
Description
Technical field
The present invention relates to the technical field of display device, more particularly to a kind of array base palte, preparation method and display
Device.
Background technology
On the array base palte of array base palte, at least 8~10 layers metal or insulating barrier, exactly these metal levels and insulation
Layer ensure that the TFT function normal operations on array base palte, and control array base palte is shown according to set input signal.In order to be able to
Make to need substantial amounts of via on same layer metal, or different layers metallic communication, TFT-LCD array base palte, some vias are played
The effect of upper lower metal layer conducting, the via played the role of plays bridge conducting same layer metal.Therefore in the knot of array base palte
In structure design, the structure design of via is extremely important.The joint efficiency of via is improved, the quantity of via is reduced, can not only rise
To the effect of increase array base palte aperture opening ratio, the space of array substrate peripheral can also be saved, the realization to narrow frame is also functioned to
Certain effect.
First grid lead and second grid lead connected mode such as Fig. 1 and Fig. 2 on array base palte of the prior art
Shown, accompanying drawing 1 shows the via between second grid lead and first grid lead in array base palte of the prior art, its
In 1 represent first grid lead；2 represent first grid lead finish；3 represent second grid lead；4 represent insulating barrier；5 generations
Table transparency conducting layer；6-1 represents first grid lead via；6-2 represents second grid lead via.It can be sent out from accompanying drawing 2
Existing first grid lead 1 and second grid lead 3 are simultaneously not belonging to same layer, there is first grid lead finish 2 between the two, and
Second grid lead 3 has insulating barrier again above.In order that first grid lead 1 and second grid lead 3 are turned on, traditional via
Design is respectively in the top of first grid lead 1 and the top of second grid lead 3 design via, by the metal of first grid lead 1
Expose to come in respective via with the metal of second grid lead 3, finally by transparency conducting layer 5 by first grid lead 1
Via 6-1 and the via 6-2 of second grid lead 3 are connected.Applicants have discovered that, in the prior art using two vias（6-
1,6-2）First grid lead 1 and second grid lead 3 are connected, causes the width of first grid lead 1 larger so that non-pixel
The area in region is larger, and then has influence on the aperture opening ratio of display device, reduces the display effect of display device.
The content of the invention
The invention provides a kind of array substrate manufacturing method and display device, the aperture opening ratio to improve display device,
And then improve the display effect of display device.
The invention provides a kind of array base palte, the array base palte includes：It is arranged on the first of array base palte neighboring area
Grid lead, second grid lead and the gate insulator between the first grid lead and second grid lead,
Also include multiple vias being etched on the first grid lead, wherein, each via is at least partially across the second gate
The first transparency conducting layer for turning on the first grid lead and second grid lead is provided with pole lead, and each via.
In the above-mentioned technical solutions, by changing the set location of via so that first set in same via
Transparency conducting layer can turn on first grid lead and second grid lead, so that the horizontal number of via is reduced, and then
The width of first grid lead is reduced, so as to improve the aperture opening ratio of display device, and then the display of display device is improved
Effect.
It is preferred that, the via is circular port, polygonal hole or irregularly-shaped hole.The via can select different shapes.
It is preferred that, length direction single-row arrangement of the multiple via along the first grid lead.It is further to reduce
The width of first grid lead, improves the aperture opening ratio of display device, and then improve the display effect of display device.
It is preferred that, in addition to the insulating barrier above the second grid lead is arranged at, the via passes through the insulation
Layer.Pass through dielectric protection layer second grid lead.
It is preferred that, in addition to the organic film being arranged between the insulating barrier and the second grid lead, it is described organic
It is provided with film and crosses axially bored line identical through hole with described, and the diameter of the via is not more than the diameter of the through hole.Pass through
Organic film reduces the load of second grid lead, improves the response speed of display device.
It is preferred that, the diameter of the via is less than the diameter of the through hole.The effect of exposure in via is improved, after being easy to
The effect of connection first grid lead and second grid lead after continuous first transparency conducting layer is set.
Present invention also offers a kind of display device, the display device includes the array base palte described in any of the above-described kind.
In the above-mentioned technical solutions, by changing the set location of via so that first set in same via
Transparency conducting layer can turn on first grid lead and second grid lead, so that the horizontal number of via is reduced, and then
The width of first grid lead is reduced, so as to improve the aperture opening ratio of display device, and then the display of display device is improved
Effect.
Present invention also offers a kind of preparation method of array base palte, this method comprises the following steps：
At least one, which is etched, on the second grid lead and gate insulator of stacking partially passes through second grid lead
Via, the via etch to first grid lead；
The first transparency conducting layer of connection first grid lead and second grid lead is formed in each via.
The array base palte produced by aforementioned production method, reduces the horizontal number of via, and then reduces first
The width of grid lead, so as to improve the aperture opening ratio of display device, and then improves the display effect of display device.
It is preferred that, after the via is formed and before the first transparency conducting layer of formation, in addition to：
Organic film is formed on second grid lead, and the through hole connected with the via is formed on the organic film.
The array base palte made by the above method, the load of second grid lead is reduced by organic film, is improved
The response speed of display device.
It is preferred that, formed after through hole and also wrapped before forming the first transparency conducting layer in the via over an organic film
Include：
The second transparency conducting layer is formed on the organic film；
The second transparency conducting layer in through hole and in via is fallen in exposure；
Insulating barrier is formed over an organic film；
Etch away the insulating barrier in through hole and via.
Pass through the above method so that the array base palte with organic film is when making, and the photoresist in via can fully expose
Light, it is to avoid the influence that residue is caused to follow-up work.
Brief description of the drawings
Fig. 1 is the top view of the via of array base palte of the prior art；
Fig. 2 be Fig. 1 in A-A ' places sectional view；
Fig. 3 is the top view of the via of array base palte provided in an embodiment of the present invention；
Fig. 4 be Fig. 3 in B-B ' places sectional view；
Fig. 5 is the top view of the via of array base palte provided in an embodiment of the present invention；
Fig. 6 be Fig. 6 in C-C ' places sectional view；
Fig. 7 is the top view of the shoulder hole on array base palte provided in an embodiment of the present invention；
Fig. 8 be Fig. 7 in D-D ' places sectional view；
Fig. 9 a~Fig. 9 i are the Making programme figure of array base palte provided in an embodiment of the present invention.
Reference：
1- first grid lead 2- first grid lead finish 3- second grid leads
4- insulating barrier 5- transparency conducting layer 6-1- first grid lead vias
6-2- second grid lead via 10- first grid lead 20- gate insulators
30- second grid lead 40- insulating barriers the second transparency conducting layers of 51-
52- the first transparency conducting layer 60- via 70- organic films
Embodiment
In order to improve the aperture opening ratio of display device, and then the display effect of display device is improved, the embodiment of the present invention is provided
One kind leads array base palte, preparation method and display device.In the inventive solutions, by being connected in a via
First grid lead and second grid lead, so as to reduce the width of first grid lead, and then improve display device
Aperture opening ratio, improves the display effect of display device.To make the object, technical solutions and advantages of the present invention clearer, below
The present invention is described in further detail by taking non-limiting embodiment as an example.
As shown in Fig. 3, Fig. 4, Fig. 5 and Fig. 6, Fig. 3 and Fig. 5 respectively illustrate the via of the array base palte of the present embodiment offer
The top view of 60 different set locations；Fig. 4 shows the sectional view at B-B ' places in Fig. 3；Fig. 6 shows cuing open for C-C ' places in Fig. 5
View.
The embodiments of the invention provide a kind of array base palte, the array base palte includes：It is arranged on array base palte neighboring area
First grid lead 10, second grid lead 30 and between the first grid lead 10 and second grid lead 30
The insulating barrier 40 of first grid lead 10, in addition to multiple vias 60 being etched on the first grid lead 10, wherein, often
Individual via 60 is provided with the conducting first grid at least partially across the second grid lead 30, and in each via 60 and drawn
First transparency conducting layer 52 of line 10 and second grid lead 30.
In the above-described embodiments, etched by the position being laminated between second grid lead 30 and first grid lead 10
Go out via 60, and via 60 at least partially passes through second grid lead 30, and first grid lead 10 is etched to, so as to ensure
When forming the first transparency conducting layer 52 in same via 60, the first transparency conducting layer 52 can be by first grid lead 10
With the conductive communication of second grid lead 30, from using in the prior art by the first transparency conducting layer 52 in the different first grids
Formed in the via 60 of pole lead 10 and the via 60 of second grid lead 30 and lead first grid lead 10 and second grid lead 30
Logical structure is compared, and second grid lead 30 and the can be achieved using single via 60 for the structure of via 60 that the present embodiment is provided
The conducting connection of one grid lead 10, so as to reduce the width of first grid lead 10, and then can improve display device
Aperture opening ratio, increase display device display effect.
The set location of its via 60 can select different positions, specifically, as shown in figure 3, Fig. 3 is shown in vertical view
When, the part of via 60 is located at structure when on first grid lead 10, as shown in figure 5, Fig. 5 is shown, via 60 is entirely located at
Structure on first grid lead 10, the via 60 that above-mentioned two diverse location is set can realize that to form first transparent leads
During electric layer 52, the conductive communication of first grid lead 10 and second grid lead 30 is realized in same via 60.It is therein
Depending on the shape of the formation of via 60 can be according to actual situation, such as：Circular port, polygonal hole, slotted eye or abnormity
Hole.Depending on its specific shape can need according to production.
In order to further improve the aperture opening ratio of display device, increase the display effect of display device, preferably, multiple mistakes
Length direction single-row arrangement of the hole 60 along the first grid lead 10.So as to reduce the transverse direction that via 60 takes to greatest extent
Area, so as to increase the aperture opening ratio of display device, and then improves the display effect of whole display device.
In addition, in order to protect second grid lead 30, the array base palte of the present embodiment also includes being arranged at the second gate
The insulating barrier 40 of the top of pole lead 30, now, when setting via 60, via 60 passes through insulating barrier 40, specifically, exhausted being formed
After edge layer 40, the insulating barrier 40 in via 60 is etched away.
The array array base palte that the present embodiment is provided is when being provided with two layers of transparency conducting layer, two layers of transparency conducting layer difference
For the first transparency conducting layer 52 and the second transparency conducting layer 51, wherein, the second transparency conducting layer 51 is pixel electrode, in non-pixel
Region should be etched away, and the first transparency conducting layer 52 is the conductive layer of connection first grid lead 10 and second grid lead 30,
In addition, the array base palte also includes the organic film 70 being arranged between the insulating barrier 40 and the second grid lead 30, have
Be provided with machine film 70 with the axis identical through hole of via 60, and the diameter of via 60 is not more than the diameter of through hole.By organic
Film 70 reduces the coupled capacitor between the public electrode of second grid lead 30 and the top of second grid lead 30, reduces the
The load of two grid leads 30, improves the response speed of display device.But it is due to that organic film 70 is typically thicker（About 2um
Left and right）, its thickness is about 4~8 times of insulating barrier 40.So as to cause easily to assemble thicker photoresist in via 60, specifically,
Because the depth of via 60 is larger, in exposure, the shade of the side wall formation of through hole and via 60 can shelter from a part of photoresist,
Cause photoetching glue residua, influence being normally carried out for subsequent technique.In order to avoid other film layers in the via 60 of organic film 70 are because of light
Photoresist is remained and can not etched.Preferably, the diameter of the via 60 is less than the diameter of through hole, so that a shoulder hole is formed, its
In, depending on the depth of the diameter of through hole according to the size, depth and through hole itself of via 60, it is ensured that the side wall of through hole will not be
The photoresist being had influence on during exposure in via 60.
Specifically, its structure may be referred to Fig. 7 and Fig. 8；Fig. 7 shows the via 60 of the array base palte with organic film 70
Top view, Fig. 8 shows the sectional view at D-D ' places in Fig. 7.Using the structure of shoulder hole, the second transparency conducting layer 51 is being etched
When, it is to avoid the shadow occlusion that the side wall of through hole and via 60 is formed in exposure technology firmly photoresist, so as to improve photoetching
The exposure effect of glue, when improving the formation of the first transparency conducting layer 52, conducting first grid lead 10 and second grid lead 30
Effect.
In specific production process, the particular location of the cascaded surface of shoulder hole directly influences the exposure effect of photoresist
Really, its cascaded surface position can be located on organic film 70, i.e., through hole is shoulder hole, and part organic film 70 is etched, or is located at
The upper surface of second grid lead 30, or positioned at the upper surface of gate insulator 20（Via is shoulder hole）, or it is other
Position, depending on its particular location is according to the size of shoulder hole and processing complexity, preferably, through hole is constant straight of diameter
Through hole.It is easy to the etching of shoulder hole to be formed, meanwhile, also increase the first transparency conducting layer 52 being subsequently formed and draw with second grid
The contact area of line 30, and then increase the conductive communication effect of first grid lead 10 and second grid lead 30.
The embodiment of the present invention additionally provides a kind of display device, and the display device includes the array base described in any of the above-described kind
Plate.
In the above-described embodiments, using any of the above-described kind of array base palte so that display device can possess larger opening
Rate, increases the display effect of display device.
The preparation method that the embodiment of the present invention additionally provides array base palte, this method comprises the following steps：
At least one is etched on the second grid lead 30 and the insulating barrier 40 of first grid lead 10 of stacking to partially pass through
The via 60 of second grid lead 30, the via 60 is etched to first grid lead 10；
The first transparency conducting layer of connection first grid lead 10 and second grid lead 30 is formed in each via 60
52。
The array base palte that can be formed by the above method reduces the width of first grid lead 10, and then improves aobvious
The aperture opening ratio of showing device, improves the display effect of display device.
The above method is illustrated with specific embodiment below.
Embodiment 1
Step 1: forming first grid lead 10 on substrate；Specifically, by mask plate by the gold medal of first grid lead 10
The photoresist exposure imaging in the region beyond category, the metal etch beyond the metal of first grid lead 10 is fallen, stay by wet etching
The lower metal of first grid lead 10；
Step 2: forming the insulating barrier 40 of first grid lead 10 on first grid lead 10；Pass through plasma enhancing
Chemical vapour deposition technique Direct precipitation is formed；
Step 3: the photoresist exposure imaging in the region beyond the metal of second grid lead 30 is passed through by mask plate
Wet etching falls the metal etch beyond the metal of second grid lead 30, leaves the metal of second grid lead 30；
Insulating barrier is formed Step 4: being deposited by plasma enhanced chemical vapor deposition method on first grid lead 10
40；
Step 5: by mask plate by the photoresist exposure imaging of the position of via 60, by dry etching by the position of via 60
Insulating barrier 40 and gate insulator 20 are etched, now, and the metal of first grid lead 10 and the exposed metal/bare metal of second grid lead 30 exist
In same via 60；
Step 6: by ion sputtering, by the substrate of the first transparency conducting layer 52 on whole array base palte, then using covering
Template etches away the first transparency conducting layer 52 of developing regional the photoresist exposure imaging beyond via 60 by wet etching,
Leave the first transparency conducting layer 52 in via 60.
The array base palte that can be formed by the above method reduces the width of first grid lead 10, and then improves aobvious
The aperture opening ratio of showing device, improves the display effect of display device.
Embodiment 2
The array base palte is the array base palte with two layers of transparency conducting layer, and its preparation method is：
Step 1: as illustrated in fig. 9, forming first grid lead 10 on substrate；Specifically, by mask plate by first
The photoresist exposure imaging in the region beyond the metal of grid lead 10, by wet etching by the gold beyond the metal of first grid lead 10
Category is etched away, and leaves the metal of first grid lead 10；
Step 2: as shown in figure 9b, forming gate insulator 20 on first grid lead 10；Pass through plasma enhancing
Chemical vapour deposition technique Direct precipitation is formed；
Step 3: as is shown in fig. 9 c, the photoresist in the region beyond the metal of second grid lead 30 is exposed by mask plate
Photodevelopment, is fallen the metal etch beyond the metal of second grid lead 30 by wet etching, leaves the metal of second grid lead 30；
Step 4: with continued reference to Fig. 9 c, will by dry etching by mask plate by the photoresist exposure imaging of the position of via 60
The insulating barrier 40 and gate insulator 20 of the position of via 60 etch, now, the metal of first grid lead 10 and second grid lead
30 exposed metal/bare metals are in same via 60；
Step 5: as shown in figure 9d, organic film 70 is coated on substrate using Coating techniques, first carry out soft successively
Property baking processing, afterwards to its exposure imaging, formed organic film 70 on through hole, not developed part leaves to form organic film
70 patterns, finally carry out curing process to the pattern of organic film 70 formed；
Step 6: as shown in figure 9e, forming the second transparency conducting layer 51, the second transparency conducting layer 51 is generally in pixel region
Pixel electrode, the second transparency conducting layer 51 in non-pixel areas must be etched away, and be to form conducting first grid lead below
10 and second grid lead 30 prepare.
Step 6: as shown in figure 9f, the figure is the situation after the second transparency conducting layer 51 etching, it can be found that stepped
Via 60 in the second transparency conducting layer 51 be etched completely.
Step 7: as shown in figure 9g, using plasma enhancing chemical vapour deposition technique technology is directly on the glass substrate
Deposition forms insulating barrier 40；
Step 8: be the formation of via 60 as shown in Fig. 9 h, using mask plate by the light on the position of 70 via of organic film 60
Photoresist development exposure, then dry etching remove the insulating barrier 40 and the protective layer of first grid lead 10 in via 60, allow second grid
The metal of lead 30 and the exposed metal/bare metal of first grid lead 10 come out.
Step 9: as illustrated in fig. 9i, forming the first transparency conducting layer 52, the first transparency conducting layer 52 is generally in pixel region
Public electrode.In non-pixel areas, the function of the first transparency conducting layer 52 herein is the metal of conducting first grid lead 10 and the
The metal of two grid lead 30, the first transparency conducting layer 52 metal of connection first grid lead 10 and second in same via 60
The metal of grid lead 30.
The array base palte that can be formed by the above method reduces the width of first grid lead 10, improves display dress
The aperture opening ratio put, improves the display effect of display device, simultaneously as using shoulder hole structure, it is to avoid forming first
During transparency conducting layer 52, photoetching glue residua above improves the first transparency conducting layer 52 conducting first grid lead 10 and the
The effect of two grid leads 30.
Obviously, those skilled in the art can carry out the essence of various changes and modification without departing from the present invention to the present invention
God and scope.So, if these modifications and variations of the present invention belong to the scope of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to comprising including these changes and modification.
Claims (5)
1. a kind of array base palte, it is characterised in that including：Be arranged on array base palte neighboring area first grid lead, second
Grid lead and the gate insulator between the first grid lead and second grid lead, in addition to multiple etchings
Via on to the first grid lead, length direction single-row arrangement of multiple vias along the first grid lead；
Wherein, each via is provided with the conducting first grid at least partially across the second grid lead, and in each via
First transparency conducting layer of lead and second grid lead；
Also include being arranged at the insulating barrier above the second grid lead, the via passes through the insulating barrier；
Also include being arranged on organic film between the insulating barrier and the second grid lead, the organic film be provided with
It is described to cross axially bored line identical through hole, and diameter of the diameter less than the through hole of the via.
2. array base palte as claimed in claim 1, it is characterised in that the via is circular port, polygonal hole or irregularly-shaped hole.
3. a kind of display device, it is characterised in that including array base palte as claimed in claim 1 or 2.
4. a kind of preparation method of array base palte, it is characterised in that comprise the following steps：
The mistake that multiple at least a portion pass through second grid lead is etched on the second grid lead and gate insulator of stacking
Hole, the via etch is to first grid lead, length direction single-row arrangement of multiple vias along the first grid lead；
The first transparency conducting layer of connection first grid lead and second grid lead is formed in each via；
After the via is formed and before the first transparency conducting layer of formation, in addition to：
Organic film is formed on second grid lead, and the through hole connected with the via is formed on the organic film.
5. preparation method as claimed in claim 4, it is characterised in that formed over an organic film after through hole and in the via
Also include before forming the first transparency conducting layer：
The second transparency conducting layer is formed on the organic film；
The second transparency conducting layer in through hole and in via is fallen in exposure；
Insulating barrier is formed over an organic film；
Etch away the insulating barrier in through hole and via.
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| CN205428907U (en) * | 2016-02-17 | 2016-08-03 | 京东方科技集团股份有限公司 | Layer stack structure , array substrate and display device |
| CN105845692A (en) * | 2016-03-25 | 2016-08-10 | 京东方科技集团股份有限公司 | Display substrate, display apparatus and manufacture method of display substrate |
| CN107682001B (en) * | 2017-09-19 | 2020-01-10 | 武汉华星光电技术有限公司 | Touch screen switch, touch screen and manufacturing method of touch screen switch |
| CN110634390A (en) * | 2019-09-20 | 2019-12-31 | 武汉天马微电子有限公司 | Display panel and display device |
| CN112015016B (en) * | 2020-09-07 | 2022-11-22 | 厦门天马微电子有限公司 | Array substrate, manufacturing method of array substrate and display panel |
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| CN102023427A (en) * | 2009-09-11 | 2011-04-20 | 北京京东方光电科技有限公司 | TFT-LCD array substrate, and manufacturing and driving methods thereof |
| CN103117283A (en) * | 2013-01-25 | 2013-05-22 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof and display device |
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| KR100913306B1 (en) * | 2003-02-18 | 2009-08-26 | 삼성전자주식회사 | Method Of Forming Mo Thin Film Pattern And Method Of Manufacturing Thin Film Transistor Of Liquid Crystal Display Device Using The Same |
| CN101644866B (en) * | 2009-09-03 | 2011-05-18 | 上海广电光电子有限公司 | Film transistor array substrate |
| CN102033372B (en) * | 2009-09-24 | 2013-08-28 | 北京京东方光电科技有限公司 | TFT-LCD array substrate and manufacturing, detecting and driving methods thereof |
| JP5078176B2 (en) * | 2010-07-21 | 2012-11-21 | 株式会社ジャパンディスプレイセントラル | Liquid crystal display |
| TWI471643B (en) * | 2011-07-12 | 2015-02-01 | Innolux Corp | System for display images and fabrication method thereof |
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| CN102023427A (en) * | 2009-09-11 | 2011-04-20 | 北京京东方光电科技有限公司 | TFT-LCD array substrate, and manufacturing and driving methods thereof |
| CN103117283A (en) * | 2013-01-25 | 2013-05-22 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof and display device |
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