CN210272337U - Semiconductor structure - Google Patents

Abstract

The utility model relates to a semiconductor manufacturing technical field especially relates to a semiconductor structure. The semiconductor structure includes: a substrate; the first conductive structure is positioned on the surface of the substrate; the wiring layer is embedded between the substrate and the first conductive structure along the direction perpendicular to the substrate, and extends out of the first conductive structure along the direction parallel to the substrate; and the first plug extends along the direction vertical to the substrate, one end of the first plug is electrically connected with the end part of the wiring layer extending out of the first conductive structure, and the other end of the first plug is used for being connected with an external circuit. The utility model provides a cut the problem that the line size reduces and the difficult overall arrangement of wire winding that leads to, avoided the problem that the design principle was easily violated to structural layout, ensured the reliability and the stability of the follow-up test result of semiconductor construction.

Description

Semiconductor structure

Technical Field

The utility model relates to a semiconductor manufacturing technical field especially relates to a semiconductor structure.

Background

With the advance of advanced manufacturing processes and in order to increase the effective utilization of wafers, structures for electrical testing of chips in semiconductor structures are being designed with the aim of reducing the size of scribe lines. The electrical test structure typically includes pads (Pad) arranged in an array and wires located around the pads. The bonding pads are used for probe test and electric connection with external circuits. However, as the size of the scribe line is reduced, the area of the space around the pad for wiring is reduced, which increases the difficulty of routing layout.

To solve this problem, the prior art has adopted a method of reducing the size of the pad to increase the area around the pad where the wiring is available. Although this method can provide sufficient area for the wiring, during the wafer Test, the probe is easily slipped out from the surface of the pad with smaller size, even stuck out of the pad area, resulting in unstable WAT (wafer acceptance Test) result, low reliability, and damage to the probe.

Therefore, how to improve the winding structure in the semiconductor structure, avoid the problem that the winding is difficult to arrange because of the reduction of the cutting path size, and improve the reliability and the stability of the test result of the semiconductor structure.

SUMMERY OF THE UTILITY MODEL

The utility model provides a semiconductor structure for solve the cutting size of saying and reduce the problem that leads to the difficult overall arrangement of wire winding.

In order to solve the above problem, the utility model provides a semiconductor structure, include:

a substrate;

the first conductive structure is positioned on the surface of the substrate;

the wiring layer is embedded between the substrate and the first conductive structure along the direction perpendicular to the substrate, and extends out of the first conductive structure along the direction parallel to the substrate;

and the first plug extends along the direction vertical to the substrate, one end of the first plug is electrically connected with the end part of the wiring layer extending out of the first conductive structure, and the other end of the first plug is used for being connected with an external circuit.

Optionally, the base is a substrate, and the first conductive structure includes a plurality of pads arranged at intervals along a first direction;

the wiring layer comprises a plurality of wirings positioned between the substrate and the bonding pad, the end part of each wiring extends out of the bonding pad along the first direction, at least one first plug is arranged at the end part of each wiring, which extends out of the bonding pad, and the first direction is parallel to the substrate.

Optionally, a plurality of first plugs arranged along the first direction are disposed at an end of each of the wires extending out of the pad.

Optionally, the method further includes:

and the connecting layer is positioned above the wiring layer along the direction perpendicular to the substrate and is arranged on the same layer with the plurality of bonding pads, one end of the connecting layer is electrically connected with one first plug of at least one wiring end part positioned below one bonding pad, and the other end of the connecting layer is electrically connected with at least one other bonding pad.

Optionally, one end of the connection layer is electrically connected to the first plugs at the end portions of the plurality of wires located below one pad, and the other end of the connection layer is electrically connected to another plurality of pads.

Optionally, the substrate surface further has a test structure for transmitting a test electrical signal to the wiring layer; the connection layer includes:

a first connection line having one end for electrically connecting the first plug at one end of the wiring under one of the pads and the other end for electrically connecting the other of the pads;

and a second connection line having one end for electrically connecting the test structure and the other end for electrically connecting the first plug of the other end of the wiring located under one of the pads.

Optionally, in a second direction, a projection of the pad in a direction perpendicular to the substrate covers a plurality of wires located thereunder, and the second direction is parallel to the substrate and perpendicular to the first direction.

Optionally, the base includes a substrate and a second conductive structure located on a surface of the substrate, and the first conductive structure is located above the second conductive structure;

the wiring layer comprises a plurality of wirings positioned between the first conductive structure and the second conductive structure, the end part of each wiring extends out of the first conductive structure, and at least one first plug is arranged at the end part of each wiring, which extends out of the first conductive structure.

Optionally, the method further includes:

a plurality of second plugs, one end of each second plug is electrically connected with the second conductive structure, and the other end of each second plug is electrically connected with the first conductive structure;

each of the wirings passes through a gap between two adjacent second plugs.

Optionally, the first conductive structure is made of a metal material, and the wiring layer is made of a polysilicon material or a metal material.

The utility model provides a semiconductor structure, through with the wiring layer set up at the basement with between the first conductive structure to be connected with external circuit through the first plug that is located wiring layer tip, avoided right with the occupation of the peripheral space of first conductive structure coplanar need not to reduce the area of first conductive structure, solved cutting track size reduce and the difficult overall arrangement's of wire winding that leads to problem, avoided the structure overall arrangement easily to violate the problem of design principle, ensured the reliability and the stability of the follow-up test result of semiconductor structure.

Drawings

Fig. 1 is a schematic top view of a semiconductor structure according to an embodiment of the present invention;

fig. 2 is a schematic cross-sectional structure diagram of a first conductive structure and a wiring layer according to an embodiment of the present invention;

FIGS. 3A-3C are schematic perspective views of a semiconductor structure in accordance with embodiments of the present invention;

FIG. 4 is a flow chart of a method of forming a semiconductor structure according to an embodiment of the present invention;

fig. 5A-5M are schematic diagrams of the main process structures of the embodiments of the present invention in the process of forming a semiconductor structure.

Detailed Description

The following describes in detail a semiconductor structure according to an embodiment of the present invention with reference to the accompanying drawings.

This embodiment provides a semiconductor structure, and fig. 1 is the utility model discloses a semiconductor structure's among the embodiment overlook schematic diagram, and fig. 2 is the utility model discloses the cross-sectional structure schematic diagram of first conductive structure and wiring layer among the embodiment, and fig. 3A-3C are the utility model discloses semiconductor structure's among the embodiment three-dimensional schematic diagram. As shown in fig. 1 to 2 and fig. 3A to 3C, the semiconductor structure provided in the present embodiment includes:

a substrate 10;

a first conductive structure 11 located on the surface of the substrate 10;

a wiring layer embedded between the substrate 10 and the first conductive structure 11 in a direction perpendicular to the substrate 10, and extending out of the first conductive structure 11 in a direction parallel to the substrate 10;

and a first plug 13 extending in a direction perpendicular to the substrate 10, wherein one end of the first plug 13 is electrically connected to an end of the wiring layer extending out of the first conductive structure 11, and the other end is used for connecting to an external circuit.

Specifically, the material of the first conductive structure 11 may be a metal material such as tungsten, copper, or aluminum. The first conductive structure 11 is located on the substrate 10 and is used for transmitting an external electrical signal to the substrate 10. The external circuit may be a circuit for transmitting an external electrical signal to the first conductive structure 11, for example a circuit for transmitting a test electrical signal to the first conductive structure 11. The wiring layer partially under the first conductive structure 11 is not visible at the angles shown in fig. 1 and 2 and is therefore indicated by a dashed line.

In the present embodiment, the wiring layer is embedded between the substrate 10 and the first conductive structure 11 along the Z-axis direction, so that a peripheral region coplanar with the first conductive structure 11 (for example, a region located at the periphery of the first conductive structure 11 along the Y-axis direction) is prevented from being occupied, and even when the size of the scribe line is small, a sufficient wiring space can be obtained, thereby simplifying a winding layout process in the semiconductor structure, preventing the structure layout from easily violating the design principle, and ensuring the reliability of the subsequent test result of the semiconductor structure and the stability of the performance of the semiconductor structure. Meanwhile, the first plug for leading out the wiring layer is located at the end of the wiring layer extending out of the first conductive structure 11, so that the arrangement of the first conductive structure 11 is not affected.

Optionally, the base is a substrate, and the first conductive structure 11 includes a plurality of pads arranged at intervals along a first direction;

the wiring layer comprises a plurality of wirings 12 positioned between the substrate 10 and the bonding pads, the end part of each wiring 12 extends out of the bonding pad along the first direction, at least one first plug 13 is arranged at the end part of each wiring 12 extending out of the bonding pad, and the first direction is parallel to the substrate 10.

Optionally, the end of each of the wires 12 extending out of the pad is provided with a plurality of the first plugs 13 arranged along the first direction.

Optionally, the semiconductor structure further includes:

and a connection layer located above the wiring layer along a direction perpendicular to the substrate 10 and disposed on the same layer as the plurality of pads, wherein one end of the connection layer is electrically connected to one first plug 13 located at an end of at least one wiring 12 located below the pad, and the other end of the connection layer is electrically connected to another at least one pad.

Optionally, the substrate surface further has a test structure 15 for transmitting test electrical signals to the wiring layer; the connection layer includes:

a first connection line 141 having one end for electrically connecting the first plug 13 at one end of the wiring 12 under one of the pads and the other end for electrically connecting the other of the pads;

a second connection line 142 having one end electrically connected to the test structure 15 and the other end electrically connected to the first plug 13 of the other end of the wiring 12 located under one of the pads.

Specifically, the base 10 may be a semiconductor substrate formed with an Active Area (AA), and at this time, the wiring layer is located between the semiconductor substrate and the first conductive structure. As shown in fig. 1, 2 and 3A, the first conductive structure 11 includes a plurality of pads, such as a first Pad1, a second Pad2, a third Pad3, … …, a nineteenth Pad19 and a twentieth Pad20, which are located on the surface of the substrate 10 and are arranged in parallel along the X-axis direction. The number of pads included in the first conductive structure 11 may be selected by a person skilled in the art according to the design requirements of the integrated circuit, for example, according to the requirements of electrical performance testing. The substrate 10 surface also has a test structure 15 for transmitting test electrical signals to the wiring layer. The plurality of wiring layers are distributed between the plurality of bonding pads and the substrate 10 one by one, namely, one wiring layer corresponding to each bonding pad is arranged under each bonding pad, a plurality of wirings 12 which are arranged in parallel along the Y-axis direction are arranged in each wiring layer, and each wiring 12 is in a long strip shape which extends along the X-axis direction. Each of the ends of the wires 12 extending out of the pad has at least one of the first plugs 13. For example, the wiring layer between the first Pad1 and the substrate 10 includes three of the wirings 12 arranged in parallel in the Y-axis direction, each of the wirings 12 extending in the X-axis direction. In order to ensure the stability of the electrical connection, each of the wirings 12 has two or more first plugs 13 at the end portion extending out of the pad. The material of the first plug 13 may also be a metal material such as tungsten, copper, aluminum, and the like. The term "plurality" as used in the present embodiment means two or more.

The connection layer is located above the wiring layer and is disposed on the same layer as the pad, and includes a first connection line 141 and a second connection line 142, one end of the first connection line 141 is used to electrically connect the first plug 13 of one end of the wiring located below one of the pads, and the other end of the first connection line is used to electrically connect the other pad, one end of the second connection line 142 is used to electrically connect the test structure 15, and the other end of the second connection line is used to electrically connect the first plug 13 of the other end of the wiring located below one of the pads. For example, as shown in fig. 2, the test structure 15 is electrically connected to one end of the first plug 13 through the second connection line 142, and the other end of the first plug 13 is electrically connected to the left end of one of the wirings 12 at the bottom of the second Pad 2; the right end of the wiring 12 is connected to an end of the other first plug 13, and the other end of the other first plug 13 is electrically connected to the third Pad3 through the first connection line. With this connection, the electrical test signal is transmitted to the third Pad3 through the test structure 15, the second connection line 142, the first plug 13 connected to the left end of the wire 12 under the second Pad2, the wire 12 under the second Pad2, the first plug 13 connected to the right end of the wire 12 under the second Pad2, and the first connection line 141 in this order. Therefore, part of transmission paths of the test electric signals are arranged at the lower part of the bonding pad, the occupation of the space around the bonding pad is reduced, and the space utilization rate in the semiconductor structure is improved.

In this embodiment, the connection layer and the pad are disposed on the same layer, so that the connection layer and the pad can be formed synchronously, thereby further simplifying the semiconductor manufacturing process.

In fig. 2, only the connection layer is shown to be connected to one of the wirings 12 and one of the pads, and a person skilled in the art may make the connection layer be connected to a plurality of the wirings 12 and/or a plurality of the pads at the same time according to the requirement of the test, for example, one end of the connection layer is electrically connected to the first plug at the end of a plurality of the wirings below one pad, and the other end is electrically connected to another plurality of the pads, which is not limited in this embodiment.

In order to further improve the space utilization of the semiconductor structure, optionally, a projection of the pad in a direction perpendicular to the substrate 10 covers a plurality of the wires 12 located therebelow along a second direction, which is parallel to the substrate 10 and perpendicular to the first direction.

Specifically, in the Y-axis direction in fig. 1 and 2, the projection of the pad in the Z-axis direction completely covers the wiring 12 located therebelow. The wiring 12 extends out of the pad in the X-axis direction.

In other specific embodiments, as shown in fig. 3B and 3C, the base includes a substrate and a second conductive structure 30 located on the surface of the substrate, and the first conductive structure 11 is located above the second conductive structure 30;

the wiring layer includes a plurality of wires 12 located between the first conductive structure 11 and the second conductive structure 30, an end of each wire 12 extends out of the first conductive structure 11, and at least one first plug 13 is disposed at an end of each wire 12 extending out of the first conductive structure 11.

Optionally, the semiconductor structure further includes:

a plurality of second plugs 31, one end of each second plug 31 is electrically connected to the second conductive structure 30, and the other end of each second plug 31 is electrically connected to the first conductive structure 11;

each of the wirings 12 passes through a gap between two adjacent second plugs 31.

Fig. 3C is a schematic top view of fig. 3B, and the first conductive structure 11 is not shown in fig. 3C, so as to clearly show the relative position relationship between the second plug 31 and the wiring 12. Specifically, as shown in fig. 3B and 3C, the base may also be a semiconductor substrate whose surface is covered with the second conductive structure 30, and at this time, the wiring layer is embedded between the second conductive structure 30 and the first conductive structure 11. The wiring layer is not in direct contact with the first conductive structure 11 and the second conductive structure 30, that is, the wiring layer is isolated from the first conductive structure 11 located above the wiring layer and the second conductive structure 30 located below the wiring layer by an insulating material. The first conductive structure 11 and the second conductive structure 30 transmit an electrical signal therebetween through the second plug 31. For example, when the first conductive structure 11 includes a plurality of the pads arranged in the X-axis direction, a test signal can be transmitted to another pad through the wiring 12 under one pad. The wires 12 pass through the gap between two adjacent second plugs 31, that is, the wires 12 and the second plugs 31 are independent and electrically isolated from each other, so as to avoid signal crosstalk between the wires 12 and the second plugs 31.

The material of the first conductive structure 11 and the wiring layer can be selected by those skilled in the art according to actual needs, and the present embodiment is not limited thereto. Optionally, the first conductive structure 11 and the second conductive structure 30 are made of a metal material, and the wiring layer is made of a polysilicon material or a metal material. For example, when the substrate is a substrate, the material of the wiring layer may be a polysilicon material; when the base includes a substrate and a second conductive structure on the surface of the substrate, the material of the wiring layer may be a metal material. The material of the second plug 31 may be the same as that of the first plug 13, and for example, both are tungsten.

Furthermore, the present embodiment further provides a method for forming a semiconductor structure, fig. 4 is a flowchart of a method for forming a semiconductor structure according to an embodiment of the present invention, fig. 5A to 5M are schematic diagrams of main process structures of the semiconductor structure according to an embodiment of the present invention in a process of forming the semiconductor structure, and fig. 1, fig. 2, fig. 3A and fig. 3B can be referred to for schematic diagrams of the semiconductor structure formed according to the present embodiment. As shown in fig. 1, fig. 2, fig. 3A, fig. 3B, fig. 4, and fig. 5A to fig. 5M, the method for forming a semiconductor structure according to the present embodiment includes the following steps:

step S41, providing the substrate 10, as shown in fig. 5A.

Specifically, the base 10 may be a semiconductor substrate on which an Active Area (AA) is formed, or may be a semiconductor substrate whose surface is covered with a metal layer. The following description will be given taking the substrate 10 as a semiconductor substrate on which an active region is formed as an example.

In step S42, a wiring layer is formed on the surface of the substrate 10, as shown in fig. 5E.

Optionally, the specific step of forming the wiring layer on the surface of the substrate 10 includes:

forming a first dielectric layer 40 covering the substrate 10, as shown in fig. 5A;

etching the first dielectric layer 40 to form a first opening 401 exposing the substrate 10, as shown in fig. 5C;

a first conductive material is deposited in the first opening 401 to form the wiring layer, as shown in fig. 5E.

Optionally, the specific step of forming the wiring layer includes:

etching the first dielectric layer 40 to form a plurality of first openings 401 arranged along a second direction, wherein the first openings 401 extend along the first direction and expose the substrate, the first direction is parallel to the substrate 10, and the second direction is parallel to the substrate 10 and perpendicular to the first direction;

a first conductive material is filled in the first openings 401 to form a wiring layer including a plurality of wires 12.

Specifically, after forming the first dielectric layer 40 covering the substrate 10, forming a first photoresist layer 41 on the surface of the first dielectric layer 40, where the first photoresist layer 41 has a plurality of first etching windows 411, as shown in fig. 5B; then, etching the first dielectric layer 40 along the first etching window 411, and forming a plurality of first openings 401 in the first dielectric layer 40 to expose the substrate 10, as shown in fig. 5C; then, forming an initial wiring 42 which fills the first opening 401 and covers the top surface of the first dielectric layer 40; finally, a chemical mechanical polishing process is performed to remove a portion of the initial wiring 42, so as to expose the first dielectric layer 40, and the initial wiring 42 remaining in one of the first openings 401 is used as one of the wirings 12, as shown in fig. 5E.

Step S43, forming a first plug 13 at an end portion of the wiring layer, the first plug 13 extending in a direction perpendicular to the substrate 10 for connecting with an external circuit, as shown in fig. 5J.

Optionally, the specific step of forming the first plug 13 at the end of the wiring layer includes:

forming a second dielectric layer 43 covering the first dielectric layer 40 and the wiring layer, as shown in fig. 5F;

etching the second dielectric layer 43 to form a second opening 431 exposing the end portion of the wiring layer, as shown in fig. 5H;

depositing a second conductive material in the second opening 431 to form the first plug 13, as shown in fig. 5J.

Specifically, after forming the second dielectric layer 43, depositing a second photoresist layer 44 on the second dielectric layer 43, where the second photoresist layer 44 has a second etching window 441 exposing the second dielectric layer 43, as shown in fig. 5G; then, the second dielectric layer 43 is etched from the second etching window 441 to form a plurality of second openings 431 exposing the wires 12, as shown in fig. 5H; next, forming an initial first plug 45 filling the second opening 431 and covering the top surface of the second dielectric layer 43, as shown in fig. 5I; finally, a portion of the initial first plug 45 is removed by a chemical mechanical polishing process, and the initial first plug 45 remaining in one of the second openings 431 serves as one of the first plugs 13.

Step S44, forming a first conductive structure 11 on the wiring layer, where the end of the wiring layer formed with the first plug 13 extends out of the first conductive structure 11 along a direction parallel to the substrate 10, as shown in fig. 1, 2 and 5K, where fig. 5K is a side view of the semiconductor structure, and the first plug 13 and the first conductive structure 11 are not substantially in contact.

Optionally, the specific step of forming the first conductive structure 11 on the wiring layer includes:

depositing a third conductive material on the surface of the second dielectric layer 43 to form the first conductive structure 11 exposing the first plug 13.

Optionally, the first conductive structure 11 includes a plurality of pads arranged at intervals along a first direction, and the plurality of wiring layers are distributed below the plurality of pads one by one;

the surface of the substrate 10 further includes a second plug 31 located between two adjacent wires 12 under one of the pads, and one end of the second plug 31 is electrically connected to the substrate 10, and the other end is electrically connected to one of the pads.

Optionally, the specific step of forming the first conductive structure 11 on the wiring layer further includes:

depositing a third conductive material on the surface of the second dielectric layer, forming the first conductive structure 11 exposing the first plug 13, and simultaneously forming a connection layer, where one end of the connection layer is electrically connected to one first plug 13 at the end of one wiring 12 located under one pad, and the other end is electrically connected to the other pad, as shown in fig. 5L and 5M. Fig. 5L and 5M are schematic cross-sectional views of two other angles of fig. 5K, respectively. The pads are formed in synchronization with the first and second connection lines 141 and 142, thereby further simplifying the process of forming the semiconductor structure and reducing the manufacturing cost.

In other specific embodiments, the base includes a substrate and a second conductive structure 30 located on a surface of the substrate; the first conductive structure 11 is located above the second conductive structure 30;

the wiring layer includes a plurality of wires 12 located between the first conductive structure 11 and the second conductive structure 30, an end of each wire 12 extends out of the first conductive structure 11, and at least one first plug 13 is disposed at an end of each wire 12 extending out of the first conductive structure 11.

Optionally, the semiconductor structure includes a plurality of second plugs 31, one end of each second plug 31 is electrically connected to the second conductive structure 30, and the other end of each second plug 31 is electrically connected to the first conductive structure 11;

each of the wirings 12 passes through a gap between two adjacent second plugs 31.

Optionally, the first conductive structure 11 is made of a metal material, and the wiring layer is made of a polysilicon material or a metal material. For example, when the substrate is a substrate, the material of the wiring layer may be a polysilicon material; when the base includes a substrate and a second conductive structure on the surface of the substrate, the material of the wiring layer may be a metal material.

The semiconductor structure provided by the specific embodiment is characterized in that the wiring layer is arranged between the substrate and the first conductive structures and is connected with an external circuit through the first plug positioned at the end part of the wiring layer, so that occupation of the coplanar peripheral space of the first conductive structures is avoided, the area of the first conductive structures is not required to be reduced, the problem that the winding is difficult to arrange due to reduction of the size of a cutting channel is solved, the problem that the structural arrangement easily violates the design principle is avoided, and the reliability and the stability of the subsequent test result of the semiconductor structure are ensured.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of improvements and decorations can be made without departing from the principle of the present invention, and these improvements and decorations should also be regarded as the protection scope of the present invention.

Claims (10)

1. A semiconductor structure, comprising:

a substrate;

the first conductive structure is positioned on the surface of the substrate;

the wiring layer is embedded between the substrate and the first conductive structure along the direction perpendicular to the substrate, and extends out of the first conductive structure along the direction parallel to the substrate;

and the first plug extends along the direction vertical to the substrate, one end of the first plug is electrically connected with the end part of the wiring layer extending out of the first conductive structure, and the other end of the first plug is used for being connected with an external circuit.

2. The semiconductor structure of claim 1, wherein the base is a substrate, and the first conductive structure comprises a plurality of pads spaced apart along a first direction;

the wiring layer comprises a plurality of wirings positioned between the substrate and the bonding pad, the end part of each wiring extends out of the bonding pad along the first direction, at least one first plug is arranged at the end part of each wiring, which extends out of the bonding pad, and the first direction is parallel to the substrate.

3. The semiconductor structure of claim 2, wherein an end portion of each of the wires extending out of the pad is provided with a plurality of the first plugs arranged in the first direction.

4. The semiconductor structure of claim 2, further comprising:

and the connecting layer is positioned above the wiring layer along the direction perpendicular to the substrate and is arranged on the same layer with the plurality of bonding pads, one end of the connecting layer is electrically connected with one first plug of at least one wiring end part positioned below one bonding pad, and the other end of the connecting layer is electrically connected with at least one other bonding pad.

5. The semiconductor structure according to claim 4, wherein one end of the connection layer is electrically connected to the first plugs at the ends of the plurality of wirings under one pad, and the other end is electrically connected to another plurality of pads.

6. The semiconductor structure of claim 4, wherein the substrate surface further has a test structure for transmitting test electrical signals to the wiring layer; the connection layer includes:

a first connection line having one end for electrically connecting the first plug at one end of the wiring under one of the pads and the other end for electrically connecting the other of the pads;

and a second connection line having one end for electrically connecting the test structure and the other end for electrically connecting the first plug of the other end of the wiring located under one of the pads.

7. The semiconductor structure of claim 2, wherein a projection of the pad in a direction perpendicular to the substrate covers a plurality of the wires thereunder in a second direction parallel to the substrate and perpendicular to the first direction.

8. The semiconductor structure of claim 1, wherein the base comprises a substrate and a second conductive structure on a surface of the substrate, the first conductive structure being over the second conductive structure;

the wiring layer comprises a plurality of wirings positioned between the first conductive structure and the second conductive structure, the end part of each wiring extends out of the first conductive structure, and at least one first plug is arranged at the end part of each wiring, which extends out of the first conductive structure.

9. The semiconductor structure of claim 8, further comprising:

a plurality of second plugs, one end of each second plug is electrically connected with the second conductive structure, and the other end of each second plug is electrically connected with the first conductive structure;

each of the wirings passes through a gap between two adjacent second plugs.

10. The semiconductor structure of claim 1, wherein the material of the first conductive structure is a metal material, and the material of the wiring layer is a polysilicon material or a metal material.

Images