JPH0439231B2 - - Google Patents
Info
- Publication number
- JPH0439231B2 JPH0439231B2 JP57007588A JP758882A JPH0439231B2 JP H0439231 B2 JPH0439231 B2 JP H0439231B2 JP 57007588 A JP57007588 A JP 57007588A JP 758882 A JP758882 A JP 758882A JP H0439231 B2 JPH0439231 B2 JP H0439231B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- chip
- thermal expansion
- wiring
- polymer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 239000004065 semiconductor Substances 0.000 claims abstract description 14
- 229920000642 polymer Polymers 0.000 claims abstract description 8
- 229910000679 solder Inorganic materials 0.000 claims abstract description 7
- 239000004642 Polyimide Substances 0.000 claims abstract description 5
- 229920001721 polyimide Polymers 0.000 claims abstract description 5
- 239000000463 material Substances 0.000 claims abstract description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 238000000034 method Methods 0.000 abstract description 6
- 229920006254 polymer film Polymers 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 238000010276 construction Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 abstract 1
- 239000010409 thin film Substances 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 2
- 241001391944 Commicarpus scandens Species 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000002952 polymeric resin Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 229920003002 synthetic resin Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/145—Organic substrates, e.g. plastic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
Abstract
Description
【発明の詳細な説明】
本発明は半導体素子実装用基板に関し、とく
に、多数のSi半導体のLSI(大規模集積回路)を
搭載し、LSIチツプ間の結線および基板外部との
結線を行なう高密度実装基板に用いて効あるもの
である。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a board for mounting semiconductor elements, and in particular, to a high-density board that mounts a large number of Si semiconductor LSIs (Large-Scale Integrated Circuits) and performs connections between LSI chips and connections to the outside of the board. It is effective when used on mounting boards.
従来IC(集積回路)チツプは一個ずつパツケー
ジングしてDIL(Dual in Line)のピンをとり出
し、エポキシのプリント基板に搭載する方式がと
られてきた。この方法ではICチツプの面積に比
べパツケージングの占める面積が大きくIC実装
の高密度化に限界があつた。最近この問題を回避
してICチツプ実装の高密度化をはかるためにセ
ラミツクの多層基板にICチツプを直接接続する
方式が用いられるようになつてきている。このセ
ラミツク基板実装法においては、ICチツプとセ
ラミツク基板との電気的接続には通常はんだの小
球を用いるCCB(Controled Collapse Bonding)
法が用いられている。このはんだ接続技術におい
てはチツプに用いるSiと基板に用いるアルミナと
の熱膨張係数の差のために接続はんだ小球に大き
な応力が働き、接続部が破断しやすいという問題
がある。この傾向はチツプの面積を大きくした
り、はんだ小球の直径を小さくすると激しくな
り、チツプの大面積化および接続ピンの多ピン化
を妨げ、ひいてはチツプの高集積化を妨げる要因
となつていた。 Conventionally, IC (integrated circuit) chips were packaged one by one, the DIL (Dual in Line) pins were extracted, and the chips were mounted on an epoxy printed circuit board. In this method, the area occupied by the packaging was large compared to the area of the IC chip, and there was a limit to the high density of IC packaging. Recently, in order to avoid this problem and increase the density of IC chip mounting, a method of directly connecting IC chips to a ceramic multilayer substrate has been used. In this ceramic board mounting method, CCB (Controlled Collapse Bonding), which usually uses small solder balls, is used to electrically connect the IC chip and the ceramic board.
law is used. This solder connection technique has a problem in that the difference in thermal expansion coefficient between the Si used for the chip and the alumina used for the substrate causes large stress to act on the connecting solder balls, making the connections easy to break. This tendency becomes more severe when the area of the chip is increased or the diameter of the solder balls is decreased, which hinders the increase in the area of the chip and the increase in the number of connection pins, which in turn becomes a factor that hinders the high integration of the chip. .
本発明の目的は上記欠点のない半導体素子実装
用基板を提供することにある。 SUMMARY OF THE INVENTION An object of the present invention is to provide a substrate for mounting semiconductor elements without the above-mentioned drawbacks.
上記目的を達成するための本発明の構成は、基
板材料としてSiを用いICチツプと基板材料との熱
膨張係数の差をなくすことにある。このため、多
層配線を実現させるための絶縁膜としてポリイミ
ド等の比較的軟かいポリマーを用いることにより
チツプと基板との接続部における応力集中が防止
される。ポリマーは通常Siよりも熱膨張係数が大
きいが膜厚が薄いので、Si板上に形成したポリマ
ー膜の熱膨張の挙動はSiのそれにほぼ追従する。
したがつて、Si基板上に形成したポリマー膜上の
配線にはんだボールを用いてSiチツプを電気的に
接続したときには熱膨張を原因とする接続部の破
断はほぼなくなる。そのためチツプの大面積化お
よび接続ピンの高密度多ピン化が容易となる。 The structure of the present invention to achieve the above object is to use Si as the substrate material and eliminate the difference in thermal expansion coefficient between the IC chip and the substrate material. Therefore, by using a relatively soft polymer such as polyimide as an insulating film for realizing multilayer wiring, stress concentration at the connection between the chip and the substrate can be prevented. Polymers usually have a larger coefficient of thermal expansion than Si, but are thinner, so the thermal expansion behavior of polymer films formed on Si plates roughly follows that of Si.
Therefore, when a Si chip is electrically connected to a wiring on a polymer film formed on a Si substrate using a solder ball, there is almost no chance of breakage of the connection due to thermal expansion. Therefore, it becomes easy to increase the area of the chip and increase the number of connection pins with high density.
以下図面を参照しながら、実施例を用いて本発
明を具体的に説明する。 The present invention will be specifically described below using examples with reference to the drawings.
実施例
第1図aに示すように基板1として厚さ2mmの
シリコン板を用いた。これにレーザ又は電子ビー
ムを用いて直径1mmのスルーホール11をあけ
た。次に第1図bに示すように、上記基板1に酸
化処理をほどこして、SiO2の被膜2を基板表面
およびスルーホール11内部に形成した。次い
で、スルーホール内に導体ペースト3を充填し乾
燥固化し、平坦化処理をほどこした。つぎに第1
図cに示すように、ポリイミドイソンドロキナゾ
リンジオン(ポリイミドの一種で、以下PIKと略
称する)をスピンコートにより被着させ、10μm
のPIK膜4を形成した。PIK膜の所定の箇所にス
ルーホールをあけアルミニユーム配線5を施こし
た。さらに第1図dに示すように、PIK膜形成、
スルーホール孔あけ、アルミニウム配線工程を繰
返して第二配線層51を形成した。第二配線層の
上面にあるアルミ配線部の接続パツドに必要な表
面処理を行なつた。接続パツドにシリコンICチ
ツプ6をCCB接続する。Example As shown in FIG. 1a, a silicon plate with a thickness of 2 mm was used as the substrate 1. A through hole 11 with a diameter of 1 mm was made in this using a laser or an electron beam. Next, as shown in FIG. 1b, the substrate 1 was subjected to an oxidation treatment to form a SiO 2 coating 2 on the substrate surface and inside the through hole 11. As shown in FIG. Next, a conductive paste 3 was filled into the through holes, dried and solidified, and a flattening process was performed. Next, the first
As shown in Figure c, polyimide isondroquinazolinedione (a type of polyimide, hereinafter abbreviated as PIK) was deposited by spin coating, and a 10 μm thick
A PIK film 4 was formed. Through-holes were made at predetermined locations in the PIK film, and aluminum wiring 5 was applied. Furthermore, as shown in Figure 1d, PIK film formation,
A second wiring layer 51 was formed by repeating the through-hole drilling and aluminum wiring steps. Necessary surface treatment was performed on the connection pad of the aluminum wiring section on the top surface of the second wiring layer. Connect the silicon IC chip 6 to the connection pad using CCB.
以上説明したごとく本発明によればシリコンチ
ツプと配線基板との熱膨張の差を非常に小さくす
ることができる。そのため両者の接続部に働く応
力を小さくすることができ配線基板の信頼性を著
しく高めることができる。また上記両者の中間に
比較的軟かいポリマー絶縁膜を配置するので配線
の多層化が容易である。そのため多数のICチツ
プを一枚の配線基板に搭載することも容易となつ
た。 As explained above, according to the present invention, the difference in thermal expansion between the silicon chip and the wiring board can be made very small. Therefore, the stress acting on the connecting portion between the two can be reduced, and the reliability of the wiring board can be significantly improved. Furthermore, since a relatively soft polymer insulating film is placed between the above two layers, multilayer wiring can be easily formed. This has made it easier to mount multiple IC chips on a single wiring board.
第1図a〜dは本発明の一実施例としての半導
体実装基板の構造とその製造工程の概略を示した
説明図である。
1……Si基板、11……スルーホール、2……
酸化膜、3……導体ペースト、4……高分子樹脂
層、5および51……Al配線層、6……シリコ
ンICチツプ。
FIGS. 1A to 1D are explanatory diagrams schematically showing the structure of a semiconductor mounting board and its manufacturing process as an embodiment of the present invention. 1...Si substrate, 11...Through hole, 2...
Oxide film, 3...conductor paste, 4...polymer resin layer, 5 and 51...Al wiring layer, 6...silicon IC chip.
Claims (1)
軟質ポリマー層と、該軟質ポリマー層上に形成さ
れた配線と、該配線の所定の個所と半田で電気的
に接続されたICチツプとを有し、該半導体基板
と該ICチツプとは同じ材料からなることを特徴
とする半導体装置。 2 上記軟質ポリマーは、ポリイミドであること
を特徴とする特許請求の範囲第1項記載の半導体
装置。 3 上記半導体基板は、シリコンからなることを
特徴とする特許請求の範囲第1項又は第2項記載
の半導体装置。[Claims] 1. A semiconductor substrate, a soft polymer layer formed on the semiconductor substrate, a wiring formed on the soft polymer layer, and electrically connected to a predetermined location of the wiring by solder. What is claimed is: 1. A semiconductor device comprising a semiconductor substrate and an IC chip, wherein the semiconductor substrate and the IC chip are made of the same material. 2. The semiconductor device according to claim 1, wherein the soft polymer is polyimide. 3. The semiconductor device according to claim 1 or 2, wherein the semiconductor substrate is made of silicon.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP758882A JPS58125859A (en) | 1982-01-22 | 1982-01-22 | Substrate for mounting of semiconductor element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP758882A JPS58125859A (en) | 1982-01-22 | 1982-01-22 | Substrate for mounting of semiconductor element |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5213738A Division JPH0810738B2 (en) | 1993-08-30 | 1993-08-30 | Semiconductor device and manufacturing method thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS58125859A JPS58125859A (en) | 1983-07-27 |
JPH0439231B2 true JPH0439231B2 (en) | 1992-06-26 |
Family
ID=11669969
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP758882A Granted JPS58125859A (en) | 1982-01-22 | 1982-01-22 | Substrate for mounting of semiconductor element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58125859A (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2762705B2 (en) * | 1990-05-28 | 1998-06-04 | 松下電工株式会社 | Structure of circuit board for mounting semiconductor device |
JP2868167B2 (en) * | 1991-08-05 | 1999-03-10 | インターナショナル・ビジネス・マシーンズ・コーポレイション | Multi-level high density interconnect structures and high density interconnect structures |
US6696765B2 (en) | 2001-11-19 | 2004-02-24 | Hitachi, Ltd. | Multi-chip module |
JP3967108B2 (en) | 2001-10-26 | 2007-08-29 | 富士通株式会社 | Semiconductor device and manufacturing method thereof |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5473564A (en) * | 1977-11-24 | 1979-06-12 | Hitachi Ltd | Circuit device |
JPS552738A (en) * | 1978-06-20 | 1980-01-10 | Nippon Giken:Kk | Sheltering system of gas generated during electrolytic treatment and catching and collecting apparatus of gas |
JPS5514000A (en) * | 1978-07-12 | 1980-01-31 | Siemens Ag | Printed board |
JPS5571091A (en) * | 1978-11-24 | 1980-05-28 | Hitachi Ltd | Multilayer circuit board |
-
1982
- 1982-01-22 JP JP758882A patent/JPS58125859A/en active Granted
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5473564A (en) * | 1977-11-24 | 1979-06-12 | Hitachi Ltd | Circuit device |
JPS552738A (en) * | 1978-06-20 | 1980-01-10 | Nippon Giken:Kk | Sheltering system of gas generated during electrolytic treatment and catching and collecting apparatus of gas |
JPS5514000A (en) * | 1978-07-12 | 1980-01-31 | Siemens Ag | Printed board |
JPS5571091A (en) * | 1978-11-24 | 1980-05-28 | Hitachi Ltd | Multilayer circuit board |
Also Published As
Publication number | Publication date |
---|---|
JPS58125859A (en) | 1983-07-27 |
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