JPH0831976A - Silicon double-sided packaging substrate and its manufacturing method - Google Patents

Silicon double-sided packaging substrate and its manufacturing method

Info

Publication number
JPH0831976A
JPH0831976A JP6163640A JP16364094A JPH0831976A JP H0831976 A JPH0831976 A JP H0831976A JP 6163640 A JP6163640 A JP 6163640A JP 16364094 A JP16364094 A JP 16364094A JP H0831976 A JPH0831976 A JP H0831976A
Authority
JP
Japan
Prior art keywords
substrate
silicon substrate
silicon
hole
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6163640A
Other languages
Japanese (ja)
Inventor
Kiyoshi Hasegawa
潔 長谷川
Mutsusada Itou
睦禎 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP6163640A priority Critical patent/JPH0831976A/en
Publication of JPH0831976A publication Critical patent/JPH0831976A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0017Etching of the substrate by chemical or physical means
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038Through-connections; Vertical interconnect access [VIA] connections
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4673Application methods or materials of intermediate insulating layers not specially adapted to any one of the previous methods of adding a circuit layer
    • H05K3/4676Single layer compositions

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

PURPOSE:To improve packaging density of an electronic part mounting substrate with silicon as a substrate. CONSTITUTION:A through hole 2 is punched to a silicon substrate 1 using the wet etching process, powder beam process, or dry etching process, a conductor is formed inside the through hole 2, and the wirings on both surfaces of the silicon substrate are electrically connected. Further, a plurality of layers are wired on both surfaces of the silicon substrate 1 to create an electronic parts mounting substrate. Therefore, since electronic parts can be mounted on both surfaces of the silicon substrate and are electrically connected via through holes, the packaging density can be drastically improved and at the same time a circuit with improved high-frequency characteristics can be created.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、電子部品を実装する基
板に関するもので、更に詳しくはスルーホールで両面に
形成された配線の電気的接続をとる、シリコンの両面実
装基板に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a board for mounting electronic parts, and more particularly to a silicon double-sided board for electrically connecting wirings formed on both sides by through holes.

【0002】[0002]

【従来の技術】従来技術のシリコン基板を用いた実装基
板について、図5の電子部品を実装した状態での断面側
面図を参照して説明する。
2. Description of the Related Art A conventional mounting substrate using a silicon substrate will be described with reference to the sectional side view of FIG. 5 in which electronic components are mounted.

【0003】実装基板110はシリコン単結晶からなる
シリコン基板1の片面に少なくとも一層から成る配線層
を設け、その最上層の配線層に電子部品をハンダで固着
するものであり、その構成はシリコン基板1の上にパッ
シベーション膜12を形成しその上にCuの配線4A
を、また、ポリイミドやSiO2 等の絶縁体5を挟んで
配線4Bおよび4Cを設けて配線層4を形成し、各層の
配線は任意の位置で上下に接続している。中間にある配
線4Bは単層で図示されているが、複数層で構成してい
る場合が一般的である。配線層4の最上層である配線4
Cの導体に電子部品7をハンダ8で固着し、その他の導
体および絶縁体5の表面は絶縁材料を塗布し、表面絶縁
層6を形成している。
The mounting board 110 is one in which at least one wiring layer is provided on one surface of a silicon substrate 1 made of silicon single crystal, and electronic components are fixed to the uppermost wiring layer by soldering. The construction is a silicon substrate. 1. A passivation film 12 is formed on top of which a Cu wiring 4A is formed.
, And wirings 4B and 4C are provided with an insulator 5 such as polyimide or SiO2 sandwiched therebetween to form a wiring layer 4, and the wirings of each layer are connected vertically at arbitrary positions. Although the wiring 4B in the middle is shown as a single layer, it is common that the wiring 4B is made up of a plurality of layers. Wiring 4 which is the uppermost layer of wiring layer 4
The electronic component 7 is fixed to the conductor C by solder 8 and the other conductors and the surface of the insulator 5 are coated with an insulating material to form the surface insulating layer 6.

【0004】また、図示してないが、電子部品の実装基
板としては上述したシリコン基板の他にエポキシ樹脂と
の複合材料基板、あるいはセラミックス基板等がある
が、これらはシリコン基板に比較して配線密度、即ち実
装密度は遠く及ばない。特にエポキシ樹脂との複合材料
基板は温度、湿度による形状変化が大きく、実装された
小さなIC等では形状変化によるストレスが大きく、I
Cの破壊を招く虞がある。また、セラミック基板におい
ては耐候性は優れているが、セラミックを焼成する際に
形状変化が大きく、高密度実装に必要な高精度の寸法を
確保することが困難であった。
Although not shown in the figure, as a mounting substrate for electronic parts, there are a composite material substrate with an epoxy resin, a ceramics substrate and the like in addition to the above-mentioned silicon substrate. The density, ie the packaging density, is far below. In particular, a composite material substrate with an epoxy resin has a large shape change due to temperature and humidity, and a small mounted IC or the like has a large stress due to the shape change.
There is a possibility that C may be destroyed. In addition, although the ceramic substrate has excellent weather resistance, it is difficult to secure the highly accurate dimensions necessary for high-density mounting because the shape changes greatly when firing the ceramic.

【0005】[0005]

【発明が解決しようとする課題】以上説明したように、
従来のシリコンを基板とする電子部品実装基板において
は、スルーホールによる基板両面間の電気的接続をする
ことができず、半導体部品やチップ部品等の電子部品を
実装する面は実質的に片面に限定され、さらなる実装密
度の向上、小型化、軽量化等に対応することは難しく、
従って本発明はこの課題を解決しようとするものであ
る。
As described above,
In conventional electronic component mounting boards that use silicon as the substrate, it is not possible to make electrical connections between the both sides of the board by through holes, and the surface on which electronic components such as semiconductor components and chip components are mounted is practically one side. Limited, it is difficult to respond to further improvements in packaging density, downsizing, weight reduction, etc.
Therefore, the present invention seeks to solve this problem.

【0006】[0006]

【課題を解決するための手段】従って、電子部品を実装
するシリコン基板の両面に、微細な多層の電気配線と基
板両面間の電気的接続をとるためのスルーホールを半導
体製造技術であるウエットエッチングプロセス、パウダ
ービームプロセスおよびドライエッチングプロセスを利
用して作成し前記課題を解決した。
Therefore, a wet etching, which is a semiconductor manufacturing technique, is provided on both surfaces of a silicon substrate on which electronic components are mounted, and through holes for making electrical connection between fine multilayer electric wiring and both surfaces of the substrate. The above problems were solved by using a process, a powder beam process and a dry etching process.

【0007】[0007]

【作用】以上説明したスルーホールを有するシリコン両
面実装基板の構造と、半導体製造技術を応用した前記シ
リコン両面実装基板の製造方法を用いることにより、シ
リコン基板の両面に微細な多層の電気配線を作成するこ
とができるとともに、両面間の電気的接続ができるため
極めて高い密度で電子部品の実装をすることができる。
By using the structure of the silicon double-sided mounting board having the through holes described above and the method of manufacturing the silicon double-sided mounting board to which the semiconductor manufacturing technology is applied, fine multi-layer electric wiring is formed on both sides of the silicon substrate. In addition, since both sides can be electrically connected, electronic components can be mounted at an extremely high density.

【0008】[0008]

【実施例】本発明の実施例を図1ないし図4を参照して
説明する。図1はシリコン基板を用いた両面実装基板の
電子部品を実装した状態での断面側面図であり、図2
(a)ないし(h)はウエットエッチングプロセスを用
いた両面実装基板の製造工程を示す断面側面図であり、
図3(a)ないし(d)はパウダービームプロセスを用
いた両面実装基板の製造工程を示す断面側面図であり、
図4(a)および(b)はドライエッチングプロセスを
用いた両面実装基板の製造工程を示す断面側面図であ
る。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a cross-sectional side view of a double-sided mounting board using a silicon substrate in which electronic components are mounted.
(A) thru (h) are sectional side views showing a manufacturing process of a double-sided mounting substrate using a wet etching process,
3A to 3D are cross-sectional side views showing a manufacturing process of a double-sided mounting board using a powder beam process,
4 (a) and 4 (b) are cross-sectional side views showing a manufacturing process of a double-sided mounting substrate using a dry etching process.

【0009】図1に示す本発明によるシリコン基板を用
いた両面実装基板100の構成は、シリコン基板1の両
面にある配線4Aを電気的に接続する必要のある箇所に
スルーホール2が形成されていて、前記スルーホール2
の内部には導電体を充填したスルーホール導体3が形成
されている。その他の構成については従来例と同一であ
り、同一の符号を付して説明は省略する。
In the structure of the double-sided mounting substrate 100 using the silicon substrate according to the present invention shown in FIG. 1, the through holes 2 are formed at the positions where the wirings 4A on both sides of the silicon substrate 1 need to be electrically connected. The through hole 2
A through-hole conductor 3 filled with a conductor is formed inside the. The other configurations are the same as those of the conventional example, and the same reference numerals are given to omit the description.

【0010】前記シリコン基板1の両面に配線層4が形
成され、各々の面の配線層4の最上層である配線4Cに
電子部品7が固着されていて、両面の電子部品7はシリ
コン基板1に設けられたスルーホール導体3によって接
続され、一体となった回路を構成している。
Wiring layers 4 are formed on both surfaces of the silicon substrate 1, and an electronic component 7 is fixed to the wiring 4C which is the uppermost layer of the wiring layer 4 on each surface. Are connected by the through-hole conductors 3 provided in the above to form an integrated circuit.

【0011】次に、本発明による両面実装基板100の
製造方法である、ウエットエッチングプロセスを用いた
方法、パウダービームプロセスを用いた方法およびドラ
イエッチングプロセスを用いた方法について説明する。
Next, a method of using the wet etching process, a method of using the powder beam process, and a method of using the dry etching process, which are methods of manufacturing the double-sided mounting substrate 100 according to the present invention, will be described.

【0012】まず、第一の実施例であるウエットエッチ
ングプロセスを用いてスルーホールを作成する両面実装
基板の製造方法について、図2(a)ないし(h)を参
照して説明する。
First, a method of manufacturing a double-sided mounting board in which a through hole is formed by using a wet etching process according to the first embodiment will be described with reference to FIGS. 2 (a) to 2 (h).

【0013】シリコン基板1の両面に熱酸化膜あるいは
CVD法等による窒化膜等のパッシベーション膜12を
形成する。その後、その両面にレジスト13を塗布し、
レジスト13を露光、現像して開口部14を形成する
〔図2(a)〕。
A passivation film 12 such as a thermal oxide film or a nitride film is formed on both surfaces of the silicon substrate 1 by a CVD method or the like. After that, apply resist 13 on both sides,
The resist 13 is exposed and developed to form the opening 14 [FIG. 2 (a)].

【0014】次に、前記開口部14を利用して、ドライ
エッチングによりパッシベーション膜12に開口部15
を形成し〔図2(b)〕、シリコン基板1をシリコンの
エッチング液(例えばHF+HNO3 )に浸漬し、シリ
コン基板1にスルーホール2を形成する〔図2
(c)〕。
Next, the opening 15 is formed in the passivation film 12 by dry etching using the opening 14.
Is formed [FIG. 2 (b)], the silicon substrate 1 is immersed in a silicon etching solution (for example, HF + HNO 3 ) to form the through holes 2 in the silicon substrate 1 [FIG.
(C)].

【0015】スルーホール2の側壁にパッシベーション
膜17を形成するため、シリコン基板1に再び熱酸化膜
あるいは窒化膜を形成する〔図2(d)〕。ここで、シ
リコン基板1の厚さは例えば400μm、パッシベーシ
ョン膜12、17の厚さはともに数nm、レジスト13
の厚さは1μm、レジスト開口部14はその基板開口の
上面において、例えば直径1mm程度である。
In order to form the passivation film 17 on the side wall of the through hole 2, a thermal oxide film or a nitride film is formed again on the silicon substrate 1 (FIG. 2 (d)). Here, the silicon substrate 1 has a thickness of, for example, 400 μm, the passivation films 12 and 17 have a thickness of several nm, and the resist 13 has a thickness of several nm.
Has a thickness of 1 μm, and the resist opening 14 has a diameter of, for example, about 1 mm on the upper surface of the substrate opening.

【0016】次に、印刷等の方法によりスルーホール2
に導電性ペースト18を埋め込み、その後、導電性ペー
スト18を固化させるための焼成を行い、スルーホール
2に電導体を形成して両面の配線4C間の電気的接続を
得る〔図2(e)〕。
Next, the through hole 2 is formed by a method such as printing.
The conductive paste 18 is embedded in the conductive paste 18 and then baked to solidify the conductive paste 18, and an electric conductor is formed in the through hole 2 to obtain an electrical connection between the wirings 4C on both sides [FIG. 2 (e)]. ].

【0017】また、電気的接続を得る別の方法として、
図2(d)に示す状態からシリコン基板1全体にCuの
無電解メッキ19を施し、その後Cuの電解メッキ20
を行う〔図2(f)〕。次に、Cuの不要部分をレジス
ト22を用いてエッチングすると図2(g)のようにス
ルーホール2に導電体であるメッキ層21が形成され、
両面の配線4C間の電気的接続を得ることができる。
尚、レジスト22を剥離し、更に、液体レジスト23を
スルーホール2に埋め込み封鎖して基板を平坦にし、後
工程において障害が起こらないようにする。
As another method for obtaining electrical connection,
2D, Cu electroless plating 19 is applied to the entire silicon substrate 1, and then Cu electroplating 20 is performed.
Is performed [FIG. 2 (f)]. Next, when unnecessary portions of Cu are etched using a resist 22, a plated layer 21 which is a conductor is formed in the through hole 2 as shown in FIG.
Electrical connection between the wirings 4C on both sides can be obtained.
The resist 22 is peeled off, and the liquid resist 23 is embedded and sealed in the through hole 2 to flatten the substrate so that no obstacle will occur in a subsequent process.

【0018】上述したようにスルーホール導体3を形成
してシリコン基板1の両面の電気的接続をとったのち、
シリコン基板1の両面に従来の方法でCuとポリイミド
あるいはCuとSiO2 等から成る配線層4を形成して
シリコンの両面実装基板を得るものである。
After the through-hole conductor 3 is formed as described above to electrically connect both surfaces of the silicon substrate 1,
A wiring layer 4 made of Cu and polyimide or Cu and SiO 2 is formed on both sides of the silicon substrate 1 by a conventional method to obtain a silicon double-sided mounting substrate.

【0019】次に、第二の実施例であるパウダービーム
プロセスを用いてスルーホールを作成する両面実装基板
の製造方法について、図3(a)ないし(d)を参照し
て説明する。
Next, a method of manufacturing a double-sided mounting board for forming a through hole by using the powder beam process according to the second embodiment will be described with reference to FIGS. 3 (a) to 3 (d).

【0020】シリコン基板1の表面にレジスト24を塗
布し、その後、露光、現像してスルーホールを穿設する
箇所のレジスト24を除去する〔図3(a)〕。次に、
パウダービーム加工機を用いてシリコン基板1を異方性
エッチングすることにより、レジスト24を除去した箇
所にスルーホール2を穿孔することができる〔図3
(b)〕。
A resist 24 is applied to the surface of the silicon substrate 1 and then exposed and developed to remove the resist 24 at the locations where through holes are to be formed [FIG. 3 (a)]. next,
By anisotropically etching the silicon substrate 1 using a powder beam processing machine, it is possible to form the through holes 2 at the places where the resist 24 has been removed [FIG.
(B)].

【0021】レジスト24を剥離しシリコン基板1の両
面に熱酸化膜あるいは窒化膜等のパッシベーション膜1
2を形成した後、スルーホール2に印刷等の方法により
導電性ペースト18を埋め込む。次に、導電性ペースト
18を固化させるための焼成を行い、スルーホール導電
体3を形成してしてシリコン基板1の両面の配線4C間
の電気的接続を得るものである〔図3(c)〕。
The resist 24 is peeled off, and a passivation film 1 such as a thermal oxide film or a nitride film is formed on both surfaces of the silicon substrate 1.
After forming 2, the conductive paste 18 is embedded in the through hole 2 by a method such as printing. Next, firing is performed to solidify the conductive paste 18 to form the through-hole conductors 3 to obtain electrical connection between the wirings 4C on both surfaces of the silicon substrate 1 [FIG. )].

【0022】あるいはまた、ウエットエッチングプロセ
スで説明したように、図3(b)に示す状態からシリコ
ン基板1の両面に熱酸化膜あるいは窒化膜等のパッシベ
ーション膜12を形成した後、Cuの無電解メッキ19
を施し、その後Cuの電解メッキ20を行い、次に、C
uの不要部分をレジストを用いてエッチングすることに
よってスルーホール2に導電体が形成され、両面の配線
間の電気的接続を得るものである。尚、液体レジスト2
3をスルーホール2に埋め込み封鎖して基板を平坦に
し、後工程において障害が起こらないようにする。
Alternatively, as described in the wet etching process, a passivation film 12 such as a thermal oxide film or a nitride film is formed on both surfaces of the silicon substrate 1 from the state shown in FIG. Plating 19
And then electrolytic plating 20 of Cu, and then C
By etching an unnecessary portion of u using a resist, a conductor is formed in the through hole 2 and electrical connection between the wirings on both sides is obtained. Liquid resist 2
3 is embedded in the through hole 2 and sealed to flatten the substrate so that no obstacle will occur in the subsequent process.

【0023】上述したようにスルーホール導体3を形成
してシリコン基板1の両面の電気的接続を形成したの
ち、シリコン基板1の両面にCuとポリイミドあるいは
CuとSiO2 等から成る配線層4を形成することは第
一の実施例と同じである。
After the through-hole conductors 3 are formed to electrically connect both sides of the silicon substrate 1 as described above, the wiring layer 4 made of Cu and polyimide or Cu and SiO 2 is provided on both sides of the silicon substrate 1. Forming is the same as in the first embodiment.

【0024】更に、第三の実施例であるドライエッチン
グプロセスを用いてスルーホールを作成する両面実装基
板の製造方法について、図4(a)および(b)を参照
して説明する。
Further, a method of manufacturing a double-sided mounting board in which a through hole is formed by using the dry etching process according to the third embodiment will be described with reference to FIGS. 4 (a) and 4 (b).

【0025】シリコン基板1の表面にレジスト25を塗
布し、その後、露光、現像してスルーホール2を穿設す
る箇所のレジスト25を除去する〔図4(a)〕。これ
を例えば反応性スパッタエッチング装置でSF6 ガスを
用いてエッチングを行う等の異方性エッチング方法を用
いることにより、図4(b)に示すような直線状の側壁
を持ったスルーホール2をシリコン基板1に穿孔するこ
とができる。ここでシリコン基板1の厚さは例えば30
0μm、レジスト24の厚さは数μm、スルーホール2
の直径は数10μmである。
A resist 25 is applied to the surface of the silicon substrate 1 and then exposed and developed to remove the resist 25 at the places where the through holes 2 are to be formed [FIG. 4 (a)]. By using this anisotropic etching method such as etching with SF 6 gas in a reactive sputter etching apparatus, a through hole 2 having a linear side wall as shown in FIG. 4B is formed. The silicon substrate 1 can be perforated. Here, the thickness of the silicon substrate 1 is, for example, 30
0 μm, thickness of resist 24 is several μm, through hole 2
Has a diameter of several tens of μm.

【0026】レジスト24を剥離すると上述した第二の
実施例でで説明した示した図3(b)の状態が得られ、
以下の配線プロセスは第二の実施例と同一であり説明は
省略する。
When the resist 24 is peeled off, the state shown in FIG. 3 (b) described in the second embodiment is obtained,
The subsequent wiring process is the same as that of the second embodiment, and the description thereof is omitted.

【0027】第二の実施例であるパウダービームプロセ
スおよび第三の実施例であるドライエッチングプロセス
で形成されるスルーホールは、第一の実施例であるウエ
ットエッチングプロセスで形成される図2(c)に示す
ような中央部が突出した形状ではなく、直線状の側壁を
持ったスルーホールにすることができる。従って、第二
と第三のプロセスを用いることで第一のプロセスより微
細なスルーホールを形成することができ、配線密度を更
に上げることができる。
The through holes formed by the powder beam process of the second embodiment and the dry etching process of the third embodiment are formed by the wet etching process of the first embodiment as shown in FIG. It is possible to form a through hole having a linear side wall instead of the shape in which the central portion is projected as shown in FIG. Therefore, by using the second and third processes, finer through holes can be formed than in the first process, and the wiring density can be further increased.

【0028】[0028]

【発明の効果】以上説明したように、本発明によれば、
シリコン実装基板の両面の電気的導通をとることができ
るため、より一層の高密度な電子部品の実装を実現する
ことができる。また、配線長を短くすることができるた
め、高周波特性に優れた回路を形成することができる。
As described above, according to the present invention,
Since electrical conduction can be established on both sides of the silicon mounting board, it is possible to realize mounting of electronic components with higher density. Further, since the wiring length can be shortened, a circuit having excellent high frequency characteristics can be formed.

【0029】基板がシリコンであるため、ICのベアチ
ップと温度または湿度等の特性が同じであり、ベアチッ
プ実装後の基板との親和性がよい。また、シリコン加工
に半導体製造技術を用いることができ、高精度で微細な
実装基板を作成することができる。
Since the substrate is made of silicon, the characteristics of the IC such as temperature and humidity are the same as those of the bare chip of the IC, and the affinity with the substrate after mounting the bare chip is good. Further, a semiconductor manufacturing technique can be used for silicon processing, and a highly accurate and fine mounting substrate can be created.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明によるシリコン基板を用いた両面実装
基板の電子部品を実装した状態での断面側面図である。
FIG. 1 is a cross-sectional side view of a double-sided mounting substrate using a silicon substrate according to the present invention in which electronic components are mounted.

【図2】 ウエットエッチングプロセスを用いた両面実
装基板の製造工程を示す断面側面図である。
FIG. 2 is a sectional side view showing a manufacturing process of a double-sided mounting substrate using a wet etching process.

【図3】 パウダービームプロセスを用いた両面実装基
板の製造工程を示す断面側面図である。
FIG. 3 is a sectional side view showing a manufacturing process of a double-sided mounting substrate using a powder beam process.

【図4】 ドライエッチングプロセスを用いた両面実装
基板の製造工程を示す断面側面図である。
FIG. 4 is a sectional side view showing a manufacturing process of a double-sided mounting substrate using a dry etching process.

【図5】 従来のシリコン基板を用いた実装基板の電子
部品を実装した状態での断面側面図である。
FIG. 5 is a cross-sectional side view of a mounting board using a conventional silicon substrate in a state where electronic components are mounted.

【符号の説明】[Explanation of symbols]

1 シリコン基板 2 スルーホール 3 スルーホール導電体 4 配線層 5 絶縁体 6 表面絶縁層 7 電子部品 8 ハンダ 12 パッシベーション膜 13 レジスト 14 開口部 17 パッシベーション膜 18 導電性ペースト 19 無電解メッキ 20 電解メッキ 21 メッキ層 23 液体レジスト 1 Silicon Substrate 2 Through Hole 3 Through Hole Conductor 4 Wiring Layer 5 Insulator 6 Surface Insulating Layer 7 Electronic Component 8 Solder 12 Passivation Film 13 Resist 14 Opening 17 Passivation Film 18 Conductive Paste 19 Electroless Plating 20 Electroplating 21 Plating Layer 23 Liquid resist

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 シリコンを基板とする電子部品実装基板
において、 シリコンウエハーの両面に、電子部品を実装し配線する
少なくとも一層から成る配線層を設け、更に、前記両面
の配線層を電導性のスルーホールで電気的に接続するこ
とを特徴とする、シリコン両面実装基板。
1. An electronic component mounting board using silicon as a substrate, wherein a wiring layer consisting of at least one layer for mounting and wiring electronic components is provided on both surfaces of a silicon wafer, and the wiring layers on both surfaces are electrically conductive. A silicon double-sided mounting board characterized by being electrically connected through a hole.
【請求項2】 ウエットエッチングプロセスを用いて該
実装基板のスルーホールを作成することを特徴とする、
請求項1に記載したシリコン両面実装基板の製造方法。
2. A through hole of the mounting board is formed by using a wet etching process,
A method for manufacturing the silicon double-sided mounting substrate according to claim 1.
【請求項3】 パウダービームプロセスを用いて該実装
基板のスルーホールを作成することを特徴とする、請求
項1に記載したシリコン両面実装基板の製造方法。
3. The method for manufacturing a silicon double-sided mounting substrate according to claim 1, wherein the through-holes of the mounting substrate are created by using a powder beam process.
【請求項4】 ドライエッチングプロセスを用いて該実
装基板のスルーホールを作成することを特徴とする、請
求項1に記載したシリコン両面実装基板の製造方法。
4. The method of manufacturing a silicon double-sided mounting substrate according to claim 1, wherein the through hole of the mounting substrate is formed by using a dry etching process.
JP6163640A 1994-07-15 1994-07-15 Silicon double-sided packaging substrate and its manufacturing method Pending JPH0831976A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6163640A JPH0831976A (en) 1994-07-15 1994-07-15 Silicon double-sided packaging substrate and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6163640A JPH0831976A (en) 1994-07-15 1994-07-15 Silicon double-sided packaging substrate and its manufacturing method

Publications (1)

Publication Number Publication Date
JPH0831976A true JPH0831976A (en) 1996-02-02

Family

ID=15777791

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6163640A Pending JPH0831976A (en) 1994-07-15 1994-07-15 Silicon double-sided packaging substrate and its manufacturing method

Country Status (1)

Country Link
JP (1) JPH0831976A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003005786A1 (en) * 2001-07-05 2003-01-16 Mejiro Precision, Inc. Method for manufacturing printed wiring board
JP2006100653A (en) * 2004-09-30 2006-04-13 Dainippon Printing Co Ltd Wiring board and manufacturing method thereof
JP2006287085A (en) * 2005-04-04 2006-10-19 Sony Corp Method for manufacturing wiring substrate
JP2007214437A (en) * 2006-02-10 2007-08-23 Dainippon Printing Co Ltd Wiring board incorporated with passive element, and manufacturing method thereof
JP2008205145A (en) * 2007-02-20 2008-09-04 Nec Electronics Corp Semiconductor device and its manufacturing method

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003005786A1 (en) * 2001-07-05 2003-01-16 Mejiro Precision, Inc. Method for manufacturing printed wiring board
KR100914376B1 (en) * 2001-07-05 2009-08-28 메지로 프리씨젼 가부시끼가이샤 Method for manufacturing printed wiring board
JP2006100653A (en) * 2004-09-30 2006-04-13 Dainippon Printing Co Ltd Wiring board and manufacturing method thereof
JP4504774B2 (en) * 2004-09-30 2010-07-14 大日本印刷株式会社 Wiring board manufacturing method
JP2006287085A (en) * 2005-04-04 2006-10-19 Sony Corp Method for manufacturing wiring substrate
JP2007214437A (en) * 2006-02-10 2007-08-23 Dainippon Printing Co Ltd Wiring board incorporated with passive element, and manufacturing method thereof
JP2008205145A (en) * 2007-02-20 2008-09-04 Nec Electronics Corp Semiconductor device and its manufacturing method

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