JP4570051B2 - Circuit boards, electronic devices and their manufacture - Google Patents

Description

  The present invention relates to a circuit board having a three-dimensional circuit, an electronic device, and a manufacturing method thereof.

  Examples of electronic devices having a three-dimensional circuit include various scale integrated circuits, various semiconductor elements, or chips thereof.

  In this type of electronic device, as a technique for realizing the three-dimensional circuit arrangement, conventionally, semiconductor packages are stacked on a substrate, and a wire bonding or a TAB tape is used between the semiconductor package and a conductor pattern on the substrate. It was common to connect.

  However, in a structure in which packages are stacked, the entire module becomes extremely thick. Even when wire bonding or TAB tape is used, the element itself has a large molded shape, which is a major obstacle to miniaturization.

  Furthermore, conventional mounting technology cannot cope with high-speed and high-integration of IT equipment, which is the main application of this type of electronic device. In other words, IT devices are required to be more compact (low power consumption) as well as more compact (high speed, large capacity). In the above-described conventional technology, first, this requirement is met from the viewpoint of miniaturization. I can't. Moreover, the internal clock of the LSI that constitutes the main part of the IT equipment is as fast as several GHz in recent CPUs, but the signal transmission clock to the outside of the chip is several hundred MHz, and wiring delay becomes a big problem. ing. Furthermore, the delay in the buffer circuit for outputting the signal to the outside and the power consumption for driving cannot be ignored. These requests cannot be met by the prior art.

  Conventionally, in order to connect a plurality of LSIs, a method has been used in which LSIs are two-dimensionally arranged on a printed circuit board and connected between them by multilayer wiring. However, in this method, the mounting area increases with the number of LSIs, and the signal delay between LSIs increases due to the increase in wiring length.

  In view of this, a technique has been proposed in which a circuit pattern for forming a signal transmission line is provided on the substrate, while a circuit substrate is provided which is conductive to the circuit pattern and has a through electrode penetrating in the thickness direction of the substrate. .

  As such a substrate, for example, in Patent Document 1, in a method of filling a liquid viscous material into a through hole or a non-through hole of a multilayer circuit substrate, the liquid viscous material is stencil printed on the circuit substrate in a vacuum atmosphere. After that, a method of filling a liquid viscous material is disclosed in which the vacuum degree of the vacuum atmosphere is lowered or the vacuum atmosphere is changed to a normal atmospheric pressure to perform differential pressure filling.

  In Patent Document 2, a through hole having a high aspect ratio is formed in a substrate by a photoexcited electrolytic polishing method, an inner wall of the through hole is oxidized to form an oxide film as an insulating layer, and then the through hole is formed. Discloses a method of forming a through electrode by filling a metal with a molten metal backfilling method.

  However, in any conventional technique including the techniques disclosed in Patent Documents 1 and 2, the through electrode and the circuit pattern are formed in separate steps, and both are mechanically and physically connected. Therefore, in particular, in the high frequency region, the contact resistance at the connection portion between the two cannot be ignored, and there is a problem that the high frequency characteristics are deteriorated such as an increase in high frequency loss.

  The prior art is mainly intended for the case where the through hole has a hole diameter of about 50 μm or more and a hole depth / hole diameter ratio (L / d: aspect ratio) of about 2 to 3. Recently, due to the demand for high-density wiring and the like, a through-electrode having a pore diameter of 25 μm or less and an aspect ratio of 5 or more is required. When the above-described prior art is applied under such a condition, an unfilled portion tends to remain particularly at the bottom of the non-through hole, and thus there is a possibility that the reliability and quality of the through electrode may be impaired.

  As another method, vias are formed in bump formation areas existing on the surface of the substrate by a solder paste method, solder ball method or plating method, and solder paste or solder balls are filled or plated in the vias. The method of doing is also known.

  However, with this method, it is difficult to accurately and regularly form vias having a hole diameter of 100 μm or less, a spot diameter of 100 μm or less, and a pitch width of 100 μm or less. In the current situation where lead-free products must be satisfied in order to cope with environmental conservation, the difficulty is further increased. In addition, since the bump forming step and the through electrode forming step must be separate steps, it is easy to impair the reliability of the connection between the two.

  As a means for achieving high density, there is a method of forming a thin film having a miniaturized multi-layered structure by using a photolithography process and a thin film forming technique, but this method is technically difficult. In addition, huge capital investment is required and there are problems such as high cost.

Further, Patent Document 3 discloses a method for filling a metal with a fine hole by an atmospheric pressure difference, and Patent Document 4 describes a filling method for filling a fine hole with a conductive paste. Further, Patent Document 5 discloses a method of forming a through electrode in which a metal is directly embedded in a through hole before and after the plating embedding process. However, none of the patent documents discloses a technique for solving the above-described problems.
JP 11-298138 A JP 2000-228410 A JP 2002-158191 A JP 2003-257891 A JP 2006-111896 A

  An object of the present invention is to provide a circuit board having a three-dimensional circuit structure with low high-frequency loss and thus excellent high-frequency characteristics, and an electronic device using the circuit board.

  Another object of the present invention is to provide a circuit board manufacturing method capable of forming a through electrode with high reliability and high quality by avoiding generation of an unfilled portion inside a through hole even at a high aspect ratio. Is to provide.

  Still another object of the present invention is to provide a method capable of inexpensively manufacturing a circuit board having a three-dimensional circuit.

  In order to solve the above-described problems, the present invention discloses a circuit board, an electronic device using the circuit board, and a method for manufacturing the circuit board.

<Circuit board>
The circuit board according to the present invention constitutes a three-dimensional circuit including a circuit pattern and a through electrode on the board. The circuit pattern is provided on at least one surface of the substrate, and the through electrode is filled in a through hole extending in the thickness direction from the one surface of the substrate.

  The circuit pattern and the through electrode are continuous conductors formed in the same body from the same metal material or alloy material without having a joint portion therebetween.

  As described above, since the circuit pattern and the through electrode are continuous conductors formed of the same metal material or alloy material without having a joint portion therebetween, the through electrode and the circuit pattern are separated from each other. Unlike the conventional structure in which the two are physically overlapped and connected to each other, there are no mechanical and physical connection portions. For this reason, there are no factors causing the deterioration of the high frequency characteristics such as the generation of contact resistance and the increase of the high frequency loss.

  The present invention is particularly effective when the through electrode is a fine hole having a pore diameter of 100 μm or less and an aspect ratio of 1 or more, preferably a pore diameter of 25 μm or less and an aspect ratio of 5 or more. Even under such fine and high-density wiring conditions, an increase in high-frequency loss due to contact resistance can be avoided and excellent high-frequency characteristics can be ensured.

  As a specific aspect, a plurality of substrates can be used, and each substrate can be sequentially stacked, and at least one of the substrates can employ a structure including the circuit pattern and the through electrode. Thereby, a circuit board having a complicated three-dimensional circuit can be realized.

<Electronic device>
The electronic device according to the present invention includes a circuit board and a circuit function unit. The circuit board is a circuit board according to the present invention. The circuit function unit is combined with the circuit board.

  Since the electronic device according to the present invention includes the circuit board according to the present invention, the function and effect of the circuit board can be exhibited as they are.

<Circuit board manufacturing method>
In the method of manufacturing a circuit board according to the present invention, first, a non-through hole is formed in one surface of the wafer. Then, while applying ultrasonic vibration to the wafer in a vacuum atmosphere, the molten metal material is filled into the hole and diffused on the one surface using the melt flow pressure.

  By including the above process, even if the through hole has a high aspect ratio, a highly reliable and high quality through electrode can be formed while avoiding the occurrence of an unfilled portion inside the through hole.

  Moreover, it is only necessary to fill the inside of the hole with the molten metal material and diffuse it to one surface of the wafer while applying fine vibrations to the wafer in a vacuum atmosphere. Unlike a method for forming a thin film having a miniaturized multi-layered structure by using a process and a thin film forming technique, the technical difficulty is low and the capital investment is small. For this reason, the cost of the circuit board itself can be reduced.

  The circuit pattern and the through electrode are preferably made of a material having Sn as a main component and a melting point in the range of 500 ° C. to 130 ° C. According to such a material, the molten metal material is introduced into the inside of the hole using the melt flow pressure while giving fine vibration to the substrate even for a fine hole having a hole diameter of 25 μm or less and an aspect ratio of 5 or more. By filling, it is possible to form a highly reliable and high quality through electrode and a continuous circuit pattern while avoiding the occurrence of an unfilled portion in the interior.

More preferably, the circuit pattern and the through electrode are polycrystalline aggregates mainly composed of Sn and having a re- solidified crystal of 500 nm or less. As a result, it is possible to form a stable circuit pattern and through electrode having a low electrical resistance.

As described above, according to the present invention, the following effects can be obtained.
(A) It is possible to provide a circuit board and an electronic device having a three-dimensional circuit structure with low high-frequency loss and thus excellent high-frequency characteristics.
(B) Even when the aspect ratio is high, it is possible to provide a circuit board manufacturing method that can avoid formation of an unfilled portion in the through hole and can form a highly reliable and high quality through electrode. .
(C) It is possible to provide a method capable of manufacturing a circuit board having a three-dimensional circuit, and thus an electronic device using the circuit board, at low cost.

  Other objects, configurations and advantages of the present invention will be described in more detail with reference to the accompanying drawings. However, the attached drawings are merely examples.

<Circuit board>
FIG. 1 is a sectional view schematically showing the structure of a circuit board according to the present invention. Although FIG. 1 only shows a simple configuration, in practice, a more complicated structure is taken to satisfy the functions and structures corresponding to the types of circuit boards described above.

Referring to FIG. 1, the circuit board forms a three-dimensional circuit with a circuit pattern 2 and a through electrode 3 on the board 1. The substrate 1 is composed of various semiconductor substrates, dielectric substrates, insulating substrates, magnetic substrates, or the like. The substrate 1 according to the embodiment is an insulating substrate, for example, a dielectric substrate or an insulating substrate. In the case of a semiconductor substrate such as a silicon wafer, insulating films are provided on both surfaces thereof and on the interface between the through electrode 3 and the substrate 1. The insulating film is a film of a metal oxide, for example, SiO ₂ or Al ₂ O ₃ , and can be formed in a necessary thickness (depth) at a necessary position by a known chemical treatment.

  The circuit pattern 2 is provided on at least one surface of the substrate 1. Although not shown, the circuit pattern 2 may be provided on both surfaces of the substrate 1. This circuit pattern 2 constitutes a signal transmission line, and takes various plane patterns according to a required pattern. It is simply different from a so-called “land” used as a connection conductor for the through electrode 2. The circuit pattern 2 may be filled with an insulating film as necessary.

  The through electrode 3 is filled in a through hole 20 extending in the thickness direction from one surface of the substrate 1. Although only one through electrode 3 in the figure is provided for one circuit pattern 2, the present invention is not limited to this. A plurality of through electrodes 3 may be provided for one circuit pattern 2. The depth L and the diameter d of the through-hole 20 have a diameter d of 100 μm or less and an aspect ratio (L / d) of 1 or more, particularly preferably a diameter d of 25 μm or less and an aspect ratio (L / d) of 5 or more. Select so that Such a through hole 20 can be formed by, for example, laser drilling or chemical treatment.

  The most significant feature of the present invention is that the circuit pattern 2 and the through electrode 3 are formed of a continuous conductor formed of the same metal material or alloy material without having a joint portion therebetween.

  As described above, since the circuit pattern 2 and the through electrode 3 are continuous conductors formed of the same metal material or alloy material without having a joint portion therebetween, the through electrode 3 and the circuit pattern Unlike the conventional structure in which the two are formed separately and the two are physically overlapped and connected, there are no mechanical and physical connection portions. For this reason, there are no factors causing the deterioration of the high frequency characteristics such as the generation of contact resistance and the increase of the high frequency loss.

  In particular, the through electrode 3 avoids an increase in high-frequency loss due to contact resistance and has excellent high-frequency characteristics even under the condition of a fine and high-density wiring having a diameter d of 25 μm or less and an aspect ratio of 5 or more. Can be secured.

  The circuit pattern 2 and the through electrode 3 are preferably made of a metal material or alloy material containing Sn as a main component. According to the metal material or alloy material containing Sn as a main component, the following merit in manufacturing can be obtained and necessary conductivity can be ensured.

  FIG. 2 is an exploded view showing an example of a circuit board according to the present invention, and FIG. 3 is a view showing a laminated state (finished product). The illustrated circuit board has a multi-layered structure in which an arbitrary number of circuit boards A1 to A6 are sequentially stacked. A structure including the circuit pattern 2 and the through electrode 3 can be employed in at least one of the layers.

  In the illustrated embodiment, each of the circuit boards A1 to A6 has a structure in which the circuit pattern 2 and the through electrode 3 are provided on the board 1. The circuit pattern 2 is formed on one surface of each of the circuit boards A1 to A6. Some of the circuit patterns 2 are arranged across a plurality of adjacent through electrodes 3.

  The circuit boards A1 to A6 are bonded by an adhesive at the laminated interface. In the drawing, the through electrodes 3 are all connected between the circuit boards A1 to A6, but may not be connected depending on the circuit configuration. Further, bumps (extraction electrodes) 60 to 69 are provided on the outermost circuit boards A1 and A6 as necessary. The multilayer laminated structure shown in FIGS. 2 and 3 is suitable for realizing a circuit board having a complicated three-dimensional circuit. An example is shown below.

<Electronic device>
The electronic device according to the present invention includes a sensor module, a photoelectric module, a unipolar transistor, a MOS FET, a CMOS FET, a memory cell, an FC (Field Complementary) chip, or an integrated circuit component (IC) thereof, or various scales. In general, most LSIs having an electronic circuit as a functional element can be included. In particular, an integrated circuit LSI using the circuit board according to the present invention as an interposer is suitable as a representative example. In the present invention, the term “integrated circuit LSI” includes all of small scale integrated circuits, medium scale integrated circuits, large scale integrated circuits, ultra large scale integrated circuits VLSI, ULSI, and the like.

  An example is shown in FIG. In FIG. 4, a first integrated circuit LSI1 as a circuit function unit is mounted on one surface of a first interposer INT1 using a circuit board according to the present invention, and the first integrated circuit LSI1 is mounted on one surface. The second interposer INT2 using the circuit board according to the present invention is mounted, and the second integrated circuit LSI2 is mounted on one surface of the second interposer INT2.

  However, the number of the first and second interposers INT1, INT2, the internal wiring, the thickness, the shape, and the like are arbitrary. The same applies to the first and second integrated circuits LSI1 and LSI2.

  Signals from the first integrated circuit LSI1 to the upper second integrated circuit LSI2 are transmitted to the second interpose INT2 through connection portions called bumps. In the second interpose INT2, the signal is transmitted to the target bumps 65 to 69 through the internal wirings 2 and 3, and the signal is transmitted to the second integrated circuit LSI2 through the bumps 65 to 69. Signal transmission to the lower first integrated circuit LSI1 can be similarly performed.

  As shown in FIG. 4, the circuit board according to the present invention is the first and second interposers INT1 and INT2, and the first and second integrated circuits LSI1 and LSI2 are overlapped on this to operate as a single chip. As a result, it is possible to realize ultra-small packaging of electronic circuits that are the heart of IT equipment and high-speed signal transmission between the first and second integrated circuits LSI1 and LSI2.

  In addition, the second interposer INT2 is arranged between the stacked layers of the first and second integrated circuits LSI1 and LSI2, and enables high-density and high-speed signal transmission.

  In addition, the internal clock of the integrated circuit is as fast as several GHz in recent CPUs, whereas the signal transmission clock to the outside of the chip is several hundred MHz, so wiring delay is a big problem. By using the circuit board according to the present invention as the first and second interposers INT1 and INT2, the wiring length can be minimized and the problem caused by the wiring delay can be solved.

  Furthermore, the delay in the buffer circuit for outputting the signal to the outside and the power consumption for driving cannot be ignored, but by using the circuit board according to the present invention as the first and second interposers INT1, INT2, Power consumption can also be reduced.

  If a CPU, a cache main memory, an IO chip, and the like are stacked on one chip, an ultra-compact and high-performance microcomputer system can be realized.

<Others>
In FIG. 4, the circuit board according to the present invention is configured as independent from the first and second integrated circuits LSI1 and LSI2, but the internal structure of the first and second integrated circuits LSI1 and LSI2, in particular, The present invention can also be applied to the local wiring portion. Further, the present invention can be applied not only to the active circuit element but also to the internal wiring structure of the passive circuit element.

<Circuit board manufacturing method>
Next, with reference to FIGS. 7-10, the manufacturing method of the circuit board based on this invention is demonstrated. In the method of manufacturing a circuit board according to the present invention, first, a resist mask 7 is formed on one surface of a substrate (wafer) 1 as shown in FIG. The resist mask 7 can be obtained by performing a well-known photolithography process.

  Subsequently, a predetermined position in the extraction pattern 71 surrounded by the resist mask 7 is irradiated with, for example, a laser to form a hole 20 as illustrated in FIG. The holes 20 are formed as non-through holes that remain inside the substrate 1. Instead of the laser, a chemical reaction etching method may be used.

  Next, as shown in FIG. 7, the substrate 1 with the holes 20 drilled is placed in a vacuum atmosphere in the vacuum chamber 8, and ultrasonic vibrations F1 and F2 are applied to the substrate (wafer) 1, The molten metal material is filled into the holes 20 using the melt flow pressure and diffused to the surface of the punch pattern 71. Since the hole 20 is a non-through hole, there is no problem in filling the molten metal material.

  Next, as shown in FIGS. 8 and 9, the surface opposite to the side where the circuit pattern 2 is provided is polished by ΔH, the filling metal in the hole 20 is surfaced (FIG. 9), and the through electrode Get 3. Thereafter, as shown in FIG. 10, bumps 60 and 61 are formed so as to overlap the end surface of the through electrode 3 exposed on the surface that has been exposed.

  By the above process, even if the hole 20 has a high aspect ratio, the through electrode 3 having high reliability and high quality can be formed while avoiding the generation of an unfilled portion (void) inside the hole 20.

  In addition, while applying ultrasonic vibration to the substrate (wafer) in a vacuum atmosphere, the molten metal material is filled into the holes 20 using the melt flow pressure and diffused to the surface of the punch pattern 71. Therefore, unlike a method of forming a thin film having a miniaturized multi-layered structure by using a photolithography process and a thin film forming technique, the technical difficulty is low and the capital investment is small. For this reason, the cost of the circuit board itself can be reduced.

  The circuit pattern 2 and the through electrode 3 are preferably made of a material having Sn as a main component and a melting point in the range of 500 ° C. to 130 ° C. According to such a material, the molten metal material is applied to the inside of the hole using the melt flow pressure while giving fine vibration to the substrate 1 even for a fine hole having a hole diameter of 25 μm or less and an aspect ratio of 5 or more. By filling in, high-reliability and high-quality through electrodes 3 and continuous circuit patterns 2 can be formed while avoiding the occurrence of unfilled portions in the interior.

The circuit pattern 2 and the through electrode 3 are more preferably a polycrystal aggregate whose main component is Sn and whose re- solidified crystal is 500 nm or less. As a result, it is possible to form the circuit pattern 2 and the through electrode 3 that have a low electrical resistance and are stable.

<Example>
Next, examples will be described. First, an alloy containing Sn as a main component and containing Bi, In, Cu, Ag, Ga and having a particle size of 30 μm or less and an oxygen content of 300 ppm or less is manufactured, and this powder is used as a through electrode and a circuit wiring material. Prepared as. Specifically, a nanomized alloy powder containing Sn as a main component and containing Bi, In, Cu, Ag, and Ga was used. The particle size of the particles contained in this powder is in the range of 10 μm to 30 μm.

On the other hand, after a resist mask is formed on the substrate by a photolithography process, the resist mask is exposed and exposed to a hole (aspect ratio) having a diameter d of 20 μm and a depth L of 170 μm by chemical reaction etching. 8.5) was formed. Thereafter, a photolithography process was performed again to expose the wafer surface so as to define the wiring shapes of the pads and the circuit pattern. Thereafter, the area surrounding the pad and the circuit pattern was covered with SiO ₂ (insulator).

Next, in a vacuum chamber, the substrate is placed on a holding jig in a vacuum atmosphere with a gas concentration of 10 ppm, and acoustic vibration from 30 Hz to an ultrasonic region of 2000 KHz is gradually performed by a vibrator placed on the holding jig. The metal material was redissolved while adding. The metal material is maintained at a melting temperature of 250 ° C., and at the same time, an acceleration of 0.1 m / S ² or more is applied to the molten metal, and a flow pressure of 0.1 Pa to 1 Pa is generated. The hole was forcibly filled with molten metal. After that, returning to the atmosphere, removing the molten metal on the wafer resist in the atmosphere, then lowering the temperature to solidify the metal and removing the resist, a three-dimensional circuit wiring in which the through electrodes and the circuit pattern were integrated together was obtained. .

  When filling the metal material, the powder was melted on the wafer and impregnated into the micropores by dissolution at a flow rate and vibration. Flow pressure control was adjusted by controlling the operation of the rotating screw or pump. In re-dissolution, heating was performed so that the melting point of the metal was higher by about 50 ° C. Thereafter, by washing away the resist mask, a fine through electrode having a high aspect and a circuit pattern could be collectively formed.

  FIG. 11 is a cross-sectional SEM image of the through electrode of the sample obtained by the above example. From the SEM image, it can be seen that the metal material is filled 100% from the top to the bottom in the 170 μm hole. FIG. 12 is an X-ray X-ray image of part A in FIG. The video of the void was not recognized, and it was confirmed that it was completely filled.

<Comparative Example 1>
A three-dimensional circuit wiring was manufactured by the method described in Patent Document 3 (Japanese Patent Application Laid-Open No. 2002-158191) and confirmed by an SEM image. FIG. 13 is a cross-sectional SEM image of the through electrode of the sample obtained in Comparative Example 1. From the SEM image, it was confirmed that there was an incompletely embedded region (B1) and a void (B2) having a size that can be visually confirmed.

<Comparative Example 2>
A three-dimensional circuit wiring was manufactured by the method described in Patent Document 4 (Japanese Patent Application Laid-Open No. 2003-257891) and confirmed by an SEM image. According to the Tore method, gas is generated because the resin is present only in the through electrode. FIG. 14 is a cross-sectional SEM image of the through electrode of the sample obtained in Comparative Example 2. C1 is an airspace region due to resin gasification, and a void (C2) having a size that can be visually confirmed is also present in the filling portion. Furthermore, it was confirmed that the filling was incomplete due to the air space of C3.

<Comparative Example 3>
A three-dimensional circuit wiring was manufactured by the method described in Patent Document 5 (Japanese Patent Application Laid-Open No. 2006-111896) and confirmed by an SEM image. FIG. 15 is a cross-sectional SEM image of the through electrode of the sample obtained in Comparative Example 3. From the SEM image, a gap region was confirmed at the bottom of the hole, indicating that it was incompletely filled.

  FIG. 16 is an X-ray X-ray image of part D shown in FIG. It was confirmed that there were quite large voids.

  Table 1 shows a summary of the electrical characteristics (insertion loss) and the presence or absence of voids for Example 1 and Comparative Examples 1 to 3 obtained above. Table 1 shows the insertion loss (dB) when a high-frequency current having a frequency of 0.3 GHz to 5 GHz is passed through the through electrode and the presence or absence of voids by observation of the SEM image. The allowable value of insertion loss was (−0.5 dB).

  Referring to Table 1, first, in the case of Comparative Example 1, since the insertion loss reaches −0.24 (dB) at 0.3 GHz and the allowable value −0.5 (dB) at 2 GHz, the allowable value − In the case of 0.5 (dB), use up to 2 GHz is acceptable. Next, in the case of Comparative Example 2, the insertion loss reaches −0.35 (dB) at a frequency of 0.3 GHz and an allowable value −0.5 (dB) at 1 GHz, so that the use up to 1 GHz can be allowed. stay. In the case of Comparative Example 3, the insertion loss reaches −0.04 (dB) at a frequency of 0.3 GHz and reaches an allowable value of −0.5 (dB) at 5 GHz. Therefore, the allowable value can be barely secured up to 5 GHz. . In other words, in a region exceeding 5 GHz, this cannot be handled as long as the allowable value −0.5 (dB) is maintained.

  On the other hand, in the case of Example 1 according to the present invention, the insertion loss is in the range of -0.03 (dB) to -0.05 (dB) in a wide high-frequency region with a frequency of 0.3 to 5 GHz. Excellent high frequency loss characteristics are shown for any of Comparative Examples 1 to 3.

  The presence or absence of voids was confirmed in any of Comparative Examples 1 to 3, whereas in Example 1 according to the present invention, the presence could not be confirmed (attached SEM). See image).

  The present invention has been described in detail with reference to the preferred embodiments. However, the present invention is not limited to these embodiments, and various modifications can be made by those skilled in the art based on the basic technical idea and teachings. It is self-evident that

It is sectional drawing which shows the structure of the circuit board based on this invention roughly. It is an exploded view showing an example of a circuit board according to the present invention. It is a figure which shows a lamination | stacking state (finished product). It is a figure showing roughly an example of an electronic device concerning the present invention. It is a figure explaining the manufacturing method of the circuit board based on this invention. FIG. 6 is a diagram showing a step after the step shown in FIG. 5. It is a figure which shows the process after the process shown in FIG. It is a figure which shows the process after the process shown in FIG. It is a figure which shows the process after the process shown in FIG. FIG. 10 is a diagram showing a step after the step shown in FIG. 9. It is a penetration electrode cross-sectional SEM image of the sample obtained by the Example which concerns on this invention. 12 is an X-ray X-ray image of part A in FIG. 4 is a cross-sectional SEM image of a through electrode of a sample obtained in Comparative Example 1. 6 is a through electrode cross-sectional SEM image of a sample obtained in Comparative Example 2. FIG. 10 is a through electrode cross-sectional SEM image of a sample obtained in Comparative Example 3. FIG. FIG. 16 is an X-ray X-ray image of a D part shown in FIG. 15.

Explanation of symbols

1 Substrate 2 Circuit pattern 3 Through electrode

Claims (6)

A circuit board provided with a three-dimensional circuit with circuit patterns and electrodes on the board,
The circuit pattern is provided on at least one surface of the substrate;
The electrode is filled in a hole extending in the thickness direction from the one surface of the substrate,
The circuit pattern and the electrode are made of the same metal material or alloy material containing Sn as a main component, and are the same and continuous molten and solidified conductor, which is obtained by solidifying molten metal supplied in a molten state. ,
Circuit board.   The circuit board according to claim 1, wherein the circuit pattern and the electrode are a polycrystal aggregate having a solidified crystal of 500 nm or less.   3. The circuit board according to claim 1, wherein there are a plurality of the substrates, and each substrate is sequentially laminated, and at least one of the substrates includes the circuit pattern and the electrodes. Circuit board. An electronic device having a circuit board and a circuit function unit,
The circuit board is described in any one of claims 1 to 3,
The circuit function unit is combined with the circuit board,
Electronic devices.   5. The electronic device according to claim 4, wherein the electronic device is a sensor module, a photoelectric module, a FET, a MOS-FET, a CMOS-FET, a memory cell or an integrated circuit element, or a chip thereof. A method of manufacturing a circuit board according to any one of claims 1 to 3,
Forming a hole in one side of the wafer,
In a vacuum atmosphere, while applying minute vibrations to the wafer, a molten metal of a metal material or alloy material containing Sn as a main component is filled into the hole, and on the one surface of the wafer. Diffuse,
A manufacturing method including a process.