JP4386458B2 - Circuit board, electronic device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a circuit board, an electronic device, and a manufacturing method thereof.

  Examples of the electronic device include various scale integrated circuits, various semiconductor elements, or chips thereof.

  In this type of electronic device, as a method for realizing the three-dimensional circuit arrangement, an LSI is arranged on a circuit board and a multilayer wiring is connected between them. However, in this method, the mounting area increases with the number of LSIs, and the signal delay between LSIs increases due to the increase in wiring length.

  In view of this, there has been proposed a technology that uses a circuit board provided with a circuit pattern on one surface, and provided with a through electrode that is conductive to the circuit pattern and penetrates in the thickness direction.

  As such a circuit board, for example, in Patent Document 1, the liquid viscous material is stencil-printed on the circuit board in a vacuum atmosphere in a method of filling a liquid viscous material into holes or non-holes of a multilayer circuit board. Subsequently, a method of filling a liquid viscous material is disclosed in which the vacuum degree of the vacuum atmosphere is lowered or the vacuum atmosphere is changed to a normal atmospheric pressure to perform differential pressure filling.

  In Patent Document 2, a high-aspect-ratio hole is formed in a circuit board by a photo-excited electrolytic polishing method, and an inner wall of the hole is oxidized to form an oxide film as an insulating layer. A method of forming a through electrode by filling a metal by a metal backfilling method is disclosed.

  Patent Document 3 discloses a method for filling a metal with a fine hole by an atmospheric pressure difference, and Patent Document 4 describes a filling method for filling a fine hole with a conductive paste. Further, Patent Document 5 discloses a method for forming a through electrode in which a metal is directly embedded in a hole before and after a plating embedding process.

  By the way, in this type of electronic device, there are roughly two methods for realizing a structure in which a through electrode is joined to a circuit pattern. The first method is a method in which a through electrode mainly composed of Sn (tin) is formed in advance on a circuit board, and then a circuit pattern is formed. In the second method, a circuit pattern is formed in advance on a circuit board, a through hole is drilled at a position corresponding to the circuit pattern on the circuit board, and then Sn (tin) melted in the through hole. In this method, a through electrode is formed by injecting a metal material such as the above.

  The circuit pattern is formed by applying a thin film forming technique represented by a CVD (Chemical Vapor Deposition Chemical Vapor Deposition) method or a sputtering method. In these thin film formation techniques, the circuit board is exposed to high temperatures. Therefore, when the first technique is applied, the through electrode mainly composed of Sn or the like is melted in this thin film formation process.

  On the other hand, when the second method is applied, since the through electrode is formed after the circuit pattern is formed, it is possible to avoid melting of the through electrode, which is a problem in the first method. Thus, it is superior to the first method.

  However, although the process of forming the circuit pattern on one surface of the circuit board is performed in a vacuum atmosphere, after this process, the circuit board is taken out into the air in the through hole forming process and the molten metal material injecting process. . For this reason, the surface of the circuit pattern existing on the inner bottom surface of the through hole is oxidized.

  When the surface of the circuit pattern to which the through electrode is connected is oxidized, the bonding between the circuit pattern and the through electrode becomes insufficient, and in this type of electronic device, such as poor characteristics and reduced yield, It creates serious problems that cannot be overlooked.

  As means for solving this oxidation problem, a technique is known in which flux is used and the oxide film of the circuit pattern is reduced by utilizing the reducing action of the flux.

However, when this flux reduction technique is applied, the following serious problems occur. That is, when a flux is injected into the through hole together with the molten metal material, a flux gas is generated. In this type of electronic device, the through hole is a very small hole having a hole diameter of, for example, several tens of μm, and the aspect ratio is considerably high. When flux gas is generated in a through-hole of such a shape, the gas escape naturally becomes worse, and voids due to the flux gas are generated around the through-electrode, reducing the cross-sectional area of the through-electrode and reducing the electric resistance. This leads to an increase in connection with a circuit pattern and an increase in junction resistance.
JP 11-298138 A JP 2000-228410 A JP 2002-158191 A JP 2003-257891 A JP 2006-111896 A

  An object of the present invention is to provide a circuit board, an electronic device, and a method for manufacturing the same, in which generation of an oxide film on the surface of a circuit pattern is suppressed.

  Another object of the present invention is to provide a circuit board, an electronic device, and a method of manufacturing the same, in which generation of voids in the through hole is suppressed.

  In order to solve the above-described problems, the present invention discloses a circuit board, an electronic device, and a manufacturing method thereof.

<Circuit board>
The circuit board according to the present invention includes a substrate, a circuit pattern, and a through electrode. The circuit pattern is provided on one surface in the thickness direction of the substrate, the through electrode is filled in a through hole provided in the substrate, and one end is bonded to the circuit pattern. The circuit pattern and the through electrode each have a region containing a noble metal component and are joined to each other by the region.

  According to this structure, the through electrode can be bonded to the circuit pattern without generating an oxide film on the surface of the circuit pattern. The reason is that even if an oxide film is formed on the surface of the circuit pattern, the noble metal component, typically Au (gold), has a precious metal when thermally diffusing into the metal component constituting the circuit pattern. It is assumed that the oxide film is reduced by the catalytic action.

  In addition, since the reducing action on the oxide film is based on the catalytic action of the noble metal and it is not necessary to use a flux for the reduction, generation of voids due to the flux gas can be avoided.

  The circuit board according to the present invention may be composed of a plurality of layers sequentially stacked, and at least one of them may include a combination of the circuit pattern and the through electrode.

<Electronic device>
The electronic device according to the present invention includes a circuit board and a circuit function unit. The circuit board is a circuit board according to the present invention. The circuit function unit is combined with the circuit board.

  Since the electronic device according to the present invention includes the circuit board according to the present invention, the function and effect of the circuit board can be exhibited as they are.

  The electronic device according to the present invention includes a sensor module, a photoelectric module, a FET, a MOS-FET, a CMOS-FET, a memory cell, an FC (Field Complementary) or an integrated circuit element, or a chip thereof.

<Method for manufacturing circuit board or electronic device>
In manufacturing the circuit board according to the present invention, first, a board having a circuit pattern on one side is prepared. Next, a through hole reaching the circuit pattern from the other surface side of the substrate is drilled at a position corresponding to the circuit pattern of the substrate. Next, noble metal fine particles having at least a surface covered with the noble metal are supplied into the through-hole. Next, a molten metal material is injected into the through hole to form a through electrode. Also in the manufacturing method of an electronic device, the manufacturing method according to the present invention is applied when manufacturing the circuit board.

  According to the manufacturing method described above, even if the surface of the circuit pattern appearing on the bottom surface of the through hole is oxidized, the noble metal fine particles are melted in the step of injecting the molten metal material into the through hole to form the through electrode. It melts by receiving thermal energy and diffuses into the circuit pattern and the through electrode. As a result, each of the circuit pattern and the through electrode has a region in which the noble metal component is diffused in the composition, and the circuit pattern and the through electrode are joined to each other by the region in which the noble metal component is diffused. .

  In general, the melting point of noble metal materials is higher than the melting point of the through electrode material. However, by reducing the particle size (nanoization), the melting point is remarkably lowered, and the melting is caused by the heat received from the molten through electrode material. To do.

  Before injecting the molten metal material for the through electrode, the oxide film generated on the surface of the circuit pattern appearing on the bottom surface of the through hole is reduced by the catalytic action of the noble metal fine particles. Therefore, since it is not necessary to use a flux for reduction, generation of voids due to the flux gas can be avoided.

  The composition of the circuit pattern, the through electrode, and the noble metal fine particles is as exemplified above. The noble metal fine particles may be entirely composed of a noble metal, or may have a structure in which a core portion is composed of, for example, Sn (tin) and the surface thereof is covered with a noble metal film.

  Other objects, configurations and advantages of the present invention will be described in more detail with reference to the accompanying drawings. However, the attached drawings are merely examples.

<Circuit board>
Referring to FIG. 1, only a circuit board having a simple configuration is shown, but in reality, a more complicated structure is taken to satisfy the function and structure according to the type of circuit board. In the illustrated circuit board, a three-dimensional circuit is configured on the substrate 1 by the circuit pattern 2 and the through electrode 3. The substrate 1 is composed of various semiconductor substrates, dielectric substrates, insulating substrates, magnetic substrates, or the like. The substrate 1 of the embodiment is a semiconductor substrate such as a silicon wafer. In the case of a semiconductor substrate such as a silicon wafer, an insulating film is provided on both surfaces thereof and on the interface between the through electrode 3 and the substrate 1. The insulating film is a film of a metal oxide, for example, SiO ₂ or Al ₂ O ₃ , and can be formed at a required thickness (depth) at a required position by a known chemical treatment.

  The circuit pattern 2 is a thin film and is provided on at least one surface of the substrate 1. In FIG. 1, a circuit pattern 4 is also provided on the other surface side of the substrate 1. The circuit pattern 2 takes various plane patterns according to the required function. The circuit pattern 2 may be filled with an insulating film as necessary. The circuit pattern 2 is made of a known material, for example, a metal material containing copper (Cu) as a main component. If necessary, indium (In), aluminum (Al), bismuth (Bi), or the like may be contained. The circuit pattern 2 is formed by a thin film forming technique such as a CVD method or a sputtering method. These thin film formation techniques are techniques for forming a vacuum film while heating.

  The through electrode 3 is filled in a through hole 30 extending in the thickness direction from one surface of the substrate 1, and one end thereof is bonded to the circuit pattern 2. The through electrode 3 is made of a known material, for example, a metal material mainly composed of tin (Sn), and contains indium (In), aluminum (Al), bismuth (Bi), or the like as necessary. Also good. Although only one through electrode 3 in the figure is provided for one circuit pattern 2, the present invention is not limited to this. A plurality of through electrodes 3 may be provided for one circuit pattern 2. The depth L of the through-hole 30 and the diameter d of the bottom portion are such that the diameter d is 100 μm or less and the aspect ratio (L / d) is 1 or more, particularly preferably the diameter d is 25 μm or less and the aspect ratio (L / d) is Select 5 or more. Such a through hole 30 can be formed by, for example, laser drilling or chemical treatment.

  The circuit pattern 2 and the through electrode 3 respectively have diffusion regions AL1 and AL2 containing a common noble metal component, and are joined to each other by the diffusion regions AL1 and AL2. The content (diffusion amount) of the noble metal component is highest at the boundary between the diffusion region AL1 and the diffusion region AL2, and diffuses with a concentration gradient that decreases as the distance from the boundary increases. In FIG. 1, the diffusion regions AL1 and AL2 are displayed as regions defined by a one-dot chain line, but this is merely a convenient display for explanation. In practice, there are no clear boundaries.

  The noble metals include gold (Au), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru), and osmium (Os). Among these, it is preferable to include at least one selected from Au (gold), Pt (platinum), or Pd (palladium).

  According to this structure, the through electrode 3 can be bonded to the circuit pattern 2 without generating an oxide film on the surface of the circuit pattern 2. Since the circuit pattern 2 is formed in vacuum by applying the thin film forming technique described above, the circuit pattern 2 is not oxidized in the film forming process, but in the process of forming the through hole 30 and the through electrode 3, the circuit pattern 2 is in the air. As a result, it is oxidized through the through hole 30. Thus, even if an oxide film is formed on the surface of the circuit pattern 2, the noble metal component, typically Au (gold), is thermally diffused into the metal component constituting the circuit pattern 2. The action of reducing the oxide film is caused by the catalytic action of. For this reason, the through electrode 3 can be bonded to the circuit pattern 2 without generating an oxide film on the surface of the circuit pattern 2.

  In addition, the reduction action on the oxide film is based on the catalytic action of the noble metal, and it is not necessary to use a flux for the reduction. Therefore, generation of voids due to the flux gas can be avoided.

  Next, the effects of the present invention will be specifically described with reference to the experimental data of FIGS. 2 is an SEM image of a conventional electronic device as a comparative example, and FIG. 3 is an enlarged view of the SEM image shown in FIG. 4 is an SEM image of the electronic device according to the present invention, FIG. 5 is an enlarged view of the SEM image shown in FIG. 4, and FIG. 6 is an enlarged view of the SEM image shown in FIG. It is.

  The electronic device shown in FIGS. 2 and 3 has a structure in which a circuit pattern 2 mainly composed of Cu is formed on one surface of a silicon substrate 1 and one end of the through electrode 3 is directly bonded to the circuit pattern 2. Yes. In order to reduce the oxide film on the surface of the circuit pattern 2, the through electrode 30 is formed by filling the inside of the through hole 30 with a molten electrode material mainly composed of molten Sn using a flux. .

  As apparent from FIGS. 2 and 3, a considerably large void is generated between the outer periphery of the through electrode 3 and the inner wall surface of the through hole 30. When the flux reduction technique is applied, the oxide film on the surface of the circuit pattern 2 can be reduced, but when a flux is injected into the through hole 30 together with the molten metal material, a flux gas is generated. In this type of electronic device, the through hole 30 is a very small hole having a hole diameter of, for example, several tens of μm, and has an extremely high aspect ratio. When flux gas is generated in the through hole 30 having such a shape, the gas escape naturally becomes worse. For this reason, a void caused by the flux gas is generated around the through electrode 3, the cross sectional area of the through electrode 3 is decreased, the electric resistance is increased, and further, the connection to the circuit pattern 2 is poor and the junction resistance is increased. It invites.

  In contrast, in the electronic device according to the present invention, as illustrated in FIGS. 4 to 6, the outer peripheral surface of the through electrode 3 is in close contact with the inner wall surface of the through hole 30 provided in the substrate 1. There is almost no void between them. A shadow like a void can be seen between the contact surface of the circuit pattern 2 and the through electrode 3, but this is a chip generated when polishing in taking an SEM image. is not.

  FIG. 7 is a diagram showing a result of analyzing the P1 region of FIG. 6 using an EDAX apparatus. The P1 region is a central region of the through electrode 2 and indicates that the through electrode 3 contains Sn as a main component and further contains In, Cu, and Bi.

  FIG. 8 is a diagram showing a result of analyzing the P2 region of FIG. 6 using an EDAX apparatus. The P2 region is set at a position close to the silicon substrate 1 in the through electrode 3. Sn, which is a main component of the through electrode 3, is displayed in the SnL column as 17.42 wt% and 3.29 at%. For Au, 1.24 wt% and 0.14 at% are displayed in the AuL column. As is clear from this, Au diffuses in the through electrode 3 in a minute amount of 1.24 wt% and 0.14 at%.

  When bismuth (Bi) is contained in the through electrode 3, the volume of the bismuth (Bi) expands by about 3 to 3.5% when solidified from the molten state, A gap to be generated between the through-holes 3 filled in the through-holes 30 can be eliminated by the volume expansion of Bi.

  In a system containing Sn, In, Cu and Bi, 50 wt% or more of bismuth (Bi), 30 wt% or less of indium (In), 30 wt% or less of tin (Sn), and in the range of 1 to 5 wt%. When it contains the selected copper (Cu), it has been confirmed that it is extremely effective in preventing the generation of gaps.

  The through electrode 3 comes into close contact with the inner surface of the through hole 30 by a synergistic effect of the effect of preventing the generation of gaps due to the Bi content and the effect of preventing the generation of voids by not using the flux.

  Next, the multilayer circuit board shown in FIGS. 9 and 10 has a structure in which an arbitrary number of circuit boards A1 to A6 are sequentially stacked. A structure including the circuit pattern 2 and the through electrode 3 can be employed in at least one of the layers.

  In the illustrated embodiment, each of the circuit boards A1 to A6 has a structure in which the circuit pattern 2 and the through electrode 3 are provided on the board 1. The circuit pattern 2 is formed on one surface of each of the circuit boards A1 to A6. Some of the circuit patterns 2 are arranged across a plurality of adjacent through electrodes 3.

  The circuit boards A1 to A6 are bonded by an adhesive at the laminated interface. In the drawing, the through electrodes 3 are all connected between the circuit boards A1 to A6, but may not be connected depending on the circuit configuration. Further, bumps (extraction electrodes) 60 to 69 are provided on the outermost circuit boards A1 and A6 as necessary. The multilayer stacked structure shown in FIGS. 9 and 10 is suitable for realizing a circuit board having a complicated three-dimensional circuit.

<Manufacturing method>
Next, a method for manufacturing a circuit board according to the present invention will be described with reference to FIGS. In the method of manufacturing a circuit board according to the present invention, first, as shown in FIG. 11, a substrate 1 (wafer) having a circuit pattern 2 formed on one surface is prepared. The circuit pattern 2 is formed by applying a thin film forming technique such as CVD or sputtering.

  Next, as shown in FIG. 12, after applying a resist 5 on the other surface of the substrate 1, a known photolithography process is performed to form a resist mask 51 having an opening d1 as shown in FIG. To do.

  Subsequently, through holes 30 are formed at predetermined positions in the extraction pattern 52 surrounded by the resist mask 51, for example, by laser irradiation or a chemical reaction etching method, as shown in FIG. The through hole 30 is formed at the bottom having the opening d2 so that the surface of the circuit pattern 2 is exposed. The opening d2 is generally d2 <d1 although it depends on the manufacturing method.

  Next, as shown in FIG. 15, the noble metal fine particles 4 having at least the surface covered with the noble metal are supplied into the through hole 30 by means such as a screen printing method. The noble metal fine particles 4 may be entirely composed of a noble metal, or may have a surface coated with a noble metal using Sn or the like as a nucleus. Specific examples of the noble metal fine particles are as described above. Further, the noble metal fine particles 4 are made of nanoparticles so that the melting point lowering effect due to nano-ization can be utilized. The noble metal fine particles 4 may be in such a small amount that, for example, about 1 to 3 noble metal fine particle layers are formed on the surface of the circuit pattern 2.

  Next, as shown in FIG. 16, a molten metal material is injected into the through hole 30 to form the through electrode 3. In this step, a circuit board is placed in a vacuum atmosphere in a vacuum chamber, and a molten metal material is applied to the substrate 1 (wafer) using the melt flow pressure while applying ultrasonic vibration F1. The inside of 30 is filled. When filling the metal material, the powder is melted on the circuit board 1, and the fine holes are impregnated by melting at a flow rate and vibration. Flow pressure control can be adjusted by controlling the operation of the rotating screw or pump.

  In this molten metal filling step, a noble metal component, typically Au (gold), receives molten heat energy and thermally diffuses into the metal component constituting the circuit pattern 2 to be alloyed. At that time, the action of reducing the oxide film that may exist on the surface of the circuit pattern 2 is caused by the catalytic action of the noble metal. Therefore, the through electrode 3 can be bonded to the circuit pattern 2 without generating an oxide film on the surface of the circuit pattern 2.

  In addition, since the reducing action on the oxide film is based on the catalytic action of the noble metal and it is not necessary to use a flux for the reduction, generation of voids due to the flux gas can be avoided.

  Moreover, the molten metal material may be filled into the through hole 30 using the melt flow pressure while applying ultrasonic vibration to the substrate 1 (wafer) in a vacuum atmosphere. Unlike a method of forming a thin film having a miniaturized multi-layered structure using a thin film forming technique or the like, the technical difficulty is low and the capital investment is small. For this reason, it is possible to reduce the cost.

<Electronic device>
The electronic device according to the present invention includes a sensor module, a photoelectric module, a unipolar transistor, a MOS FET, a CMOS FET, a memory cell, an FC (Field Complementary) chip, or an integrated circuit component (IC) thereof, or various scales. In general, most LSIs having an electronic circuit as a functional element can be included.

  In particular, an integrated circuit LSI using the substrate according to the present invention as an interposer is suitable as a representative example. In the present invention, the term “integrated circuit LSI” includes all of small scale integrated circuits, medium scale integrated circuits, large scale integrated circuits, ultra large scale integrated circuits VLSI, ULSI, and the like.

  Referring to FIG. 18, a first integrated circuit LSI1 as a circuit function unit is mounted on one surface of a first interposer InT1 using a circuit board according to the present invention, and one surface of the first integrated circuit LSI1. Above, the second interposer InT2 using the substrate according to the present invention is mounted, and the second integrated circuit LSI2 is mounted on one surface of the second interposer InT2.

  However, the number of the first and second interposers InT1, InT2, the internal wiring, the thickness, the shape, and the like are arbitrary. The same applies to the first and second integrated circuits LSI1 and LSI2.

Signals from the first integrated circuit LSI1 to the upper second integrated circuit LSI2 are transmitted to the second interposer InT2 through connection portions called bumps. Inside the second Lee Ntapoza INT2, through internal wirings 2 and 3, and transmitted to the bumps 65 to 69 of the object, through the bumps 65 to 69, transmitting the signal to the second integrated circuit LSI 2. Signal transmission to the lower first integrated circuit LSI1 can be similarly performed.

  As shown in FIG. 18, the circuit board according to the present invention is the first and second interposers InT1 and InT2, and the first and second integrated circuits LSI1 and LSI2 are overlapped on this to operate as one chip. As a result, it is possible to realize ultra-small packaging of electronic circuits that are the heart of IT equipment and high-speed signal transmission between the first and second integrated circuits LSI1 and LSI2.

  In addition, the second interposer InT2 is arranged between the stacked layers of the first and second integrated circuits LSI1 and LSI2, and enables high-density and high-speed signal transmission.

  In addition, the internal clock of the integrated circuit is as fast as several GHz in recent CPUs, whereas the signal transmission clock to the outside of the chip is several hundred MHz, so wiring delay is a big problem. By using the circuit board according to the present invention as the first and second interposers InT1 and InT2, the wiring length can be minimized and the problem caused by the wiring delay can be solved.

  Furthermore, the delay in the buffer circuit for outputting a signal to the outside and the power consumption for driving cannot be ignored. However, the consumption of the substrate according to the present invention can be increased by using the first and second interposers InT1 and InT2. Electric power can also be reduced.

  If a CPU, a cache main memory, an IO chip, and the like are stacked on one chip, an ultra-compact and high-performance microcomputer system can be realized.

  In FIG. 18, the circuit board according to the present invention is configured to be independent from the first and second integrated circuits LSI1 and LSI2, but the internal structure of the first and second integrated circuits LSI1 and LSI2, in particular, The present invention can also be applied to the local wiring portion. Further, the present invention can be applied not only to the active circuit element but also to the internal wiring structure of the passive circuit element.

  The present invention has been described in detail with reference to the preferred embodiments. However, the present invention is not limited to these embodiments, and various modifications can be made by those skilled in the art based on the basic technical idea and teachings. It is self-evident that

Sectional drawing which shows roughly the structure of the circuit board based on this invention, It is a SEM (Scanning Electron Microscope) image of the conventional circuit board as a comparative example. It is a figure which expands and shows the SEM image shown in FIG. It is a SEM image of the circuit board concerning the present invention. It is a figure which expands and shows the SEM image shown in FIG. It is a figure which expands and shows the SEM image shown in FIG. It is a figure which shows the result of having analyzed P1 area | region of FIG. 6 using the EDAX (energy dispersive X-ray analysis) apparatus. It is a figure which shows the result of having analyzed P2 area | region of FIG. 6 with the EDAX apparatus. It is an exploded view in other embodiments of a circuit board concerning the present invention. FIG. 10 is a cross-sectional view schematically showing the structure of the circuit board shown in FIG. 9. It is a figure which shows the manufacturing process of the circuit board based on this invention. FIG. 12 is a diagram showing a step after the step shown in FIG. 11. FIG. 13 is a diagram showing a step after the step shown in FIG. 12. FIG. 14 is a diagram showing a step after the step shown in FIG. 13. It is a figure which shows the process after the process shown in FIG. FIG. 16 is a diagram showing a step after the step shown in FIG. 15. FIG. 17 is a diagram showing a step after the step shown in FIG. 16. 1 is a cross-sectional view schematically showing an electronic device according to the present invention.

Explanation of symbols

1 Substrate 2 Circuit pattern 3 Through electrode 30 Through hole AL1 Diffusion region AL2 Diffusion region

Claims (8)

A circuit board including a substrate, a circuit pattern, a through electrode, and a diffusion region,
The circuit pattern is provided on one surface of the substrate in the thickness direction,
The through electrode has Sn (tin) as a main component, is filled in a through hole provided in the substrate, and one end is bonded to the circuit pattern,
The diffusion region is a region that joins both the circuit pattern and the through electrode by diffusion and alloying of a noble metal component,
Circuit board.   2. The circuit board according to claim 1, wherein the noble metal component includes at least one selected from Au (gold), Pt (platinum), and Pd (palladium). A circuit board including a plurality of layers stacked sequentially, at least one of which includes the circuit pattern according to claim 1, the through electrode, and the diffusion region . Circuit board.   4. The circuit board according to claim 1, wherein the through electrode contains bismuth (Bi). An electronic device having a circuit board and an integrated circuit LSI ,
The circuit board is described in any one of claims 1 to 4 ,
The integrated circuit LSI is an electronic device laminated with the circuit board. 6. The electronic device according to claim 5, wherein the electronic device is a sensor module, a photoelectric module, a FET, a MOS-FET, a CMOS-FET, a memory cell or an integrated circuit element, or a chip thereof. A circuit board manufacturing method comprising:
Prepare a substrate with a circuit pattern on one side,
At a position corresponding to the circuit pattern of the substrate, a through hole reaching the circuit pattern from the other surface side of the substrate is drilled,
Said the through hole, the noble metal appears at least on the surface, to supply the fine noble metal particles having a particle size is nanoized to form a noble metal particle layer on the bottom of the through hole,
Next, molten metal containing Sn as a main component is injected into the through hole to form a through electrode filling the through hole, and the noble metal fine particles are thermally diffused in the circuit pattern and the through electrode. Create an alloying region,
A manufacturing method including a process.   The manufacturing method according to claim 7, wherein the noble metal fine particles include at least one selected from Au (gold), Pt (platinum), and Pd (palladium).