JPH11330257A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a method for manufacturing it, wherein fraction defective is decreased when a semiconductor device which allows high-density mounting is manufactured, with simplified process. SOLUTION: With a plurality of different kinds of semiconductor chips 1 (processor chip 1a and memory chip 1b) formed on a semiconductor wafer 2, a soundness inspection is performed with each semiconductor chip 1, and each semiconductor chip 1 which is determined to be sound is cut out of the semiconductor wafer 2 as a set where adjoining processor chip 1a and memory chip 1b are connected together, thus a semiconductor device is manufactured. After that, semiconductor device is mounted on a substrate 4 to manufacture a semiconductor module 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device that can be mounted on a memory substrate, a motherboard, or the like, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Generally, semiconductor chips such as memory chips cut from a semiconductor wafer are mounted on a printed circuit board or the like in a packaged state. However, since the external dimensions of the package are considerably larger than the size of various semiconductor chips themselves, there are certain restrictions on the number of packages that can be mounted on a printed circuit board or the like.

On the other hand, recently, a multi-chip module (MCM) in which a plurality of semiconductor chips are mounted on a substrate has been spreading. By using this multi-chip module, the mounting area can be reduced and the weight can be reduced.
Higher speed and higher reliability can be ensured.

[0004]

By the way, in the above-mentioned multi-chip module capable of high-density mounting,
Since a plurality of semiconductor chips are mounted on one substrate, the failure rate of each semiconductor chip is accumulated and the failure rate of the entire module increases. For example, when two semiconductor chips are mounted on one module substrate, even if one semiconductor chip is defective, the entire module will be defective. Therefore, it is necessary to perform a repair operation for replacing a defective semiconductor chip, or to take measures such as discarding the entire module as a defective product, resulting in a low yield and a lot of waste. Further, when a plurality of semiconductor chips are mounted on one substrate, each semiconductor chip is mounted on the substrate one by one, so that the manufacturing process is complicated.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to reduce a defect rate in manufacturing a semiconductor device capable of high-density mounting, and to further reduce the number of processes. An object of the present invention is to provide a semiconductor device which can be simplified and a manufacturing method thereof.

[0006]

In order to solve the above-mentioned problems, according to the present invention, after a plurality of different kinds of semiconductor chips are formed on a semiconductor wafer, or wiring or resin sealing is performed on these semiconductor chips. After forming the terminals,
A semiconductor device is formed by performing a quality inspection of each semiconductor chip and dividing the semiconductor chip into predetermined plural units according to the result. Since the semiconductor chips are separated according to the results of the pass / fail inspection, when a semiconductor device composed of a plurality of semiconductor chips and capable of high-density mounting is manufactured, some of the semiconductor chips in the semiconductor devices are defective. Since the semiconductor device is a non-defective product, the entire semiconductor device does not become defective, and the defect rate in manufacturing the semiconductor device can be reduced. Further, since a semiconductor device including a plurality of semiconductor chips can be used in a subsequent step, the subsequent steps can be simplified as compared with a case where a plurality of semiconductor devices including a single semiconductor chip are used in combination. Can be.

In particular, by performing a mounting process including wiring, resin sealing, and terminal formation on each semiconductor chip formed on the semiconductor wafer, the mounting process is performed after each semiconductor chip is individually cut. The process can be further simplified as compared with the case.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment A semiconductor device according to a first embodiment of the present invention will be specifically described below with reference to the drawings. FIG. 1 is a diagram showing a manufacturing process of the semiconductor device of the present embodiment.

First, as shown in FIGS. 1 (a) and 1 (b), a semiconductor wafer 2 which is a thin silicon single crystal, for example, is used.
To form two types of semiconductor chips 1 on the semiconductor wafer 2 (first step). For example, one of the two types of semiconductor chips 1 is a processor chip 1a, and the other is a memory chip 1b. A blank area surrounded by a dotted line in FIG. 1B indicates the processor chip 1a, and a hatched area indicates the memory chip 1b. As shown in FIG. 1B, when a plurality of semiconductor chips 1 are formed on a semiconductor wafer 2, a processor chip 1a and a memory chip 1b are formed.
Are arranged so as to be adjacent to each other on all sides.

FIG. 2 is a view schematically showing a semiconductor chip 1 formed on a semiconductor wafer 2. As shown in FIG.
The semiconductor chip 1 includes a semiconductor wafer 2 having a predetermined size,
And a plurality of chip pads 3 formed on the surface of the semiconductor wafer 2. The chip pad 3
This is a connection terminal for making an electrical connection with a substrate on which the semiconductor chip 1 is mounted. FIG. 2 shows the semiconductor chip 1
Although the case where the chip pads 3 are formed in a line at substantially the center of FIG. 1 is shown, the number and arrangement position of the chip pads 3 are appropriately changed depending on the type of the semiconductor chip 1.

With the plurality of semiconductor chips 1 formed on the semiconductor wafer 2 in this manner, next, a pass / fail inspection is performed on each of the semiconductor chips 1 (second step).
For example, various functional tests are performed by pressing a test probe against a chip pad 3 formed on each semiconductor chip 1 to make it electrically contact. Each semiconductor chip 1
By performing the pass / fail inspection of the entire semiconductor wafer 2 as a unit, that is, by conducting pass / fail inspection of a plurality of semiconductor chips 1 formed on the semiconductor wafer 2 at one time.
The aim is to improve inspection efficiency.

Next, based on the results of the pass / fail inspection in the second step, as shown in FIG. 1C, each semiconductor chip 1 determined to be non-defective is replaced with one adjacent processor chip 1a. 2 combining one memory chip 1b
The individual pieces are cut as one set (third step).

FIG. 3 is a diagram showing an example of a method for separating a plurality of semiconductor chips 1 formed on a semiconductor wafer 2. FIG. 3A is a diagram showing a result of a pass / fail inspection of each semiconductor chip 1 formed on the semiconductor wafer 2 in the above-described second step. , And the crosses indicate one semiconductor chip 1 determined to be defective. FIG. 3 (b)
FIG. 4A is a diagram illustrating how the semiconductor chip 1 determined to be non-defective in FIG. 3A is separated, and a range surrounded by a solid line indicates a unit of separation. As described above, each semiconductor chip 1 includes one processor chip 1a.
And one memory chip 1b are combined and cut. Therefore, as shown in FIG. 3B, the processor chip 1a and the memory chip 1b are separated by devising and combining the adjoining processor chip 1a and the memory chip 1b determined to be non-defective. A semiconductor device in a state of being connected is manufactured.

Next, as shown in FIG. 1D, the separated processor chip 1a and memory chip 1b
To finally complete the semiconductor module 10 (fourth step). As a mounting method on the substrate 4, the chip pads 3 formed on the semiconductor chip 1 are connected to electrodes (not shown) formed on the substrate 4 using bonding wires.

As described above, a plurality of two types of semiconductor chips 1 are formed on the semiconductor wafer 2 and these semiconductor chips 1 are formed.
Of these, the semiconductor module 10 is manufactured by combining and cutting only those which are determined to be non-defective by the pass / fail inspection. One of the semiconductor chips 1 included in the semiconductor module 10 is defective, and the semiconductor module 10 The entire product does not become defective, and the defective rate at the time of manufacturing the semiconductor module 10 can be reduced.

In particular, in this embodiment, the processor chip 1a and the memory chip 1b are cut out in a connected state, but the combination of the adjacent processor chip 1a and the memory chip 1b is freely determined based on the result of the pass / fail test. be able to. Therefore, each processor chip 1a can be combined with another adjacent memory chip 1b even if one adjacent memory chip 1b is defective. Similarly, each of the memory chips 1b can be used even if one adjacent processor chip 1a is defective.
It can be combined with another adjacent processor chip ab. For this reason, by devising the combination of the processor chip 1a and the memory chip 1b, it is possible to manufacture more semiconductor devices as a combination of the two semiconductor chips 1 from one semiconductor wafer 2.

The semiconductor module 10 has a processor chip 1a and a memory chip 1b formed on the semiconductor wafer 2 cut out together and mounted. That is, since the plurality of semiconductor chips 1 are mounted in a state of being connected to each other, a processor module 1a and a memory chip 1b are cut out from the semiconductor wafer 2 one by one, and they are mounted at an interval to form a semiconductor module. In comparison with the above, it is possible to reduce the size of components by high-density mounting. Further, since a plurality of semiconductor chips 1 can be mounted at one time, the manufacturing process can be simplified.

(Second Embodiment) Next, a semiconductor module according to a second embodiment of the present invention will be described. The semiconductor module of the present embodiment is manufactured by a chip size package (CSP) mounting technology. FIG. 4 is a diagram illustrating a manufacturing process of the semiconductor module of the present embodiment.

First, as shown in FIGS. 4A and 4B, a semiconductor wafer 12 is introduced.
A plurality of semiconductor chips 11 (for example, processor chip 1
1a and the memory chip 11b) are formed (first step). A blank area surrounded by a dotted line in FIG. 4B indicates the processor chip 11a, and a hatched area indicates the memory chip 11b. When a plurality of semiconductor chips 11 are formed on the semiconductor wafer 12, the processor chips 11a and the memory chips 11b are formed so as to be adjacent to each other on all sides. Next, as shown in FIG. 4C, CSP mounting for forming terminals after performing wiring and resin sealing is performed on the entire semiconductor wafer 12 on which the plurality of semiconductor chips 11 are formed (FIG. 4C). Second step).

FIG. 5 shows a semiconductor chip 1 mounted with CSP.
1 is an enlarged sectional view of FIG. As shown in FIG. 5, the CSP-mounted semiconductor chip 11 includes a semiconductor wafer 12, a wiring pattern 13, a via post 14, a barrier metal 15,
It is configured to include the resin layer 16 and the solder balls 17.

The wiring pattern 13 is formed by processing a metal thin film formed on the surface of the semiconductor wafer 12 with a resist, and then performing an electrolytic plating process. The via post 14 is connected to the wiring pattern 13, and a barrier metal 15 is formed on the top of the via post 14. Resin layer 16
Seals the surface of the semiconductor wafer 12. Resin layer 1
Numeral 6 has a thickness substantially equal to the height of the via post 14, so that the barrier metal 15 is exposed to the outside when sealed with a resin. The solder balls 17 are connection terminals for making an electrical connection with a substrate on which the semiconductor chip 11 is mounted.

With the plurality of semiconductor chips 11 thus formed on the semiconductor wafer 12 mounted on the CSP, a pass / fail inspection of each semiconductor chip 11 is then performed (third test).
Process). For example, various functional tests are performed by pressing an inspection probe against a solder ball 17 formed corresponding to each semiconductor chip 11 to make it electrically contact. By performing the pass / fail inspection of the semiconductor chip 11 in units of the entire semiconductor wafer 12, that is, by passing the pass / fail inspection of the plurality of semiconductor chips 11 formed on the semiconductor wafer 12 at once, the inspection efficiency is improved. I have.

Next, based on the result of the pass / fail inspection in the third step, as shown in FIG. 4D, each of the semiconductor chips 11 after mounting the CSP determined to be non-defective is replaced with a processor chip 11a and a memory chip 11a. The semiconductor module 20 is finally completed by dividing the combination of the semiconductor device 11b and the semiconductor device 11b into one set of semiconductor devices (fourth step). As a specific dividing method, the dividing method shown in FIG. 3 in the first embodiment described above is applied.

As described above, after a plurality of different types of semiconductor chips 11 are formed on the semiconductor wafer 12, CSP mounting is performed, and among the semiconductor chips 11 after CSP mounting, those which are determined to be non-defective by the quality inspection. Since only the semiconductor module 20 as a semiconductor device is manufactured by cutting only the semiconductor chip 20, the two semiconductor chips 11 (the processor chip 11a and the memory chip 1
Since at least one of 1b) is defective, the entire semiconductor module 20 does not become defective.
The defective rate when manufacturing the semiconductor module 20 can be reduced.

Further, the semiconductor module 20 includes a processor chip 11a and a memory chip 1 from the semiconductor wafer 12.
1b are cut out as a set. For this reason, compared with the case where the processor chip 11a and the memory chip 11b are separately cut out from the semiconductor wafer 12 and then mounted with an interval between them to form a semiconductor module, miniaturization of components by high-density mounting is achieved. Becomes possible. In particular, since the CSP mounting is performed, the mounting area is minimized. Further, since each semiconductor chip 11 is cut out based on the pass / fail pattern,
The multi-cavity semiconductor module 20 can be manufactured efficiently.

The present invention is not limited to the above embodiment, and various modifications can be made within the scope of the present invention. For example, the corresponding terminals of the processor chip 1a and the memory chip 1b included in the semiconductor wafer 2 of the first embodiment described above may be connected to each other by wiring. For example, a common power supply voltage is applied to each power supply terminal of the processor chip 1a and the memory chip 1b, and a common operation clock signal is input to each clock terminal. In a semiconductor device in which terminals to which the same voltage is applied or signals to which the same signal is input are connected when forming each semiconductor chip 1 and the two semiconductor chips 1 are cut out in a connected state. A common voltage is applied to one of the two semiconductor chips 1 or a common signal is input. As described above, by mutually interconnecting the insides of the semiconductor chips 1, the amount of wiring between the plurality of semiconductor chips 1 and the substrate 4 on which the semiconductor chips 1 are mounted can be reduced, and the mounting process can be simplified. become.

However, it is not known how to combine and cut out adjacent semiconductor chips 1 until a pass / fail inspection is performed. Therefore, as shown in FIG. 6, corresponding terminals of all adjacent semiconductor chips 1 are connected to each other. It is preferable to wire them mutually. Further, as an example, the case where the power supply terminal and the clock terminal are connected to each other has been described, but other terminals may be connected to each other.

In the above-described first embodiment, a semiconductor device in which two semiconductor chips 1 are connected is manufactured and further mounted on a substrate 4 to form a semiconductor module 10. A semiconductor device composed of the individual semiconductor chips 1 may be directly mounted on a motherboard or the like of a personal computer.

Further, in each of the above-described embodiments, a semiconductor device is formed by combining two different kinds of semiconductor chips 1 and 11, but more (for example, four) different kinds of semiconductor chips 1 and 11 are formed. They may be combined. In this case, the types of all the semiconductor chips do not necessarily need to be different, and at least two types of semiconductor chips are combined. The combination of different types of semiconductor chips includes a case where different types of memory chips (such as a DRAM and a flash memory) are combined, and a case where the same DRAM is combined with different bit configurations and capacities.

[0030]

As described above, according to the present invention, a semiconductor chip is divided into a plurality of units in accordance with a result of a pass / fail inspection, so that a high-density mounting constituted by a plurality of semiconductor chips is performed. When manufacturing a semiconductor device that can be used, the semiconductor device as a whole is not defective because some of the semiconductor chips in it are defective, reducing the defect rate when manufacturing semiconductor devices. can do. Further, since a semiconductor device including a plurality of semiconductor chips can be used in a subsequent step, the subsequent steps can be simplified as compared with a case where a plurality of semiconductor devices including a single semiconductor chip are used in combination. Can be.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a manufacturing process of a semiconductor module according to a first embodiment.

FIG. 2 is a view schematically showing a semiconductor chip formed on a semiconductor wafer.

FIG. 3 is a diagram illustrating an example of a method for separating semiconductor chips formed on a semiconductor wafer.

FIG. 4 is a view illustrating a manufacturing process of the semiconductor module according to the second embodiment;

FIG. 5 is an enlarged sectional view of a semiconductor chip mounted with CSP.

FIG. 6 is a diagram showing a connection state between respective semiconductor chips connected to each other;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1, 11 Semiconductor chip 1a, 11a Processor chip 1b, 11b Memory chip 2, 12 Semiconductor wafer 3 Chip pad 4 Substrate 10 Semiconductor module 13 Wiring pattern 14 Via post 15 Barrier metal 16 Resin layer 17 Solder ball

Claims (4)

[Claims] 2. A semiconductor device comprising: forming a plurality of different types of semiconductor chips on a semiconductor wafer; and forming the plurality of semiconductor chips by dividing the plurality of semiconductor chips into a plurality of units in accordance with a result of a pass / fail inspection of each semiconductor chip. Semiconductor device. 2. After performing wiring, resin sealing, and terminal formation on a plurality of different types of semiconductor chips formed on a semiconductor wafer, a predetermined plurality of semiconductor chips are formed according to the result of a pass / fail inspection of each semiconductor chip. A semiconductor device formed by cutting the semiconductor chip as a unit. 3. A first step of forming a plurality of different types of semiconductor chips on a semiconductor wafer; a second step of performing a pass / fail inspection of each of the plurality of semiconductor chips formed on the semiconductor wafer; A third step of dividing the semiconductor chip into a plurality of units based on the result of the pass / fail inspection. 4. A first step of forming a plurality of different types of semiconductor chips on a semiconductor wafer, and performing wiring, resin sealing, and terminal formation on the plurality of semiconductor chips formed on the semiconductor wafer. A second step, and using the terminal formed in the second step,
A third step of performing a pass / fail inspection of each of the plurality of semiconductor chips formed on the semiconductor wafer; and a fourth step of separating the semiconductor chips into a plurality of units based on a result of the pass / fail inspection. A method for manufacturing a semiconductor device, comprising: