JP3842272B2 - Interposer, semiconductor chip mount sub-board and semiconductor package - Google Patents

Interposer, semiconductor chip mount sub-board and semiconductor package Download PDF

Info

Publication number
JP3842272B2
JP3842272B2 JP2004164489A JP2004164489A JP3842272B2 JP 3842272 B2 JP3842272 B2 JP 3842272B2 JP 2004164489 A JP2004164489 A JP 2004164489A JP 2004164489 A JP2004164489 A JP 2004164489A JP 3842272 B2 JP3842272 B2 JP 3842272B2
Authority
JP
Japan
Prior art keywords
semiconductor
electrode
chip
mounting
bare chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2004164489A
Other languages
Japanese (ja)
Other versions
JP2005347470A (en
Inventor
盛義 中島
和男 小林
夏夫 味香
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Genusion Inc
Original Assignee
Genusion Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Genusion Inc filed Critical Genusion Inc
Priority to JP2004164489A priority Critical patent/JP3842272B2/en
Publication of JP2005347470A publication Critical patent/JP2005347470A/en
Application granted granted Critical
Publication of JP3842272B2 publication Critical patent/JP3842272B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015Shape
    • H01L2924/10155Shape being other than a cuboid
    • H01L2924/10158Shape being other than a cuboid at the passive surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

この発明は、半導体装置のパッケージ構造に関するものである。 The present invention relates to a package structure of a semiconductor device.

移動体通信システムの端末装置(携帯電話機)などのように半導体装置を用いた電子機器において、その小型軽量化を図る上で半導体装置の高集積化を如何に高めるかは常に重要である。これまで半導体回路の微細化が順調に進んでいたときには可能な限りの回路を1チップ化して、実装面積の縮小化、高速化、消費電力の低減化というメリットを生かしてきた。ところが、半導体回路の微細化に伴う製造コストの急騰と設計開発期間の長期化という問題が顕在化してきた。 In an electronic device using a semiconductor device such as a terminal device (mobile phone) of a mobile communication system, it is always important how to increase the integration of the semiconductor device in order to reduce the size and weight. Up to now, when miniaturization of semiconductor circuits has been progressing smoothly, as many circuits as possible are made into one chip, and the advantages of reducing the mounting area, increasing the speed, and reducing the power consumption have been utilized. However, problems such as a rapid increase in manufacturing cost and a prolonged design and development period due to miniaturization of semiconductor circuits have become apparent.

そこで、複数の半導体チップを3次元実装するSIP(System in Package)技術が注目されている。例えば図13に示すように、パッケージ基板10の上に半導体ベアチップ30をマウントし、この半導体ベアチップ30の上にさらに別の半導体ベアチップ31をマウントし、これらの半導体ベアチップ30、31とパッケージ基板10との間をワイヤ60でワイヤボンディングしている(非特許文献1参照)。
日経エレクトロニクス2002,2−11 no.815 p108 「第1部 チップがダメならパッケージがある」
Therefore, SIP (System in Package) technology that three-dimensionally mounts a plurality of semiconductor chips has attracted attention. For example, as shown in FIG. 13, a semiconductor bare chip 30 is mounted on a package substrate 10, and another semiconductor bare chip 31 is mounted on the semiconductor bare chip 30, and these semiconductor bare chips 30, 31 and the package substrate 10 are A wire 60 is used for wire bonding (see Non-Patent Document 1).
Nikkei Electronics 2002, 2-11 no. 815 p108 “Part 1 If there is no chip, there is a package”

上記のように複数の半導体チップを1つのパッケージに納めたSIPの良品率は、各半導体チップの良品率の相乗値となり、たとえば、良品率が8割の半導体チップを3個納めたSIPの場合、その良品率はほぼ5割(=0.8×0.8×0.8)に低下してしまうという問題点があった。特に、DRAMなどの低価格のチップの良品率のほうが、高価なCPUなどのロジック半導体チップの良品率よりも低いため、低価格の半導体チップの不良のために高価な半導体チップが無駄になってしまうという問題点があった。したがって、SIPに実装する半導体チップは、予め検査をすませて良品であることが確認された半導体チップ(検査済み良品チップ、KGD:Known−Good−Die)であることが強く望まれる。 The non-defective product rate of SIP in which a plurality of semiconductor chips are contained in one package as described above is a synergistic value of the good product rate of each semiconductor chip. For example, in the case of SIP in which three semiconductor chips with a good product rate of 80% are contained. The non-defective product rate is reduced to almost 50% (= 0.8 × 0.8 × 0.8). In particular, since the yield rate of low-priced chips such as DRAM is lower than the yield rate of logic semiconductor chips such as expensive CPUs, expensive semiconductor chips are wasted due to defects in low-priced semiconductor chips. There was a problem of end. Therefore, it is strongly desired that the semiconductor chip to be mounted on the SIP is a semiconductor chip (inspected good chip, KGD: Known-Good-Die) that has been verified in advance to be a good product.

次に、KGDを取得する方法を説明する。まず、半導体ウェハの状態で個々の半導体チップに所定のプローブ検査を行う。半導体ウェハをダイシング(切断)して半導体チップの個片に分離する。プローブ検査の結果に基づいて半導体チップを選別し、これにより、良品の半導体チップのみをバーンイン検査(以下、BTとする)等のスクリーニング検査を行う。この際、良品の半導体チップのみをBT用のチップトレイまたはキャリアソケットに収容し、KGD専用治具および専用装置を用いてチップ状態でのBTを行い、さらに、選別した後、BT用のチップトレイもしくは、キャリアソケットから半導体チップを取り出し、良品の半導体チップを出荷用のトレイに移し換えて梱包及び出荷を行っている。半導体チップ個片(ベアチップ)は、非常に薄く形成されているため、割れやすく、選別試験に使用されるソケットやプローブ、テスターの操作には非常に繊細な操作が要求されていた。 Next, a method for acquiring KGD will be described. First, a predetermined probe inspection is performed on each semiconductor chip in the state of the semiconductor wafer. The semiconductor wafer is diced (cut) and separated into semiconductor chip pieces. Based on the result of the probe inspection, the semiconductor chips are selected, and only a good semiconductor chip is subjected to a screening inspection such as burn-in inspection (hereinafter referred to as BT). At this time, only good semiconductor chips are accommodated in a chip tray or carrier socket for BT, BT in a chip state is performed using a dedicated jig for KGD and a dedicated device, and after further sorting, a chip tray for BT Alternatively, the semiconductor chip is taken out from the carrier socket, and the non-defective semiconductor chip is transferred to a shipping tray for packing and shipping. Since the semiconductor chip piece (bare chip) is formed very thin, it is easy to break, and a very delicate operation is required for the operation of the socket, probe, and tester used in the sorting test.

この問題を解決するために、たとえば特開2002−40095に開示されているような方法がある。 In order to solve this problem, for example, there is a method as disclosed in JP-A-2002-40095.

特開2002−40095に開示されている半導体装置は、半導体チップを樹脂封止してなる第一の樹脂封止パッケージの表面に形成された電極が前記半導体チップの電極に接続されると共に実装対象に接続される実装用領域と試験用機器を接続する試験用領域とが設けられてなることを特徴とする。特開2002−40095に開示されている半導体装置をSIPに適用した場合の例を図14に示し、これを参照して以下に説明する。 In a semiconductor device disclosed in Japanese Patent Laid-Open No. 2002-40095, an electrode formed on the surface of a first resin-sealed package formed by resin-sealing a semiconductor chip is connected to the electrode of the semiconductor chip and mounted. And a test area for connecting a test device. An example in which the semiconductor device disclosed in Japanese Patent Laid-Open No. 2002-40095 is applied to SIP is shown in FIG. 14 and will be described below with reference to this.

図14に示すように、半導体パッケージ20は、パッケージ基板10に実装される際に、パッケージ基板10上の電極と接続されるリードフレームに半導体パッケージ21及び半導体パッケージ22が搭載されると共に、封止樹脂80によって樹脂封止される。
このとき、半導体パッケージ21及び半導体パッケージ22は、それぞれ半導体ベアチップ30及び半導体ベアチップ31を内蔵し、かつ封止樹脂81によってそれぞれ樹脂封止されている。但し、特開2002−40095に開示されている半導体装置をSIPに適用するにあたっては、半導体パッケージ21の電極40は、半導体パッケージ21を載置している半導体パッケージ22の電極41にワイヤ60によって接続されている。また、半導体パッケージ22の電極41とリードフレームとがワイヤ61によって接続されている。このように、特開2002−40095に開示されている樹脂封止パッケージ(半導体パッケージ21および半導体パッケージ22)は従来のベアチップに比べて、樹脂封止されているがゆえに、その取り扱いが簡単になり、選別試験に使用されるソケットやプローブ、テスターの操作に要求される繊細度は減る、という効果がある。
As shown in FIG. 14, when the semiconductor package 20 is mounted on the package substrate 10, the semiconductor package 21 and the semiconductor package 22 are mounted on a lead frame connected to an electrode on the package substrate 10 and sealed. The resin 80 is sealed with resin.
At this time, the semiconductor package 21 and the semiconductor package 22 incorporate the semiconductor bare chip 30 and the semiconductor bare chip 31, respectively, and are sealed with a sealing resin 81, respectively. However, when the semiconductor device disclosed in Japanese Patent Laid-Open No. 2002-40095 is applied to SIP, the electrode 40 of the semiconductor package 21 is connected to the electrode 41 of the semiconductor package 22 on which the semiconductor package 21 is mounted by the wire 60. Has been. Further, the electrode 41 of the semiconductor package 22 and the lead frame are connected by a wire 61. As described above, the resin-sealed package (semiconductor package 21 and semiconductor package 22) disclosed in Japanese Patent Laid-Open No. 2002-40095 is easier to handle because it is resin-sealed than the conventional bare chip. There is an effect that the fineness required for the operation of the socket, probe, and tester used in the screening test is reduced.

さらに、特開2002−40095では、電極を試験用領域と実装用領域とに分けることにより、実装時に選別試験で傷がついた前記電極を使用することがなくなる構成をとっている。この試験用電極と実装用電極に対しては、以下のような要求がある。 Further, Japanese Patent Application Laid-Open No. 2002-40095 has a configuration in which the electrodes that are damaged in the sorting test at the time of mounting are not used by dividing the electrodes into a test region and a mounting region. The test electrode and the mounting electrode have the following requirements.

まず、試験用電極に対しては、その電極ピッチを例えば、BGAタイプのパッケージでは、0.8mm程度にする。このレベルの電極ピッチが実現できれば、選別試験に使用されるソケットやプローブ、テスターの操作に要求される繊細度はCSPを測定するレベルでよくなる。一方、実装用電極に対しては、その電極ピッチを通常のベアチップの電極ピッチと同等にすることで、その有用性を発揮する。このピッチは例えば、130um程度である。このレベルの電極ピッチが実現できれば、アセンブリ装置等は特に変更する必要なく使用できる。 First, for the test electrodes, the electrode pitch is set to about 0.8 mm in a BGA type package, for example. If this level of electrode pitch can be realized, the fineness required for the operation of the socket, probe, and tester used in the sorting test will be sufficient to measure the CSP. On the other hand, the usefulness of the mounting electrode is demonstrated by making the electrode pitch equal to the electrode pitch of a normal bare chip. This pitch is about 130 μm, for example. If this level of electrode pitch can be realized, the assembly apparatus or the like can be used without any particular changes.

上記のような、実装用の狭いピッチでも配線できるようにするために、ガラス基材を用いたインターポーザーを使った方法が特開2003−249606に開示されている。しかし、試験用電極配置と実装用電極配置とにそれぞれ自由度をもたせるには、単に狭いピッチで配線できるだけでは限界があり、任意の試験用電極配置と実装用電極配置とが実現できないという問題があった。 In order to enable wiring with a narrow pitch for mounting as described above, a method using an interposer using a glass substrate is disclosed in Japanese Patent Application Laid-Open No. 2003-249606. However, there is a limit to simply providing wiring with a narrow pitch in order to give freedom to both the test electrode arrangement and the mounting electrode arrangement, and there is a problem that any test electrode arrangement and mounting electrode arrangement cannot be realized. there were.

一方、半導体チップのパッド電極を任意の電気接続部に対して接続できる配線方法を提供したものに特開2001−196529がある。特開2001−196529に開示される配線手法を図15に示す。図15では、半導体ベアチップ30の矢印Y−Y’方向に伸びる縁部近傍に配置されたパッド電極とパッケージ基板10において矢印X−X’方向に伸びる縁部近傍に配置されたパッド電極とを半導体ベアチップ31の内部配線を介して接続している。 On the other hand, Japanese Patent Application Laid-Open No. 2001-196529 provides a wiring method capable of connecting a pad electrode of a semiconductor chip to an arbitrary electrical connection portion. A wiring technique disclosed in Japanese Patent Laid-Open No. 2001-196529 is shown in FIG. In FIG. 15, the pad electrode disposed in the vicinity of the edge extending in the arrow YY ′ direction of the semiconductor bare chip 30 and the pad electrode disposed in the vicinity of the edge extending in the arrow XX ′ direction in the package substrate 10 They are connected via the internal wiring of the bare chip 31.

以上のごとくSIPを実現するのであるが、複数チップを3次元に積層するチップ・オン・チップを実現するには、積層するチップに隙間を設ける必要がある。この隙間は、半導体素子の放熱を行う働きや、実装の際の半導体素子の保護の働きをする。また、この隙間は、積層するチップのサイズが同じ、あるいは、ほぼ同じの場合、それらのチップを直接積層すると、下側のチップのボンディングパッド部分がかくれてワイヤボンディングができなくなることを防ぐ働きもする。この積層するチップ間に隙間を設ける手段をスペーサーと呼ぶ。 As described above, SIP is realized, but in order to realize a chip-on-chip in which a plurality of chips are three-dimensionally stacked, it is necessary to provide a gap in the stacked chips. This gap functions to radiate heat from the semiconductor element and to protect the semiconductor element during mounting. In addition, this gap prevents the bonding pads of the lower chip from being separated and making wire bonding impossible if the chips to be stacked are the same or nearly the same size and the chips are stacked directly. To do. The means for providing a gap between the stacked chips is called a spacer.

この発明のインターポーザーは、複数の半導体ベアチップを実装して封止される半導体パッケージにおいて、前記半導体ベアチップの該半導体パッケージへの実装に用いられるインターポーザーであって、半導体ベアチップをこのインターポーザーにマウントするために、前記半導体ベアチップの電極端子を接続する内部電極と、半導体ベアチップマウント後の試験時に試験装置の端子が接続される試験用電極と、半導体ベアチップをマウントしたのち前記半導体パッケージに実装される時に他の部品に接続される実装用電極とを備え、前記実装用電極は、半導体ベアチップの電極ピッチと同じピッチで形成され、前記試験用電極は、前記半導体ベアチップの電極ピッチよりも大きい前記半導体パッケージの電極ピッチと同じピッチで形成されたことを特徴としている。 The interposer of the present invention is an interposer used for mounting the semiconductor bare chip to the semiconductor package in a semiconductor package to be sealed by mounting a plurality of semiconductor bare chips, and the semiconductor bare chip is mounted on the interposer to be implemented the internal electrode connecting the electrode terminals of the semiconductor bare chip, and the test electrode terminals are connected in the test device during the test after the semiconductor bare chip mounting, the semiconductor package after mounting the semiconductor bare chip Mounting electrodes connected to other components, and the mounting electrodes are formed at the same pitch as the electrode pitch of the semiconductor bare chip, and the test electrode is larger than the electrode pitch of the semiconductor bare chip. Formed at the same pitch as the package electrode pitch It is characterized in that was.

また、この発明は、基材への実装時に該材との間に空間を形成する突起を設けたことを特徴とする。 Further, the invention is characterized in that a projection forming a space between said substrate at the time of mounting to a substrate.

この発明の半導体チップマウントサブ基板は、上記インターポーザーに半導体ベアチップをマウントして、該半導体ベアチップの電極端子と前記内部電極とを接続し、樹脂で封止したことを特徴とする。 The semiconductor chip mount sub-board of the present invention is characterized in that a semiconductor bare chip is mounted on the interposer , electrode terminals of the semiconductor bare chip and the internal electrodes are connected, and sealed with resin.

また、この発明は、前記樹脂に、基材への実装時に該基材との間に空間を形成する突起を形成したことを特徴とする。 Further, the present invention is characterized in that a protrusion is formed on the resin to form a space between the resin and the substrate when mounted on the substrate.

この発明は、上記半導体チップマウントサブ基板を、他の半導体素子とともに、基板状またはフレーム状の基材に搭載して樹脂封止したことを特徴とする。 The present invention is characterized in that the semiconductor chip mount sub-substrate is mounted on a substrate-like or frame-like base material together with other semiconductor elements and resin-sealed.

この発明によれば、半導体チップマウントサブ基板は、ベアチップを接続する内部電極と、ベアチップと同程度のピッチで形成された実装用電極と、半導体パッケージと同程度のピッチで形成された試験用電極を備えたインターポーザーを有するため、前記半導体チップマウントサブ基板をテストするときには、試験用電極を用いることで、従来のソケット方式でテストができ、テスト費用の削減が図れるとともに、前記半導体チップマウントサブ基板を実装するときには、実装用電極を用いることで、従来の実装装置が使用でき、実装費用の削減が図れる。
さらに、前記内部電極と、前記実装用電極と、前記試験用電極との相互接続を多層配線で実現することで、内部電極の配置と、試験用電極の配置と、実装用電極の配置とがそれぞれ任意に設定でき、様々なパッド配置の半導体チップに対して、テスト方式に適した試験用電極の配置と、実装条件に適した実装用電極の配置とがそれぞれ選択できる。
According to the present invention, the semiconductor chip mount sub-board includes an internal electrode for connecting the bare chip, a mounting electrode formed at a pitch similar to the bare chip, and a test electrode formed at a pitch similar to the semiconductor package. because it has an interposer having a said when testing semiconductor chip mounting sub-board, the use of the test electrode can test a conventional socket type, with attained a reduction in test cost, the semiconductor chip mounting sub When mounting the substrate, by using the mounting electrode, a conventional mounting apparatus can be used, and the mounting cost can be reduced.
Furthermore, by realizing the interconnection between the internal electrode, the mounting electrode, and the test electrode with a multilayer wiring, the arrangement of the internal electrode, the arrangement of the test electrode, and the arrangement of the mounting electrode Each can be set arbitrarily, and for the semiconductor chips having various pad arrangements, the arrangement of the test electrodes suitable for the test method and the arrangement of the mounting electrodes suitable for the mounting conditions can be selected.

また、この発明によれば、前記半導体チップマウントサブ基板の樹脂封止と、前記樹脂封止後の半導体チップマウントサブ基板と他の半導体チップと前記基材との樹脂封止を別に行うことにより、前記樹脂封止後の半導体チップマウントサブ基板の取り扱いがさらに簡単になり、テスト装置に要求される繊細度を低減でき、ひいてはテスト費用の削減が図れる。 Further, according to the present invention, the resin sealing of the semiconductor chip mount sub-substrate and the resin sealing of the semiconductor chip mount sub-substrate after the resin sealing, the other semiconductor chip, and the base material are separately performed. The handling of the semiconductor chip mounted sub-board after the resin sealing is further simplified, the fineness required for the test apparatus can be reduced, and the test cost can be reduced.

また、この発明によれば、前記半導体チップマウントサブ基板の樹脂封止部分に突起を設けることにより、前記突起をスペーサーとして利用することができるので、スペーサー挿入工程の省略が図れる。 Further, according to the present invention, by providing a protrusion on the resin sealing portion of the semiconductor chip mounting sub-board, the projections can be utilized as a spacer, thereby to omit the spacer insertion process.

また、この発明によれば、前記半導体チップマウントサブ基板のインターポーザー突起を設けることにより、前記突起をスペーサーとして利用することができるので、スペーサー挿入工程の省略が図れる。 Further, according to the present invention, by providing a projection on the interposer of the semiconductor chip mounting sub-board, the projections can be utilized as a spacer, thereby to omit the spacer insertion process.

また、この発明によれば、前記半導体チップマウントサブ基板の、前記実装用電極の配列ピッチと、前記試験用電極の配列ピッチとを異なるように設定することで、テスト方式に適した試験用電極の配列ピッチと、実装条件に適した実装用電極の配列ピッチとがそれぞれ選択できる。 According to the invention, the test electrode suitable for the test method is set by setting the arrangement pitch of the mounting electrodes and the arrangement pitch of the test electrodes of the semiconductor chip mount sub-board different from each other. And an arrangement pitch of mounting electrodes suitable for the mounting conditions can be selected.

また、この発明によれば、前記半導体チップマウントサブ基板とは別に、複数の電極と、前記電極を電気的に接続する多層配線とを形成したサブ基板を具備することで、ワイヤで接続可能な範囲を超えて、半導体チップと基材との電気的接続が実現できる。 In addition, according to the present invention, in addition to the semiconductor chip mount sub-board, a sub-board on which a plurality of electrodes and a multi-layer wiring for electrically connecting the electrodes are provided can be connected by wires. Beyond the range, electrical connection between the semiconductor chip and the substrate can be realized.

図1は本発明に係る半導体チップマウント封止サブ基板100の構造を示したものである。図2は、図1の断面図である。インターポーザー70に対して半導体ベアチップ30をマウントし、その下に、スペーサー90を積層し、さらにその下に半導体ベアチップ31を積層している。この半導体チップマウントサブ基板50を樹脂封止したものが半導体チップマウント封止サブ基板100である。 FIG. 1 shows a structure of a semiconductor chip mount sealing sub-substrate 100 according to the present invention. FIG. 2 is a cross-sectional view of FIG. The semiconductor bare chip 30 is mounted on the interposer 70, the spacer 90 is laminated below it, and the semiconductor bare chip 31 is laminated below it. A semiconductor chip mount sub-substrate 100 is obtained by sealing the semiconductor chip mount sub-substrate 50 with a resin.

図3は図2に示したインターポーザー70の上面図であり、試験用電極110と実装用電極120とをその表面に配備している。試験用電極110は、例えば、14×14のアレイ状に配備し、0.8mmピッチである。これはCSPチップの電極ピッチと同じレベルである。したがって、これらの試験用電極に対する測定は、従来のソケット方式でのテストが可能になる。実装用電極120は、例えば、片側に96個ずつ配備され、130μmピッチである。これは、ベアチップの電極ピッチと同じレベルである。したがって、これらの実装用電極120からリードフレームへのワイヤリングは従来装置を用いて実施できる。 FIG. 3 is a top view of the interposer 70 shown in FIG. 2, in which the test electrode 110 and the mounting electrode 120 are provided on the surface thereof. The test electrodes 110 are arranged in a 14 × 14 array, for example, and have a pitch of 0.8 mm. This is the same level as the electrode pitch of the CSP chip. Therefore, the measurement for these test electrodes can be performed by a conventional socket method. For example, 96 mounting electrodes 120 are arranged on each side and have a pitch of 130 μm. This is the same level as the electrode pitch of the bare chip. Accordingly, the wiring from the mounting electrode 120 to the lead frame can be performed using a conventional apparatus.

図4は図2に示したインターポーザー70の下面図である。このインターポーザー70上に配備する半導体ベアチップ30から内部電極130へワイヤリングを行う。内部電極130は、例えば、片側に36個ずつ配備され、160μmピッチである。 FIG. 4 is a bottom view of the interposer 70 shown in FIG. Wiring is performed from the semiconductor bare chip 30 provided on the interposer 70 to the internal electrode 130. For example, 36 internal electrodes 130 are provided on one side and have a pitch of 160 μm.

内部電極130と試験用電極110と実装用電極120との相互接続はインターポーザー70の内部配線で実現する。内部電極130と試験用電極110とを相互接続する第1層目の接続パターンを図5に示す。試験用電極110と実装用電極120とを相互接続する第2層目の接続パターンを図6に示す。2層を用いることで内部電極群、試験用電極群、実装用電極群を基板の面積を増加することなしに、相互の接続を実現している。このように、インターポーザー内の配線を多層にすることで、任意の試験用電極配置と実装用電極配置とが実現できる。 Interconnection between the internal electrode 130, the test electrode 110, and the mounting electrode 120 is realized by the internal wiring of the interposer 70. FIG. 5 shows a first layer connection pattern for interconnecting the internal electrode 130 and the test electrode 110. FIG. 6 shows a second layer connection pattern for interconnecting the test electrode 110 and the mounting electrode 120. By using two layers, the internal electrode group, the test electrode group, and the mounting electrode group are connected to each other without increasing the area of the substrate. As described above, by arranging the wiring in the interposer in multiple layers, any test electrode arrangement and mounting electrode arrangement can be realized.

インターポーザー内の配線を多層にすることで、任意の電極の接続が実現できることを、特開2001−196529の着想に応用したものが、図7である。図7の半導体ベアチップ30が図15の半導体ベアチップ30に相当し、図7のインターポーザー70が図15の半導体ベアチップ31の役割を受け持っている。すなわち、インターポーザー70の内部配線が半導体ベアチップ30からワイヤで接続可能な範囲を超えてパッケージ基板10への電気的接続を可能にしている。 FIG. 7 shows an application of the idea of Japanese Patent Application Laid-Open No. 2001-196529 that arbitrary electrodes can be connected by forming a multi-layer wiring in the interposer. The semiconductor bare chip 30 in FIG. 7 corresponds to the semiconductor bare chip 30 in FIG. 15, and the interposer 70 in FIG. 7 plays the role of the semiconductor bare chip 31 in FIG. 15. That is, the internal wiring of the interposer 70 can be electrically connected to the package substrate 10 beyond the range that can be connected from the semiconductor bare chip 30 with a wire.

半導体チップマウント封止サブ基板100と半導体ベアチップ34とをSIP化した場合の例を図8に示す。この場合、半導体チップマウント封止サブ基板100が半導体ベアチップ34とほぼ同じ大きさなので、下チップのボンディングパッド部がかくれないよう、スペーサー90を半導体チップマウント封止サブ基板100と半導体ベアチップ34との間に挿入している。 FIG. 8 shows an example in which the semiconductor chip mount sealing sub-substrate 100 and the semiconductor bare chip 34 are made into SIP. In this case, since the semiconductor chip mount sealing sub-board 100 is approximately the same size as the semiconductor bare chip 34, the spacer 90 is placed between the semiconductor chip mount sealing sub-board 100 and the semiconductor bare chip 34 so that the bonding pad portion of the lower chip is not covered. Inserted in between.

図8ではスペーサー90を用いていたが、半導体チップマウント封止サブ基板100にスペーサーの役割を果たす突起を備えることもできる。半導体チップマウント封止サブ基板100に突起を具備したものを図9に示す。この突起はモールド金型を所望の形状にすることで実現できる。この突起を半導体ベアチップ32上に接着し、半導体ベアチップ32からのワイヤリングスペースと半導体ベアチップ31からのワイヤリングスペースとを確保している。 Although the spacer 90 is used in FIG. 8, the semiconductor chip mount sealing sub-substrate 100 may be provided with a protrusion serving as a spacer. FIG. 9 shows a semiconductor chip mount sealing sub-substrate 100 having protrusions . This protrusion can be realized by making the mold mold into a desired shape. This protrusion is bonded onto the semiconductor bare chip 32 to secure a wiring space from the semiconductor bare chip 32 and a wiring space from the semiconductor bare chip 31.

図10に、図9と同様に半導体チップマウント封止サブ基板100に突起を備えた、別の実施例を示す。図9では、半導体チップマウント封止サブ基板に設けた突起を半導体ベアチップ32上に接着しているが、図10では、半導体チップマウント封止サブ基板100に設けた突起をパッケージ基板10上に接着している。この半導体チップマウント封止サブ基板100とパッケージ基板10との間に形成される空間に半導体ベアチップ31と32とを配備し、ワイヤリングを可能にしている。 FIG. 10 shows another embodiment in which a protrusion is provided on the semiconductor chip mount sealing sub-substrate 100 as in FIG. In FIG. 9, the protrusion provided on the semiconductor chip mount sealing sub-substrate is bonded onto the semiconductor bare chip 32, but in FIG. 10, the protrusion provided on the semiconductor chip mount sealing sub-substrate 100 is bonded onto the package substrate 10. is doing. Semiconductor bare chips 31 and 32 are provided in a space formed between the semiconductor chip mount sealing sub-substrate 100 and the package substrate 10 to enable wiring.

図11は、半導体チップマウントサブ基板50をパッケージ基板10上にスペーサー90を介して積層したものである。半導体チップマウントサブ基板50には、あらかじめ半導体ベアチップ34をマウントしている。この半導体チップマウントサブ基板50以外に、半導体ベアチップ32と半導体ベアチップ33とを積層配置した後、一括して樹脂封止を行っている。 In FIG. 11, the semiconductor chip mount sub-board 50 is stacked on the package board 10 via the spacer 90. The semiconductor bare chip 34 is mounted in advance on the semiconductor chip mount sub-board 50. In addition to the semiconductor chip mount sub-substrate 50, the semiconductor bare chip 32 and the semiconductor bare chip 33 are stacked and arranged, and then resin sealing is performed collectively.

図11の半導体チップマウントサブ基板50は、スペーサー90を介して積層しているが、インターポーザー70に突起を具備し、これにスペーサーの役割をさせてもよい。インターポーザー70に突起を設けた構造を図12に示す。この場合でも封止は一括で行うことが可能である。 Although the semiconductor chip mount sub-board 50 of FIG. 11 is laminated via the spacer 90, the interposer 70 may be provided with a protrusion, which may serve as a spacer. FIG. 12 shows a structure in which the interposer 70 is provided with protrusions . Even in this case, sealing can be performed in a lump.

本発明に係る半導体チップマウント封止サブ基板の外観図。1 is an external view of a semiconductor chip mount sealing sub-board according to the present invention. 図1の半導体チップマウンド封止サブ基板の断面図。Sectional drawing of the semiconductor chip mound sealing sub-board | substrate of FIG. 図2に示したインターポーザー70の上面図。FIG. 3 is a top view of the interposer 70 shown in FIG. 2. 図2に示したインターポーザー70の下面図。The bottom view of the interposer 70 shown in FIG. 内部電極130と試験用電極110とを相互接続するインターポーザー70内の第1層目の接続パターン。A connection pattern of the first layer in the interposer 70 that interconnects the internal electrode 130 and the test electrode 110. 試験用電極110と実装用電極120とを相互接続するインターポーザー70内の第2層目の接続パターン。A connection pattern of the second layer in the interposer 70 that interconnects the test electrode 110 and the mounting electrode 120. 本発明に係る、インターポーザー70の内部配線により、半導体ベアチップ30からワイヤで接続可能な範囲を超えてパッケージ基板10への電気的接続を可能にしている例。The example which enables the electrical connection to the package board | substrate 10 exceeding the range which can be connected with a wire from the semiconductor bare chip 30 by the internal wiring of the interposer 70 based on this invention. 本発明に係る、半導体チップマウント封止サブ基板100と半導体ベアチップ34とをSIP化した場合の例。The example at the time of SIP-izing the semiconductor chip mount sealing sub-board | substrate 100 and the semiconductor bare chip 34 based on this invention. 本発明に係る、突起を具備した半導体チップマウント封止サブ基板100と半導体ベアチップ31、32とをSIP化した場合の例。The example at the time of SIP-izing the semiconductor chip mount sealing sub-board | substrate 100 and the semiconductor bare chips 31 and 32 which comprised the protrusion based on this invention. 本発明に係る、突起を具備した半導体チップマウント封止サブ基板100と半導体ベアチップ31、32とをSIP化した場合の例。The example at the time of SIP-izing the semiconductor chip mount sealing sub-board | substrate 100 and the semiconductor bare chips 31 and 32 which comprised the protrusion based on this invention. 本発明に係る、半導体チップマウントサブ基板50をパッケージ基板10上にスペーサー90を介して積層し、半導体ベアチップ32、33とともに一括して樹脂封止した場合の例。An example in which the semiconductor chip mount sub-substrate 50 according to the present invention is stacked on the package substrate 10 via the spacer 90 and is encapsulated together with the semiconductor bare chips 32 and 33 with resin. 本発明に係る、突起を具備したインターポーザー70を持つ半導体チップマウントサブ基板50をパッケージ基板10上に積層し、半導体ベアチップ32、33とともに一括して樹脂封止した場合の例。An example in which a semiconductor chip mount sub-board 50 having an interposer 70 having protrusions is stacked on a package board 10 and sealed together with semiconductor bare chips 32 and 33 according to the present invention. 従来のSIPの例。Example of conventional SIP. 従来のSIPの例。Example of conventional SIP. 従来のSIPの例。Example of conventional SIP.

符号の説明Explanation of symbols

10‐パッケージ基板
20‐半導体パッケージ
21‐半導体パッケージ
22‐半導体パッケージ
30‐半導体ベアチップ
31‐半導体ベアチップ
32‐半導体ベアチップ
33‐半導体ベアチップ
34‐半導体ベアチップ
40‐電極
41‐電極
50‐半導体チップマウントサブ基板
60‐ワイヤ
61‐ワイヤ
70‐インターポーザー
80‐封止樹脂
81‐封止樹脂
90‐スペーサー
100‐半導体チップマウント封止サブ基板
110‐試験用電極
120‐実装用電極
130‐内部電極
10-Package substrate 20-Semiconductor package 21-Semiconductor package 22-Semiconductor package 30-Semiconductor bare chip 31-Semiconductor bare chip 32-Semiconductor bare chip 33-Semiconductor bare chip 34-Semiconductor bare chip 40-Electrode 41-Electrode 50-Semiconductor chip mount sub-substrate 60 -Wire 61-Wire 70-Interposer 80-Sealing resin 81-Sealing resin 90-Spacer 100-Semiconductor chip mount sealing sub-board 110-Test electrode 120-Mounting electrode 130-Internal electrode

Claims (5)

複数の半導体ベアチップを実装して封止される半導体パッケージにおいて、前記半導体ベアチップの該半導体パッケージへの実装に用いられるインターポーザーであって、
半導体ベアチップをこのインターポーザーにマウントするために、前記半導体ベアチップの電極端子を接続する内部電極と、半導体ベアチップマウント後の試験時に試験装置の端子が接続される試験用電極と、半導体ベアチップをマウントしたのち前記半導体パッケージに実装される時に他の部品に接続される実装用電極と、を備え、
前記実装用電極は、半導体ベアチップの電極ピッチと同じピッチで形成され、前記試験用電極は、前記半導体ベアチップの電極ピッチよりも大きい前記半導体パッケージの電極ピッチと同じピッチで形成されたことを特徴とするインターポーザー
In a semiconductor package to be sealed by mounting a plurality of semiconductor bare chips, an interposer used for mounting the semiconductor bare chip to the semiconductor package,
In order to mount the semiconductor bare chip on this interposer, the internal electrode for connecting the electrode terminal of the semiconductor bare chip , the test electrode to which the terminal of the test apparatus is connected during the test after mounting the semiconductor bare chip, and the semiconductor bare chip mounted And mounting electrodes connected to other components when mounted on the semiconductor package later ,
The mounting electrodes are formed at the same pitch as the electrode pitch of the semiconductor bare chip, and the test electrodes are formed at the same pitch as the electrode pitch of the semiconductor package that is larger than the electrode pitch of the semiconductor bare chip. Interposer to do .
基材への実装時に該材との間に空間を形成する突起を設けたことを特徴とする請求項1に記載のインターポーザー Interposer according to claim 1, characterized in that a projection forming a space between said substrate at the time of mounting to a substrate. 請求項1に記載のインターポーザーに半導体ベアチップをマウントして、該半導体ベアチップの電極端子と前記内部電極とを接続し、樹脂で封止したことを特徴とする半導体チップマウントサブ基板A semiconductor chip mount sub-board , wherein a semiconductor bare chip is mounted on the interposer according to claim 1, the electrode terminal of the semiconductor bare chip and the internal electrode are connected, and sealed with resin. 前記樹脂に、基材への実装時に該基材との間に空間を形成する突起を形成したことを特徴とする請求項3に記載の半導体チップマウントサブ基板4. The semiconductor chip mount sub-board according to claim 3, wherein a protrusion is formed on the resin to form a space between the resin and the base material when mounted on the base material. 請求項3に記載の半導体チップマウントサブ基板を、他の半導体素子とともに、基板状またはフレーム状の基材に搭載して樹脂封止してなる半導体パッケージA semiconductor package formed by mounting the semiconductor chip mount sub-board according to claim 3 together with other semiconductor elements on a substrate-like or frame-like base material and sealing with resin.
JP2004164489A 2004-06-02 2004-06-02 Interposer, semiconductor chip mount sub-board and semiconductor package Expired - Fee Related JP3842272B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2004164489A JP3842272B2 (en) 2004-06-02 2004-06-02 Interposer, semiconductor chip mount sub-board and semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004164489A JP3842272B2 (en) 2004-06-02 2004-06-02 Interposer, semiconductor chip mount sub-board and semiconductor package

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2005336256A Division JP4388926B2 (en) 2005-11-21 2005-11-21 Package structure of semiconductor device

Publications (2)

Publication Number Publication Date
JP2005347470A JP2005347470A (en) 2005-12-15
JP3842272B2 true JP3842272B2 (en) 2006-11-08

Family

ID=35499571

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004164489A Expired - Fee Related JP3842272B2 (en) 2004-06-02 2004-06-02 Interposer, semiconductor chip mount sub-board and semiconductor package

Country Status (1)

Country Link
JP (1) JP3842272B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8723334B2 (en) 2012-07-27 2014-05-13 Kabushiki Kaisha Toshiba Semiconductor device including semiconductor package

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4889359B2 (en) * 2006-04-14 2012-03-07 ルネサスエレクトロニクス株式会社 Electronic equipment
US7420206B2 (en) 2006-07-12 2008-09-02 Genusion Inc. Interposer, semiconductor chip mounted sub-board, and semiconductor package
US7772683B2 (en) * 2006-12-09 2010-08-10 Stats Chippac Ltd. Stacked integrated circuit package-in-package system
JP7042713B2 (en) * 2018-07-12 2022-03-28 キオクシア株式会社 Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8723334B2 (en) 2012-07-27 2014-05-13 Kabushiki Kaisha Toshiba Semiconductor device including semiconductor package

Also Published As

Publication number Publication date
JP2005347470A (en) 2005-12-15

Similar Documents

Publication Publication Date Title
US6249052B1 (en) Substrate on chip (SOC) multiple-chip module (MCM) with chip-size-package (CSP) ready configuration
KR100690922B1 (en) Semiconductor device package
JP2007123520A (en) Laminated semiconductor module
KR20060074796A (en) Semiconductor device package
US20130256865A1 (en) Semiconductor module
US20090065922A1 (en) Semiconductor device package structure
US20070052082A1 (en) Multi-chip package structure
JP4388926B2 (en) Package structure of semiconductor device
US7868439B2 (en) Chip package and substrate thereof
US20040245651A1 (en) Semiconductor device and method for fabricating the same
JP3842272B2 (en) Interposer, semiconductor chip mount sub-board and semiconductor package
JP2009188325A (en) Semiconductor package and method for manufacturing semiconductor package
KR20040080739A (en) Semiconductor chip having test pads and tape carrier package using thereof
JP2002134651A (en) Baseless semiconductor device and its manufacturing method
JP4303772B2 (en) Semiconductor package
JP2008277457A (en) Multilayer semiconductor device and package
JP4388989B2 (en) Semiconductor chip mount sealing sub-board
US8044498B2 (en) Interposer, semiconductor chip mounted sub-board, and semiconductor package
JP2000299433A (en) Laminated type package frame
JP2011123015A (en) Method of manufacturing semiconductor device
KR101096453B1 (en) Stacked semiconductor package
JP2007335907A (en) Semiconductor device
JP4452767B2 (en) Semiconductor device and manufacturing method thereof
JP2005353687A (en) Substrate for semiconductor device, and method of manufacturing semiconductor device
JPH1070150A (en) Csp semiconductor device

Legal Events

Date Code Title Description
A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20050920

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20051121

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20060328

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20060410

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20060718

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20060809

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100818

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100818

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100818

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100818

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110818

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120818

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130818

Year of fee payment: 7

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R255 Notification that request for automated payment was rejected

Free format text: JAPANESE INTERMEDIATE CODE: R2525

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees