JP4452767B2 - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology of manufacturing efficiently a package which contains a plurality of semiconductor chips. <P>SOLUTION: A method of manufacturing the semiconductor device first seals the semiconductor chip with resin to form a seal (S10), and performs polishing/thin filming for the seal (S12). Continuously, the operation of the seal (S14) is inspected, and a laminate is formed by laminating with other semiconductor chip or the seal using only a good article (S18). Then, the laminate is sealed with the resin (S20). Thus, the semiconductor device is obtained. <P>COPYRIGHT: (C)2005,JPO&amp;NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  With recent demands for higher functionality and lighter, thinner and smaller electronic devices, electronic components have been increasingly integrated and densely packaged. Semiconductor packages used in these electronic devices have been reduced in size and increased in pin count, and mounting substrates on which electronic components including the semiconductor package are mounted have also been reduced in size. Furthermore, in order to improve the storage property in an electronic device, a rigid flex board that can be bent by laminating and integrating a rigid board and a flexible board has been used as a mounting board.

  With the miniaturization of semiconductor packages, the conventional package using a lead frame has a limit on miniaturization. Therefore, recently, it is assumed that a chip is mounted on a circuit board, and BGA (Ball Grid) is used. Array) and a new area mounting type packaging method such as CSP (Chip Scale Package) have been proposed. In these semiconductor packages, a substrate having the functions of an electrode of a semiconductor chip and a lead frame of a conventional semiconductor package is used. The substrate is also called a semiconductor package substrate, and is made of various materials such as plastic and ceramics. As an electrical connection method between a semiconductor chip and a substrate terminal, a wire bonding method, a TAB (Tape Automated Bonding) method, or an FC (Flip Chip) method is known. BGA and CSP structures using an FC connection method that is advantageous to the above are actively proposed.

However, since the above method can accommodate only one semiconductor chip in one semiconductor package, there is a limit to downsizing the semiconductor package. For this reason, a technique for improving the mounting density by stacking and storing a plurality of semiconductor chips inside one semiconductor package has been proposed (Patent Document 1).
JP-A-10-70232

  However, if the percentage of guaranteed operation of the stacked semiconductor chips is low (not a good chip (KGD)), the operation of the product is uncertain until the semiconductor package is completed using this method. When a defect is discovered after being packaged, there is a problem that even a non-defective semiconductor chip incorporated therein is wasted.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a package in which a plurality of semiconductor chips are accommodated by making the semiconductor chip into a form in which operation can be individually confirmed during the manufacturing process of the multichip package. It is to provide a technology for efficiently manufacturing the above.

  According to the present invention, there is provided a semiconductor device including a stacked body in which a first sealing body in which a first semiconductor chip is sealed with a resin and a second semiconductor chip are stacked. .

  Thus, by laminating the semiconductor chip after resin sealing, the operation of the encapsulant can be easily inspected before lamination, and the laminate can be manufactured using only good products. As a result, it is possible to prevent a situation in which the non-operational semiconductor chip is stacked and a non-defective semiconductor chip becomes unusable. As a result, the semiconductor device can be efficiently manufactured and the manufacturing cost of the semiconductor device can be reduced.

  In the semiconductor device of the present invention, the stacked body may have a structure in which a second sealed body in which a second semiconductor chip is sealed with a resin and a first sealed body are stacked.

  In the semiconductor device of the present invention, the laminate can be further resin-sealed.

  The semiconductor device of the present invention can further include a package substrate, the first sealing body can be disposed on the package substrate, and the second semiconductor chip is disposed on the first sealing body. can do.

  In the semiconductor device of the present invention, the package substrate can include a conductor circuit that electrically connects the first semiconductor chip and the second semiconductor chip. By using such a package substrate, it is possible to electrically connect the stacked semiconductor chips even when the semiconductor chips are stacked after resin sealing.

  In the semiconductor device of the present invention, the first sealing body can be thinned by polishing. Thereby, a semiconductor device can be reduced in size. Even when the second semiconductor chip is formed by resin sealing the second sealing body, the second sealing body can be thinned by polishing.

  In the semiconductor device of the present invention, the first sealing body may include a heat conductive member provided around or inside the resin and made of a material having higher heat conductivity than the resin. Can be formed at substantially the same height as the sealing body in the stacking direction.

  Here, a metal or silicon can be used as the heat conducting member. By using such a material, for example, when a laminated semiconductor chip is bonded to another semiconductor chip via a substrate substrate such as a substrate by a wire bonding technique, heat to the bonding wire of the laminated substrate is applied. Conductivity can be improved.

  In the semiconductor device of the present invention, the second semiconductor chip can be electrically connected to the first semiconductor chip via a bonding wire.

  Here, a gold wire can be used as the bonding wire. By connecting semiconductor chips by wire bonding, various semiconductor chips having different designs can be flexibly connected.

  According to the present invention, a step of forming a sealing body by sealing the first semiconductor chip with a sealing resin, a step of forming a stacked body by stacking the sealing body and the second semiconductor chip, and A method for manufacturing a semiconductor device is provided.

  The method for manufacturing a semiconductor device of the present invention can further include a step of sealing the stacked body with a sealing resin.

  The method for manufacturing a semiconductor device of the present invention can further include a step of thinning the sealing body by polishing, and the thinned sealing body can be stacked in the step of forming the stacked body.

  The method for manufacturing a semiconductor device of the present invention can further include a step of inspecting the quality of the first semiconductor chip included in the sealing body, and is determined as a non-defective product in the step of inspecting the operation of the first semiconductor chip. A method for manufacturing a semiconductor device, comprising: forming a stacked body using the sealed body.

  Thereby, a laminated body can be manufactured using only good products, and a semiconductor device can be manufactured.

  According to the present invention, it is possible to efficiently manufacture a package containing a plurality of semiconductor chips by making the semiconductor chip into a form in which the operation can be individually confirmed in the multi-chip package manufacturing process.

FIG. 1 is a flowchart showing a procedure for manufacturing a semiconductor device in an embodiment of the present invention.
In the present embodiment, first, semiconductor chips (semiconductor elements) to be stacked are arranged on a substrate and electrically joined to the substrate (S8). Here, as the substrate, a rigid printed wiring board, a flexible printed wiring board, a ceramic substrate, or the like including a conductive circuit that electrically connects a semiconductor chip stacked thereon and another semiconductor chip is used. Can do. In addition, as a method of electrical bonding between the substrate and the semiconductor chip, wire bonding, solder balls, gold stud bumps, conductive paste, anisotropic conductivity, or the like can be used.

  Subsequently, the semiconductor chip disposed on the substrate is sealed with a sealing resin to form a sealing body (S10). As a sealing method, a transfer mold, an injection mold, a potting mold, or the like can be used.

  Thereafter, the sealing resin portion of the sealing body is polished with a grindstone, and the surface is flattened and thinned (S12). When electrical bonding between the semiconductor chip and the substrate is performed by wire bonding, polishing can be performed to the extent that the bonding wires are not exposed. When electrical bonding is performed by other methods, the entire semiconductor chip can be polished and further thinned. In this manner, the semiconductor device can be reduced in size by thinning the sealing body. The thinner the sealing body, the better the size reduction. However, in order to maintain the rigidity necessary for handling, the thickness of the sealing body is, for example, 50 μm or more, preferably 75 μm or more. it can. If the sealing resin portion of the sealing body is thin or flat from the beginning, this step can be omitted.

  Subsequently, each of the sealed semiconductor chips is inspected by an electrical test, and non-defective products are selected (S14 and S16).

  Subsequently, another sealing body which is similarly sealed and thinned and judged to be a non-defective product is mounted on the thinned sealing body as described above, and is laminated. They are electrically connected (S18). The electrical connection between the semiconductor chips can be performed by wire bonding, for example.

  Here, the lowermost sealing body can be formed by arranging a plurality of semiconductor chips on one substrate and sealing each of them. On the other hand, the sealing body laminated on the upper layer can be laminated on the lower sealing body in an individualized state. In such a state, an upper layer sealing body is sequentially laminated on a chip determined to be a non-defective product among the lowermost sealing bodies. Thus, handling can be facilitated by laminating a plurality of sealing bodies without individualizing the lowermost sealing body.

  After laminating a predetermined number of sealing bodies, these sealing bodies are again sealed with a sealing resin (S20). Here, for example, a plurality of stacked bodies can be sealed at the same time by transfer molding or the like, and after sealing, each stacked body is individualized to obtain a semiconductor device.

  By using the method as described above, it is possible to manufacture a semiconductor device in which only semiconductor chips that have been inspected and judged as non-defective products are stacked. Thereby, after manufacturing the semiconductor device, it is possible to prevent other semiconductor chips from being wasted because one defective semiconductor chip is included in the stacked body. In addition, the semiconductor chip is stacked after sealing, but since the sealing body is thinned and stacked, the semiconductor device can be downsized.

  Hereinafter, an example of an embodiment of the present invention will be described in detail. In addition, this invention is not limited by this.

FIG. 2 is a process cross-sectional view showing the manufacturing process of the sealing body produced in this example.
Hereinafter, the manufacturing process of the lowermost sealed body will be described. Here, the printed wiring board 102 was used as the substrate (FIG. 2A). The printed wiring board 102 is an FR5 printed wiring board having a thickness of about 100 μm. Subsequently, the first semiconductor chip 104 was mounted on the printed wiring board 102 using a film adhesive (FIG. 2B). The first semiconductor chip 104 has a plurality of pads arranged linearly at the center of the element formation surface and has a thickness of about 80 μm. Although only one first semiconductor chip 104 is shown here, the lowermost sealing body has a plurality of first semiconductor chips 104 arranged on the printed wiring board 102 and forms the sealing body in that state. did.

  Subsequently, the pads of the first semiconductor chip 104 and the printed wiring board 102 were electrically joined by the bonding wires 106 (FIG. 2C). A gold wire was used as the bonding wire 106. The height of the topmost part of the bonding wire 106 was about 180 μm from the surface of the printed wiring board 102.

  Next, the frame member 108 was mounted around the first semiconductor chip 104 using a paste adhesive (FIG. 2D). Here, a copper frame having a thickness of about 200 μm was used.

  Here, the material of the frame member 108 is not particularly limited. For example, when a laminated semiconductor chip is bonded to a substrate or another semiconductor chip by a wire bonding technique, the heat applied to the bonding wire of the laminated substrate is not limited. Since conduction may be insufficient, it is preferable to use a material having good thermal conductivity as the frame member 108. Thereby, heat can be conducted to the substrate through the frame member 108, so that heat conduction to the bonding wire can be ensured. The frame material 108 is formed so as to be exposed on the surface of the sealing resin when polishing in a later step.

  In addition, by appropriately setting the size of the frame member 108, when the semiconductor chip is potted, the sealing region can be reduced and the semiconductor device can be downsized.

  Subsequently, a potting sealing resin was injected into the frame material 108 and cured to seal the first semiconductor chip 104 (FIG. 2E). CRP-3900 (manufactured by Sumitomo Bakelite Co., Ltd.) was used as the sealing resin.

  Subsequently, the sealing resin 110 was polished with a grindstone 150 to flatten the surface of the sealing resin 110 and the thickness of the sealing resin 110 was reduced to about 200 μm (FIG. 2F). Thereby, the 1st sealing body 100 was obtained. Thereafter, inspection was conducted by an electrical test to select non-defective products.

FIG. 3 is a process cross-sectional view showing the manufacturing process of the sealing body produced in this example.
Here, a printed wiring board 202 was used as the substrate (FIG. 3A). The printed wiring board 202 is a flexible printed wiring board having a thickness of about 50 μm. Subsequently, a film 203 was attached to a predetermined portion of the printed wiring board 202 (FIG. 3B). The film 203 is a non-conductive film.

  Next, the second semiconductor chip 204 having terminals on the entire periphery of the element formation surface was mounted on the printed wiring board 202 (FIG. 3C). Here, a gold stud bump is formed on the terminal of the second semiconductor chip 204, and the second semiconductor chip 204 is mounted on the printed wiring board 202 by applying heat and pressure while aligning the second semiconductor chip 204 with a flip chip bonder. Electrical connection was performed.

  Subsequently, the second semiconductor chip 204 was sealed with a sealing resin 210 using a transfer mold (FIG. 3D). EME-7200 (manufactured by Sumitomo Bakelite Co., Ltd.) was used as the sealing resin.

  Thereafter, the sealing resin 210 was polished with a grindstone 250 to flatten the surface of the sealing resin 210, and the thickness of the sealing resin 210 was reduced to about 150 μm (FIG. 3E). Thereby, the 2nd sealing body 200 was obtained. Thereafter, inspection was conducted by an electrical test to select non-defective products.

FIG. 4 is a process cross-sectional view illustrating an example of a semiconductor device manufacturing process.
First, the second sealing body 200 shown in FIG. 3 was laminated on the first sealing body 100 shown in FIG. 2 (FIG. 4A). These were joined by a film adhesive. Here, the frame member 108 included in the first sealing body 100 was laminated so as to overlap the peripheral portion of the printed wiring board 202 of the second sealing body 200.

  Subsequently, the peripheral portion of the printed wiring board 202 of the second sealing body 200 and the peripheral portion of the printed wiring board 102 of the first sealing body 100 are electrically joined by the bonding wires 302 (FIG. 4). (B)). As described above, since the frame material 108 included in the first sealing body 100 is laminated so as to overlap with the peripheral portion of the printed wiring board 202 of the second sealing body 200, when the bonding wire 302 is formed. Heat can be conducted to the periphery of the printed wiring board 202, and the bonding wire 302 can be formed satisfactorily.

  Then, the laminated body of the 1st sealing body 100 and the 2nd sealing body 200 was collectively sealed with the sealing resin 304 (FIG.4 (c)). Here, EME-7200 (manufactured by Sumitomo Bakelite Co., Ltd.) was used as the sealing resin. Then, it individualized for every laminated body and the semiconductor device 300 was obtained.

  As a result of confirming the operation of the semiconductor device 300 as described above, it was confirmed that the semiconductor device operates normally.

  As described above, according to the present invention, in the manufacture of a multichip package in which a plurality of semiconductor chips are three-dimensionally stacked and packaged, the yield of the semiconductor device can be improved, and the size and weight can be reduced. Increases functionality and capacity.

  The present invention has been described based on the embodiments and examples. It is to be understood by those skilled in the art that the embodiments and examples are merely examples, and various modifications are possible and that such modifications are within the scope of the present invention.

  For example, in the above embodiment, the example in which the sealing bodies sealed with the sealing resin are stacked is shown. However, the present invention is not sealed with the sealing body sealed with the sealing resin. The present invention can also be applied to a case where a semiconductor chip is stacked.

  In addition to the semiconductor chip, passive elements can be stacked. In this case, the passive elements may be laminated with resin sealing.

  FIG. 5 is a cross-sectional view illustrating another example of the semiconductor device 300. The 1st sealing body 100 and the 2nd sealing body 200 can also be laminated | stacked on both sides of the insulating film 214 in which the wiring pattern was formed, for example. Here, the second sealing body 200 can be configured without the printed wiring board 202. The terminals of the second semiconductor element 204 are electrically joined to the wiring pattern of the insulating film 214. A through electrode is provided at an end of the insulating film 214, and the wiring pattern and the electrode pad 114 on the printed wiring board 102 are electrically connected. Accordingly, the first semiconductor element 104 and the second semiconductor element 204 are electrically connected via the printed wiring board 102. As described above, the first sealing body 100 and the second sealing body 200 can be electrically connected in various forms.

  2 shows an example in which a material having good thermal conductivity is used as the frame member 108 when using the potting sealing resin. However, when sealing by other methods, the bonding wire is formed. In order to ensure heat conduction, a material having good heat conductivity can be provided around or inside the sealing resin.

Furthermore, the present invention includes the following aspects.
[1] A method for manufacturing a multi-chip package by stacking a plurality of semiconductor packages whose operations have been confirmed after confirming the operation of the semiconductor package, wherein the stacked semiconductor package and another semiconductor A method of manufacturing a multi-chip package, wherein the package is connected by a gold wire;
[2] At least one of the semiconductor packages has a semiconductor element mounted on an organic substrate having a terminal for connecting to the semiconductor element, a terminal for connecting to another package, and a conductor circuit for connecting them. After performing, the manufacturing method of the multichip package as described in [1] which is what sealed the semiconductor element with sealing resin,
[3] The multichip package manufacturing method according to [1] or [2], in which the upper surface of the sealing material of the semiconductor package is polished and planarized before the plurality of semiconductor packages are stacked.
[4] A metal or silicon member having substantially the same height as the sealing material constituting the semiconductor device is disposed inside or at the end of the sealing material. The multi described in [1], [2] or [3] Chip package manufacturing method,
[5] A multichip package manufactured by the manufacturing method according to any one of [1] to [4].

4 is a flowchart showing a manufacturing procedure of a semiconductor device in the embodiment of the present invention. It is process sectional drawing which shows the manufacturing process of the sealing body produced in the Example. It is process sectional drawing which shows the manufacturing process of the sealing body produced in the Example. It is process sectional drawing which shows the manufacturing process of the semiconductor device produced in the Example. It is sectional drawing which shows the other example of the semiconductor device of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 1st sealing body 102 Printed wiring board 104 1st semiconductor chip 106 Bonding wire 108 Frame material 110 Sealing resin 150 Grinding stone 200 2nd sealing body 202 Printed wiring board 203 Film 204 2nd semiconductor chip 210 Sealing Stop resin 250 Grinding stone 300 Semiconductor device 302 Bonding wire 304 Sealing resin

Claims (11)

A first sealing body in which the first semiconductor chip is resin-sealed;
A second semiconductor chip;
Including a laminated body,
The first sealing body is a heat conducting member made of a material having higher thermal conductivity than the resin, which is provided around or inside the resin so as to surround the first semiconductor chip. includes a frame member, the frame member is a semiconductor device characterized by the laminating direction, were formed in the same height as the sealing body. The semiconductor device according to claim 1,
The stacked body has a structure in which a second sealing body in which the second semiconductor chip is sealed with a resin and the first sealing body are stacked. The semiconductor device according to claim 1 or 2,
A semiconductor device, wherein the laminate is further sealed with resin. The semiconductor device according to claim 1,
A package substrate,
The first sealing body is disposed on the package substrate, and the second semiconductor chip is disposed on the first sealing body. The semiconductor device according to claim 4,
The package substrate includes a conductor circuit that electrically connects the first semiconductor chip and the second semiconductor chip. The semiconductor device according to claim 1,
The semiconductor device, wherein the first sealing body is thinned by polishing. The semiconductor device according to claim 1,
The semiconductor device, wherein the second semiconductor chip is electrically connected to the first semiconductor chip via a bonding wire. A first step of sealing the first semiconductor chip with a sealing resin to form a sealing body;
A second step of stacking the sealing body and the second semiconductor chip to form a stacked body;
Including
In the first step, a frame member made of a heat conductive member made of a material having higher thermal conductivity than the resin is provided around or inside the resin so as to surround the first semiconductor chip , and in a stacking direction The method for manufacturing a semiconductor device is characterized in that the semiconductor device is formed at a height equal to that of the sealing body. In the manufacturing method of the semiconductor device according to claim 8,
The manufacturing method of the semiconductor device characterized by further including the process of sealing the said laminated body with sealing resin. In the manufacturing method of the semiconductor device according to claim 8 or 9,
Further comprising the step of thinning the sealing body by polishing,
In the step of forming the stacked body, the thinned sealing body is stacked. In the manufacturing method of the semiconductor device according to claim 8,
Further comprising the step of inspecting the quality of the first semiconductor chip included in the sealing body,
A method of manufacturing a semiconductor device, comprising: forming the stacked body using the sealing body determined to be a non-defective product in the step of inspecting the operation of the first semiconductor chip.

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