JPS604241A - Semiconductor device - Google Patents

Abstract

PURPOSE:To contrive to reduce the noise due to parasitic capacitance in a semiconductor integrated circuit device havng the structure of multilayer wiring. CONSTITUTION:Wirings 4 and 5 intersect with each other over an insulation film 2 on a semiconductor substrate 1, and a protection film 6 is formed thereon. A wiring 7 is inserted between the wirings 4 and 5 via insulation film 8. This wiring 7 is constructed so as to cover the whole region of intersection between the wirings 4 and 5 and fixed to a substrate potential. Therefore, the formation of the wiring 7 by means of a metal such as Al having a sufficiently small wiring resistance or poly Si causes no noise due to the parasitic capacitance, because the wiring 7 has the effect of electrical shielding between the wirings 4 and 5 and does not transmits the variation of the potential of one of them to the other.

Description

[Detailed description of the invention] The present invention relates to a semiconductor integrated circuit device.

Today, integrated circuits are increasing their density by using multi-layer wiring technology instead of reducing the device area. This can be seen from the fact that the early 4OS transistors were integrated circuits made of a single layer of aluminum, and that products with two layers of polysilicon and two layers of aluminum are currently being manufactured. Therefore, parasitic ambiguity is likely to occur between each wiring.

This parasitic capacitance has the effect of causing malfunctions in digital circuits and noise in analog circuits.

This principle is shown in FIG. An insulating film 2 is formed on a semiconductor substrate 1, and wirings 4 and 5 are formed on the insulating film 2 via an interlayer insulating film 3.
intersect, and a protective film 6 is formed thereon. In this figure, the wiring 5 extends in a direction perpendicular to the plane of the paper.The wiring 4 and 5 are made of aluminum, for example, and the insulation film 2, 3, 1 and 6I are made of silicon dioxide film. The parasitic capacitance caused by the intersection of wirings 4 and 5 is 045, and wiring 4.5 is C, , C
, the noise due to the parasitic structure of the structure shown in FIG. 1 can be explained by the circuit shown in FIG. 2. First, the city to wiring 4! When EV, ke is applied, C4°V11= −−m−−−−X V is applied to the wiring 5.

When the electric current F-E of C450C5 also applies the voltage v,' to the wiring 5,
+ItL)E is applied to Is4. This circuit can be modified assuming that I%15 or 1-j4 is electrically floating. Although we considered the change in the potential of the other free grain due to I't, in most cases in conventional circuits, the potential is fixed at a certain potential. The circuit shown in FIG. 3 takes this into consideration. This circuit equivalently shows that the wiring 5 is fixed at a certain potential by the internal resistance Ri and the voltage source Vi.
It was expressed as When a voltage v4 is applied to the wiring 4 at time t=o so as to cause J movement from this circuit, a voltage of +Vi (t≧0) is generated in the wiring 5. This parasitic capacitance C4! , VC, the potential change in the wiring 4 is caused by the time constant Ri (C5+
From this equation, it can be seen that this occurs as spike noise of C411). This noise causes malfunctions in digital circuits and noise in analog circuits.

The present invention aims to reduce noise caused by this parasitic capacitance.

A feature of the present invention is that in a semiconductor device in which multilayer wiring is formed on a semiconductor substrate via an insulating film, a wiring formed to cover an intersection of the multilayer wiring is inserted between the multilayer wiring,
It is found in semiconductor devices that are fixed at a constant potential. It is preferable to use aluminum or polysilicon as the insertion wiring.

An embodiment of the present invention is shown in FIG. In this figure, a wiring 7 is inserted between the wirings 4 and 5 of FIG. 1 with an insulating film 8 interposed therebetween. This wiring 7 is made so as to cover the entire area where the wirings 4 and 5 intersect, and is fixed at the substrate potential. Therefore, if the wiring 7 is formed of a metal such as aluminum having a sufficiently low wiring resistance, the wiring 7 has an electrical shielding effect between the wirings 4 and 5, and does not transmit potential changes in one to the other. Therefore, it can be seen that noise due to parasitic capacitance is eliminated.

As another embodiment of the present invention, if the wiring 7 is connected to the power supply wiring, since the internal resistance of the power supply is generally small, this wiring 7 is not susceptible to voltage fluctuations due to parasitic capacitance, and therefore the wiring 7 is connected to the power supply wiring. It has an electrical shielding effect. Even if the material of the wiring 7 was changed from metal such as aluminum to polysilicon, this city still has an air shielding effect.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of an intersection of wiring made by a conventional method, FIGS. 2 and 3 are equivalent circuits thereof, and FIG. 4 is a sectional view of an intersection of wiring made by an embodiment of the present invention. be. In addition, in the figure, 1... semiconductor substrate, 2...
...Insulating film, 3...Interlayer insulating film, 4,5.
. . . Wiring, 6 . . . Protective film, 7 . . . Wiring, 8 . . . Insulation 11α. Agent Patent Attorney B] Hara J Day, 1-'

Claims (5)

[Claims] (1) In a semiconductor device in which multilayer wiring is formed on a semiconductor substrate via an insulating film, wiring formed to cover the intersection of the multilayer wiring is inserted between the multilayer wiring and fixed at a constant potential. A semiconductor device characterized by: (2) The semiconductor device according to claim (1), wherein aluminum or polysilicon is used as the insertion wiring. (3) A semiconductor device according to claim (1) or (2), characterized in that the insertion wiring is coupled to a power supply voltage supply wiring. (4) The semiconductor device according to claim (1) or claim (2), wherein the insertion wiring is fixed to a ground potential. (5) The semiconductor device according to claim 1 or 2, wherein the inserted wiring is fixed at a substrate potential.