JPH04363058A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a multilayer-interconnection semiconductor device wherein a semiconductor chip in which an integrated circuit has been formed on a semiconductor substrate is mounted, its performance can be increased, it can be made functional, its density can be made high and its cost can be lowered by using a fine metal interconnection technique and an insulation technique for the integrated circuit. CONSTITUTION:A semiconductor device is provided with the following: a semiconductor substrate 1; a plurality of semiconductor chips 2-1 to 2-2 which have been arranged at the upper part of the semiconductor substrate 1; an insulating layer 7 into which the plurality of semiconductor chips 2-1 to 2-3 are buried; and interconnection layers 5, 5a which connect a plurality of semiconductor chips 2-1 to 2-3 to each other.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a multilayer wiring structure.

0002

2. Description of the Related Art Electronic circuit systems are usually constructed from a plurality of different types of circuit elements. In order to achieve higher performance, higher density, lower cost, etc. of different types of elements, (1) a monolithic system using a mixed mounting process has been used as a means of integrating them into one IC. In addition, (2) surface-mount type packages for printed circuit board circuits have recently been used in order to increase the packaging density of packages on printed circuit boards. Furthermore, (3) a multi-chip package IC mounted on a lead frame substrate, that is, a technology in which multiple integrated circuit chips are encapsulated in one package, is used.

0003

[Problem to be solved by the invention] However, the above (
1) MOS logic, non-volatile memory/DRAM/
Various memories such as SRAM, bipolar ICs are becoming faster,
As the capacity increases, each has its own unique structure,
If these are to be integrated into one monolithic IC, a problem arises in that it requires a great deal of time, money, and engineers to develop the wafer process. Furthermore, each time a new special element is added and mixed, a new wafer process must be developed. Therefore, the wafer process becomes longer and more complicated, which is disadvantageous in terms of cost and manufacturing period.

[0004] In addition, in item (2) above, in order to increase the scale of circuit systems and make products more compact, packages are required, and the wiring pitch and through hole diameter on printed circuit boards are on the order of several hundred microns. It is not sufficient for miniaturization.

[0005] Furthermore, as circuit systems become larger, there is a strong demand for an increase in the number of pins in a package, which significantly increases the difficulty of packaging technology and mounting technology. Direct mounting of chips to further increase packaging density
AB technology exists, but the pitch of pads for connection with the outside is about 100 microns, and the number of pins is several hundred.

[0006] Regarding item (3) above, in this method, there is a limit to the number of chips that can be mounted, and it is difficult to multilayer metal wiring between chips. Another problem is that it cannot be directly applied to large-scale circuit systems.

[0007] The present invention provides an IC (microcomputer) on a semiconductor substrate.
MOS logic such as ASIC, non-volatile memory/DR
Various memories such as AM/SRAM, bipolar elements),
Semiconductor chips equipped with power elements, active elements such as single transistors and diodes, passive elements such as L/R/C, and other elements are mounted on a semiconductor substrate, and high performance is achieved through the fine metal wiring technology and insulation technology of integrated circuits. The purpose of the present invention is to provide a multilayer interconnection semiconductor device that is capable of increasing density and reducing cost by increasing functionality and functionality.

[0008]

[Means for Solving the Problems] A semiconductor device according to the present invention includes, on a single semiconductor substrate, a plurality of semiconductor chips, an electrical insulator covering the chips, and a chip embedded in the insulator. and a wiring layer connecting between the two. The semiconductor device according to the present invention is characterized in that an integrated circuit is also formed on the semiconductor substrate itself.

[0009]

[Operation] That is, the present invention allows the application of integrated circuit manufacturing technology on a semiconductor substrate, thereby achieving higher performance and higher packaging density of the entire circuit system. Further, according to the present invention, the entire circuit system can be constructed by simply mounting existing chips on a semiconductor substrate and performing metal wiring between the chips, so that the process development period can be shortened. Additionally, printed boards and packages are no longer required, and a long and complicated wafer process is no longer necessary, making it possible to realize a circuit system that is cost-effective. Furthermore, each chip is arranged on a semiconductor substrate, and the wiring between the chips can be achieved by using LSI's fine multilayer metal wiring technology, so that the number of external pins (terminals) can be reduced.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a semiconductor device according to the present invention will be described with reference to the drawings.

In FIG. 1A, an insulating protective film, which will be described later, is formed on a semiconductor substrate 1, and a plurality of semiconductor integrated circuit chips 2-1, 2-2, 2-3 are formed in this insulating protective film.
is buried. In addition, the semiconductor integrated circuit chip 2-1,
2-2 and 2-3, as shown in FIG. 1B, there are active elements 10 such as MOS transistors and Bipolar Transistors, passive elements 11 such as resistors and capacitors, wiring 12 connecting the active elements 10 and the passive elements 11, and the like. It is equipped. Note that 13 is a pad.

That is, first, recesses 3 are formed on the surface of the semiconductor substrate 1, corresponding to the sizes and thicknesses of the integrated circuit chips 2-1, 2-2, and 2-3. Furthermore, an insulating film is formed over the entire surface. This insulating film becomes an insulating film 4 together with an insulating film that will be formed later. Chips 2-1, 2-2, 2-3, etc. are fixed to the recesses of the insulating film corresponding to the recesses 3 using a suitable fixing material, and the chips are embedded so that the surfaces are as flat as possible. At this time, it is preferable to mark the semiconductor substrate 1 and each integrated circuit chip to align their relative positions.

Next, an insulating protective film for electrically insulating between the semiconductor substrate 1 and the integrated circuit chips and between each integrated circuit chip is formed, and an insulating protective film 4 is formed together with the previously formed insulating protective film. When embedding the chip, if necessary, the semiconductor substrate 1 and the integrated circuit chip may be connected via a conductor 8 as shown in FIG. 1B in order to have the same potential. Next, a hole is made in the above-mentioned insulating protective film for contacting the lead wire from the integrated circuit chip with the metal wiring. Next, metal is deposited and etched to form metal wiring 5. Further wiring 5
a is obtained using multilayer wiring technology.

Next, an insulating protective film 6 is applied, and a hole is made in the external lead line portion. FIG. 1C shows a plan view of the above embodiment. Integrated circuit chips 2-1, 2-2, 2- on a semiconductor substrate 1
3, 2-4 are buried, and multilayer metal wiring 5, 5a is installed between the chips.
It is also connected to the bonding pad 9 for external drawing.

Note that the multilayer metal wiring 5, 5a and the chip 2-1
, 2-2, 2-3, when connecting chips 2-1, 2-
In addition to connecting the wires 5 and 5a to the bonding pads 13 on the chips 2 and 2-3, the wires 5 and 5a are connected to the wires 12 such as arbitrary signal lines and power supply lines inside the chips 2-1, 2-2, and 2-3. May be connected. Therefore, the pads 13 do not necessarily need to be formed on the chips 2-1, 2-2, and 2-3.

[0016] By using multilayer metal wiring in this way, and using the entire surface of one layer for the power supply, ground voltage, or both, it is possible to create a circuit system that is resistant to external noise and generates little noise from itself. can. Further, a metal wiring layer can also be used for heat radiation. Board 1
A reinforcing material 7 may be attached to the back side.

Note that the semiconductor substrate 1 and the chips 2-1 and 2-2
, 2-3 are formed in separate processes, and chips 2-1, 2-2, and 2-3 are also formed in separate processes.

FIGS. 2A and 2B show MOSFETs on the semiconductor substrate 1.
FIG. 3 is a cross-sectional view of an example in which a semiconductor integrated circuit including a semiconductor device and the like is fabricated, and then individual integrated circuit chips are installed. It is preferable that a semiconductor substrate 1 on which MOS transistors T1, T2, . . . In addition, the MOS is placed at the optimum position for characteristics.
The transistors may be arranged in a distributed manner and an integrated circuit chip may be mounted. Note that in FIGS. 2A and 2B, the same or corresponding parts as in FIGS. 1A and 1B will be referred to with the same drawings, and the description thereof will be omitted. FIG. 3A shows another embodiment of the invention.

A first insulating film 2 is formed on a single semiconductor substrate 1, and semiconductor chips 2-1 and 2 each having a thickness of about 100 μm or less are manufactured on the film 22 by different processes.
-2 and 2-3 are placed on the semiconductor substrate 1. The areas between and above the semiconductor chips 2-1, 2-2, and 2-3 are covered with a second insulating film 33, and an open contact is opened in the second insulating film 33 as necessary. Furthermore, a first metal film 8 is deposited and a wiring pattern is formed using photolithographic technology to provide wiring between the chips. Furthermore, when performing multilayer wiring,
forming a third insulating film 14 on the first metal film wiring 88;
Contacts are opened as necessary, a second metal wiring film 99 is deposited thereon, a wiring pattern is formed using photoengraving technology, and a fourth insulating film 11 is further formed on the element. may be formed.

[0020] The semiconductor chips 2-1, 2-2, 2-3
An integrated circuit has already been formed on the chip, respectively, 15-1, 15-2, 15-3 are transistor gates, 16-1, 16-2, 16-3 are drain/source diffusion layers, 17-1, 17-2, 17-3 are metal wiring layers within the chip, and 32-1, 32-232-3 are insulating layers within the chip.

Although the metal wiring layer in the semiconductor chip is a single layer here, it may be multilayered. The main purpose of the second insulating film 33 is to flatten the base of the first metal wiring film 88, so it fills in the steps between the chips and may be made of a material with a higher coverage, such as an insulating resin. good.

FIG. 3B shows an example of another embodiment of the present invention, and the difference from FIG. 3A is that the first
The insulating film 22 is opened as necessary, and a conductive layer 25 is provided to connect the semiconductor chip 2-1 and the semiconductor substrate 1. In this way, by setting the semiconductor substrate 4-1 and the semiconductor substrate 1 at the same potential, disturbances such as noise can be prevented. Alternatively, a conductive film may be formed over the entire surface of the semiconductor substrate 1, semiconductor chips may be placed on top of the conductive film, and all the chips and the semiconductor substrate may be connected to the same potential.

FIG. 3C shows a plan view of the semiconductor device of the present invention, in which semiconductor chips 2-1,
2-2, 2-3, and 2-4 are arranged, and the chips are connected by the first metal wiring layer 88 and the second metal wiring layer 99.
The output pad 19 is formed by the second metal wiring layer 99.

FIG. 4A is an example of another embodiment of the present invention,
An integrated circuit consisting of a plurality of MOS transistors having a gate electrode 41 and drain/source regions 43 is formed on the surface of the semiconductor substrate 1 . In addition, 44 is a wafer area,
48 is a metal wiring. A first insulating film 22 is formed thereon, and semiconductor chips 2 each manufactured by a different process and processed to be sufficiently thin with respect to the semiconductor substrate 1 are formed thereon.
-1, 2-2, and 2-3 are arranged. The other structure is the same as that in FIG. 3A, except that the first and second metal wiring layers 88,
99 connects between the semiconductor chips and between the elements on the semiconductor substrate and the chips.

FIG. 4B shows a chip and a substrate connected by a conductive layer 25, similar to FIG. 3B. FIG. 4C is a plan view of FIG. 4A, and 17-1, 17-2, 17-3 are integrated circuit areas formed on the semiconductor substrate, and semiconductor chips 2-1, 2-
2 and 2-3 through metal wirings 88 and 99.

In the embodiment shown in FIGS. 1A and 1B, the semiconductor chip is manufactured by embedding it in a concave portion of the semiconductor substrate, so it is technically difficult to form the concave portion and the number of steps is large. This method has disadvantages in that it leads to an increase in cost, and that the strength of the semiconductor substrate deteriorates because a recess is formed in the semiconductor substrate.

A semiconductor chip processed to be sufficiently thin with respect to the semiconductor substrate is placed on the semiconductor substrate, and by covering the gaps between the chips with an insulating film having a high step coverage, a metal wiring layer between the chips is formed. By flattening the base, it is possible to provide a highly integrated semiconductor device that is technically relatively easy, requires fewer steps than the conventional method, is low cost, and does not cause deterioration of the strength of the semiconductor substrate. Become.

FIG. 5 shows an MPU chip 11, a DRAM chip 12, a peripheral control chip 13, and their interface chip 14, which constitute a microcomputer circuit system.
An example is shown in which the following are mounted on one semiconductor substrate 1. 15 is a bonding pad. Address and data buses between these integrated circuit chips that require a large number of wires are wired directly on the semiconductor substrate 1 at a high density, resulting in shorter wire lengths and fewer wires, resulting in a high-speed microcontroller. can. In order to configure a higher level system, the one shown in FIG. 6 can be put into a package.

FIG. 6 shows the EPROM chip 21 and capacitor 22.
, a resistor 23, and a crystal 24 (these are also considered to be a type of chip). Connector terminals 25 are provided for connection to other systems. This terminal 25 may be provided on the reinforcing plate (insulating) 7. In recent years, wafer size has increased, making it possible to mount large-scale circuits. It is also possible to construct a circuit system using an entire wafer.

[0030]

As described above, according to the present invention, the following advantages can be obtained.

(1) High performance and high packaging density of the entire circuit system can be realized. In other words, faster, lighter, and more compact electronic devices are the demands of the times. The present invention uses fine metal wiring technology to narrow the width and length of the wiring, reduce parasitic resistance and capacitance, and reduce the number of elements that drive current, resulting in faster speeds, lower power consumption, and lower heat generation. reduction is possible.

Furthermore, it is possible to independently select elements with the optimum structure, or mutually compensate for the weaknesses of other elements. For example, high-speed cache memory with Bi-CMOS structure and MOS
A high-speed, high-performance circuit system can be realized by directly connecting the structured MPU on a semiconductor substrate. Furthermore, since the package is eliminated, no pads, wires, or lead frames are required for bonding between the chip and the package. The wiring pitch and through-hole diameter can be made finer, allowing for dramatically higher density. Furthermore, by measuring the characteristics of individual integrated circuit chips and combining the characteristics of the chips, it is possible to improve the performance of the circuit system without reducing timing or voltage level margins.

(2) Development period can be significantly shortened. That is, according to the present invention, a circuit system can be constructed by simply mounting existing integrated circuit chips on a semiconductor substrate and making metal wiring between the chips, so that the development period can be shortened. When adding a new circuit, you can create a new chip and mount it in combination with an existing chip using the gate array or standard cell method, or you can distribute and bury the circuit in optimal locations on the semiconductor substrate. good.

[0034] There is a similar method called super integration, which uses mask data as
This is a method of creating a single chip by arranging data from multiple existing chips and interconnecting them, but with this method, each chip cannot be made into a single chip unless it can be manufactured by the same process, and originally When integrating chips made using different processes into a single chip, it is necessary to develop a hybrid process that combines each process.
The process becomes extremely complex, and it becomes extremely difficult to develop a process that satisfies the performance of each chip. Therefore, in the semiconductor integrated circuit of the present invention, each mounted integrated circuit chip is manufactured with high performance through an optimal process. Since they are mounted on a single semiconductor substrate and connected using multilayer metal wiring technology, there is no need to develop a special mixed wafer process, and an extremely long development period is not required. (3) Since printed boards and packages are no longer required, and a long and complicated wafer process is no longer necessary, a low-cost circuit system can be realized.

(4) By using LSI's fine multilayer metal wiring technology for wiring between chips, the circuit system can be divided when developing a new chip, and there is virtually no limit on the number of pins when converting to LSI. . This expands the degree of freedom in circuit system design and has a significant effect on improving performance. There is no need for multiplexing to reduce the number of pins on the package, and the number of bits and number of address/data buses can be freely adjusted. For example, a 64-bit wide address bus and data bus may be connected to a high speed cache memory and a CPU, respectively.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of a semiconductor device according to the present invention, in which A is a cross-sectional view, B is a cross-sectional view, C is a schematic plan view of the semiconductor device, and D is a schematic plan view of a semiconductor integrated circuit chip.

FIG. 2 shows another embodiment of the semiconductor device according to the present invention,
A is a sectional view, B is a sectional view.

FIG. 3 shows an embodiment of a semiconductor device according to the present invention;
B is a cross-sectional view, and C is a schematic plan view of the semiconductor device.

FIG. 4 shows an embodiment of a semiconductor device according to the present invention;
B is a sectional view, and C is a schematic plan view of the semiconductor integrated circuit chip.

FIG. 5 is a plan view showing an application example of the semiconductor device according to the present invention.

FIG. 6 is a plan view showing an application example of the semiconductor device according to the present invention.

[Explanation of symbols]

1... Semiconductor substrate, 2-1 to 2-3... Semiconductor integrated circuit chip, T1, T2... MOS transistor.

Claims (12)

[Claims] 1. A semiconductor comprising a semiconductor substrate, a plurality of semiconductor chips arranged above the semiconductor substrate, an insulating layer embedding the plurality of semiconductor chips, and a wiring layer connecting the plurality of semiconductor chips. Device. 2. The semiconductor device according to claim 1, wherein an integrated circuit is formed on the semiconductor substrate. 3. The semiconductor device according to claim 2, wherein the plurality of semiconductor chips and the integrated circuit formed on the semiconductor substrate are formed in separate processes. 4. The semiconductor device according to claim 1, wherein at least one of the plurality of semiconductor chips is formed in a process different from that of other semiconductor chips. 5. The semiconductor device according to claim 1, wherein a recess is formed on the surface of the semiconductor chip, and the recess has a depth and extent depending on the area and thickness of the semiconductor chip. 6. The semiconductor device according to claim 1, wherein an object having a higher physical strength than the semiconductor substrate is adhered to the back surface of the semiconductor substrate opposite to the side on which the semiconductor chip is formed. . 7. An electrical insulator provided on a single semiconductor substrate in a region including one or more individual semiconductor chips and between the chips; On the other hand, a semiconductor device comprising a wiring layer for connection, wherein the individual semiconductor chips are made sufficiently thinner than the semiconductor substrate and arranged on the semiconductor substrate. 8. The semiconductor device according to claim 7, wherein an integrated circuit is formed also on the semiconductor substrate itself. 9. The semiconductor device according to claim 8, wherein a process for manufacturing the semiconductor chip is different from a process for manufacturing an integrated circuit of the semiconductor substrate. 10. The semiconductor device according to claim 8, wherein at least one of the plurality of semiconductor chips uses a different chip manufacturing process from other semiconductor chips. 11. A semiconductor device characterized in that the space between the semiconductor chips and the bottom of a second metal wiring layer is covered with an insulating resin film and flattened. 12. The semiconductor device according to claim 7, wherein the wiring layer is formed by photolithography.