JPS6272145A - Mos integrated circuit device and manufacture thereof - Google Patents

Abstract

PURPOSE:To reduce the wiring capacities of the wiring regions without being affected by any bird's beak even in a case where the the integration degree of the titled device is enhanced as well as to improve the high-speed operating characteristics of the device by forming an insulating film thicker than element isolation layers in the wiring region part on the silicon substrate. CONSTITUTION:A first oxidation-resistant film 31 to cover the whole of an element region part 1 is formed (a) on a silicon substrate 20. After that, wiring region parts 3 only are selectively heat-oxidized and silicon dioxide films having a thick film thickness are formed, and the oxidation-resistant film 31 is peeled (b). Then, a second oxidation-resistant film 32 is formed (c) on the silicon substrate 20 within the extent to cover the element parts only which are source drain and gate parts of an MOS transistor arranged at the element region part 1. Thereafter, when element isolation layers 22 are formed by performing a selective oxidation, the oxide films of the wiring regions 3 are simultaneously re-oxidized and thick oxide film insulating layers 21 are formed (d). The film thickness of the element isolation layers 22 may be a film thickness enough to perform an interelement isolation. That is, wiring layers are primarily formed on the thick oxide film insulating layers 21, whereby wiring capacities CW of the wiring regions can be lessened. Accordingly, an element can be made to carry out a high-speed operation at high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a MOS integrated circuit device, such as a large-scale logic integrated circuit, and a method for manufacturing the same.

[Technical background of invention m]

A MOS integrated circuit device using MOS transistors is formed by orienting an element region and a wiring region on a chip. The element area is an area required for constructing a functional gate section using MOS transistors, and the wiring area is an area required for wiring interconnecting gates.

By the way, in large-scale logic integrated circuits (hereinafter referred to as logic LSIs), the area occupied by the distribution area on the chip is generally overwhelmingly larger than the area occupied by the element area, for example, the proportion occupied by the wiring area is 60 to 70%. It also becomes. As described above, increasing the scale of integrated circuits increases the number of gates integrated on one chip, increases the total number of wiring lines and the average wiring length, and as a result, increases the wiring area and increases the chip size.

In response to this tendency toward enlargement, the multilayer metal wiring process allows flexibility and freedom in wiring, and is widely adopted in custom LSI designs using electronic computer support, and is effective in preventing expansion of wiring areas. I'm giving. For example, in a gate array, the connection wiring between the gates is a multilayer metal wiring of the first layer aluminum and the second layer aluminum within a fixed wiring area, and in the standard cell method, the connection wiring between the gates is a multilayer metal wiring of the first layer aluminum and the second layer aluminum. In addition to aluminum wiring, multilayer metal wiring including a polysilicon wiring layer may also be used.

However, even if we try to reduce the wiring area by making full use of the wiring technology using the multilayer metal wiring process described above,
Gate array or standard cell method using current typical CMOS bus process (2.0μ rule)
In SI, the average wiring length is 2Illff per net.
Reach i.

Therefore, the wiring capacitance has a large value, and the ratio of the wiring layer H) to the total load capacity jjl of one gate is large. For example, the dielectric constant ε of silicon dioxide, which is an insulating film, is 3
．． 9. Wire capacitance C between silicon substrates for a wire with a wire length of 21111 when gllil is 1.0 μm and wire width is 2 μm
When W is determined using a parallel plate model, Cw is approximately 0.1
It becomes 4pF.

On the other hand, the gate capacitance c6 of the MOS transistor is calculated by setting the average fan-out number to 3, the thickness of the gate oxide film to 500 layers, the gate width to 2.0 layers, and the total gate of the PDP channel and N channel MOS transistor. Even if the length is 80 μm, CIL4 is approximately 0.11 pF. That is, 1
It can be seen that the wiring capacitance accounts for about 60% of the total load capacitance of the gate. Note that the above ratio does not change even if the MOS integrated circuit is scaled in two or three dimensions, and the layout E is a dominant factor in gate delay.

By the way, in order to speed up a logic LSI, the method is to reduce the above-mentioned wiring capacitance.

Conventionally, as a method for this purpose, an SO8 structure, for example, in which an element is constructed on an insulating substrate has been proposed. However, sapphire substrates are expensive, and although it is an effective technique for reducing wiring capacity j, it has not been common.

Therefore, Mo
In 8-inch LSIs, attempts have been made to increase the thickness of the insulating film between the silicon substrate and the wiring.

When manufacturing a silicon gate Mo8 type LSI, a selective oxidation method called Kobusina method or Shiacos is used as the element part 11WlJ method.

This method protects the source, drain, and gate regions of a MOS transistor with an oxidation-resistant film, and selectively thermally oxidizes the inter-element region, which serves as the wiring region. The insulating film is grown appropriately by adjusting the temperature to increase the thickness of the insulating film.

[Problems with background technology]

However, when the lil thickness of silicon dioxide is increased using the above-mentioned conventional technique, there is a problem in that the oxide film digs into the device region, which is called a bird's beak, and as a result, the device region is narrowed. Furthermore, when reducing the element spacing in order to increase the degree of integration of an integrated circuit, it becomes necessary to suppress the bird's beak, and as a result, there is a restriction that the thickness of the silicon dioxide film cannot be increased.

For this reason, the wiring layer Φ could not be reduced, which was a major hindrance to realizing a Mo8 type LSI capable of high-speed operation.

(Objective of the Invention) The present invention has been made to overcome the problems of the prior art described above, and therefore reduces wiring capacitance without impairing the degree of integration.
MOS integrated circuit device with excellent high-speed operation and its! l
The purpose is to provide a manufacturing method.

[Summary of the invention]

To achieve the above object, the present invention provides a MOS integrated circuit device in which the thickness of an oxide film insulating layer formed in a wiring region on a silicon substrate is greater than the thickness of an element portion 111 layer in an element region. It is something.

The present invention also provides a method for manufacturing a MOS beam stack circuit device, which includes a step of re-oxidizing only the wiring region in addition to the step of oxidizing the wiring region and the element isolation region of the element region. .

(Embodiments of the Invention) The present invention will be described in detail below with reference to FIGS. 1 to 5 of the accompanying drawings.

FIGS. 1 and 2 show an example of a MOS designed using a gate array or standard cell method.
The element area and wiring area of the integrated circuit device 2 are schematically shown, with FIG. 2 being a partial plan view and FIG. 1 being a cross-sectional view taken along the line AA'.

In FIG. 2, an element region 1 has Mo8 L-transistors arranged in a high-density layout and logic gates arranged therein, and a diffusion region 2 of the MoS transistor forms the element parts, which are the source, drain, and gate parts. . Wiring area section 3
In this case, connection wiring between logic gates is performed using multilayer metal wiring. Multilayer metal wiring is typically made of aluminum.
Although it depends on the layer wiring, there is also a case where a three-layer wiring including a polysilicon wiring layer is used. The polysilicon wiring layer 4 and the first aluminum arrangement i1 layer 5 are formed in the wiring region section 3, and the second aluminum wiring layer 6 is formed in the element region section 1. These A layers 4, 5.6 are connected to each other via contact holes 7 and through holes 8.

The cross-sectional structure of the vt position shown in FIG. 2 is as shown in FIG. That is, the oxide film insulating layer 2 in the wiring region portion 3
1 is larger than the thickness of the element isolation layer 22 in the element region portion 1. Accordingly, the wiring layer 4.5 shown in FIG. 2 is mainly formed on this thick oxide film insulating layer 21. Therefore, the wiring capacitance C8 can be reduced, and therefore the device can operate at high speed.

Next, a first example of the iTh manufacturing process will be described with reference to the step-by-step sectional views in FIG.

First, as shown in FIG. 3(a), the entire element region 1 (second
The first oxidation-resistant l! 31 is formed on the silicon substrate 20. After that, Fig. 3(b)
A thick silicon dioxide film having a desired thickness is formed in the wiring region 3 by selectively thermally oxidizing only the wiring region 3 as shown in FIG. Then, the first oxidation-resistant film 31 is peeled off.

Next, as shown in FIG. 3(C), a region that covers only the element portion (the portion indicated by reference numeral 2 in FIG. 2), which is the source, drain, and gate portion of the MOS t-transistor disposed in the element region 1, is formed. A second oxidation-resistant layer 132 is formed on the silicon substrate 20 (in the area indicated by reference numeral 10 in FIG. 2). After that, selective oxidation is performed to form the element part m layer 2 as shown in FIG. 3(d).
2 is formed and element isolation is performed. At this time, the oxide film in the wiring region 3 is simultaneously reoxidized to form a thick oxide film insulating layer 21. Note that the element molecule 111 layer 22 may have a thickness sufficient to provide isolation between elements.

According to the method of this embodiment, even when the element spacing is narrowed in order to increase the integration density of the MOS integrated circuit, the element region portion 1
In this case, only the thin silicon dioxide film mentioned above performs element isolation, and there is no adverse effect caused by bird's beak. In addition, during the second selective oxidation for element isolation, the wiring region 3 is also oxidized, so the silicon dioxide pattern formed in the wiring region 3 grows even thicker, and the silicon dioxide pattern formed in the wiring region 3 grows thicker. The wiring capacitance CW of the wiring can be reduced.

In the above embodiment, after removing the oxidation-resistant film 31 of the element part 1i11, the 1liil film 32 is formed on the element part, but the oxidation-resistant film 31 of the element part 1ii1 is patterned and The oxide film 32 may be formed to remain only on the surface.

Next, a second example of the manufacturing process will be explained with reference to FIG. This differs from the first example in that the element layer is formed in the previous step.

First, as shown in FIG. 4(a), an oxidation-resistant film 33 is formed only on the element portion in the element region 1 on the silicon substrate 20, and a fourth
Thermal oxidation is performed as shown in Figure (b).

Next, as shown in FIG. 4C, after removing the oxidation-resistant film 33, an oxidation-resistant film 34 covering the element region 1 is formed. After that, when thermal oxidation is performed, the wiring layer hi3 is formed as shown in FIG. 4(d).
Only the oxide film is reoxidized, and a single oxide film insulating layer 21 is formed.

In the above embodiment, the oxidation resistant film 34 is formed in the element region 1 after removing the oxidation resistant 11233 from the element portion, but the oxidation resistant film 33 is left and i
'f1 oxide film 34 may be formed.

Although the manufacturing method according to the present invention has been described above in detail according to Examples, the present invention is not limited thereto.

As for f5, any material may be used as long as a thick insulating film is formed in the wiring region on the silicon substrate and an element structure is formed in the element portion of the element region. Also, the fifth
As shown in the figure, the oxide film having a wavelength of λ9 may not be provided in the portion adjacent to the wiring region. However, in this case, problems such as disconnection of the wiring layer may occur.

(Effects of the Invention) As described above, in the present invention, the wiring layer Vi on the silicon substrate,
is+: Since an insulating film is formed that is thicker than the element isolation layer, the wiring capacitance in the wiring area can be reduced without being affected by bird's beak even when the degree of integration is increased, thus achieving high-speed operation. A unique MOS integrated circuit device and its manufacturing method! ? can be done.

[Brief explanation of drawings]

FIG. 1 is a partial cross-sectional view of a MOS integrated circuit device according to an embodiment of the present invention, FIG. 2 is a partial plan view of an integrated circuit device according to the same embodiment, and FIGS. 3 and 4 are respectively according to the present invention. FIG. 5 is a cross-sectional view of a MOSO8 integrated circuit device according to another embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Element region part, 2... Element part of MOS t-transistor, 3... Wiring region part, 4... Polysilicon wiring layer, 5... First aluminum wiring layer, 6...・
・Second aluminum wiring layer, 9...Position where first oxidation resistant film is formed, 10...Position where second oxidation resistant film is formed, 20...Silicon substrate, 31.34 ...
First oxidation resistant l19.32.33...Second oxidation resistant film. Applicant's agent Fi Fuji - Yu 63 Figure 5 z Mo 4 Ro

Claims (1)

[Claims] 1. In a MOS integrated circuit device formed on a silicon substrate having an element region and a wiring region, the thickness of an oxide film insulating layer formed on the silicon substrate in the wiring region is , a MOS integrated circuit device characterized in that the thickness is greater than the thickness of the element isolation layer in the element region. 2. In a method of manufacturing a MOS integrated circuit device formed on a silicon substrate and having an element region and a wiring region, the first step includes covering the element region with an oxidation-resistant film and forming an oxide film on the wiring region. and a second step of covering the element portion of the element region with an oxidation-resistant film to oxidize the element isolation layer and re-oxidize the wiring region. Method. 3. The method of manufacturing a MOS integrated circuit device according to claim 2, wherein the element portions covered with the oxidation-resistant film in the second step are the source, drain, and gate portions of a MOS transistor. 4. The oxidation of the wiring region in the first step, the oxidation of the element isolation layer and the re-oxidation of the wiring region in the second step are all performed by thermal oxidation. A method of manufacturing a MOS integrated circuit device. 5. Claim 2, wherein the second step includes the step of removing the oxidation-resistant film formed in the first step and then covering the element portion of the element region with another oxidation-resistant film. A method of manufacturing the described MOS integrated circuit device. 6. In a method for manufacturing a MOS integrated circuit device formed on a silicon substrate and having an element region and a wiring region, the element portion of the element region is covered with an oxidation-resistant film to prevent oxidation of the element isolation layer and the wiring. a first step of oxidizing the region;
a second step of covering the element region with an oxidation-resistant film and reoxidizing the wiring region.
A method of manufacturing an integrated circuit device. 7. The method of manufacturing a MOS integrated circuit device according to claim 6, wherein the element portions covered with the oxidation-resistant film in the first step are the drain/source and gate portions of a MOS transistor. 8. The MOS integrated circuit device according to claim 6, wherein the oxidation of the element isolation layer and wiring region in the first step and the re-oxidation film of the wiring region in the second step are performed by thermal oxidation. manufacturing method. 9. The MOS according to claim 6, wherein the second step includes a step of removing the oxidation-resistant film formed in the first step and then covering the element region with another oxidation-resistant film.
A method of manufacturing an integrated circuit device.