JPH02113554A - Wiring structure of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce a capacitance generating between a wiring and a semiconductor substrate without increasing the thickness of an oxide film by constituting a part of the oxide film for element isolation by using a thick insulating film, and forming a part of wiring on the insulating film. CONSTITUTION:A part of an oxide film 13 for element isolation formed on a semiconductor substrate 11 is constituted by using a thick insulating film 14, and at least a part of a wiring 16 formed on the oxide film 13 is formed on the insulating film 14. That is, it is not necessary for all wiring to be formed on the thick insulating film 14, and only the wiring whose parasitic capacitance becomes a serious problem is formed thereon. By this set-up, the capacitance between the semiconductor substrate 11, the first wiring 16 and a second wiring 18 scarcely changes, when the thickness of the oxide film between the semiconductor substrate and the wiring is changed. Only the capacitance of large value between the first wiring and the semiconductor substrate decreases remarkably, so that the parasitic capacitance can be reduced without reducing the surface area of the first wiring 16. Thereby, a thick insulating film can be formed without affecting miniaturization, and the reduction of parasitic capacitance is enabled.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of a semiconductor integrated circuit, and particularly to a wiring structure in which parasitic capacitance of wiring is reduced.

[Conventional technology]

Conventionally, wiring of a semiconductor integrated circuit is formed on an insulating film for isolation between elements or a glabella insulating film formed on a semiconductor substrate. FIG. 5 shows, as an example, a cross-sectional view including elements and wiring of a bipolar integrated circuit in which an oxide film is used as an element isolation film. In the figure, 11 is a semiconductor substrate, 12 is an epitaxial growth layer, an element region is defined by an oxide film 13 for isolation between elements, and a bipolar transistor 15 is formed in this element region.
is formed. Then, a first wiring 16 made of aluminum or the like is formed on the oxide film 13, and this is connected to the glabella insulating film 17.
The second wiring 18 is formed after being coated with . 19 is a protective insulating film.

Note that the oxide film 13 is normally formed to be slightly thicker than the epitaxial growth 1112.

[Problem to be solved by the invention]

Incidentally, semiconductor integrated circuits in recent years are required to operate at high speed. In particular, in active elements formed in integrated circuits, efforts are being made to reduce parasitic capacitance and parasitic resistance, increase cut-off frequency, and increase speed by miniaturizing dimensions and making PN junctions shallower. However, even if the dimensions of the device become smaller, the current required for high-speed operation must be large, and therefore the wiring width cannot be reduced below the width required to ensure electromigration resistance. It is.

On the other hand, as the above-mentioned elements become faster to operate, signal delays inside the chip due to wiring loads cannot be ignored. The wiring load is determined by the resistance of the wiring itself and the parasitic capacitance generated in the wiring, and it is necessary to reduce these. In particular, the wiring capacitance is related to the surface area of the wiring, and by reducing this surface area, the parasitic capacitance can be reduced. However, reducing the surface area increases interconnect resistance and also deteriorates electromigration resistance.

Therefore, instead of reducing the surface area, attempts have been made to reduce the capacitance by increasing the distance between wires or between the wires and the semiconductor substrate, or in other words, by increasing the thickness of the insulating film that insulates the two. . However, when the insulating film is made thicker, it becomes difficult to form the insulating film into a fine pattern or to microfabricate it by etching, etc., which prevents the miniaturization of devices from being promoted and leads to the problem of high-speed characteristics deterioration of the device. There is.

An object of the present invention is to provide a wiring structure for a semiconductor integrated circuit that enables the formation of a thick insulating film without impairing miniaturization and reduces parasitic capacitance.

[Means to solve the problem]

In the wiring structure of the semiconductor integrated circuit of the present invention, a part of the oxide film for element isolation formed on the semiconductor substrate is composed of a thick insulating film or an insulating film with a small dielectric constant, and the wiring formed on the oxide film is At least a portion of the insulating film is formed on the insulating film.

[Effect]

In the above structure, the distance between the wiring on the insulating film formed on a part of the oxide film and the semiconductor substrate is electrically increased without increasing the thickness of the oxide film, and the capacitance generated between the two is reduced. reduce

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a longitudinal sectional view of a first embodiment of the present invention, showing an example in which the present invention is applied to a bipolar integrated circuit.

In the figure, an epitaxial growth layer 12 is formed on a semiconductor substrate 11, and an element region is defined by a thick oxide film 13 for isolation between elements. At this time, an insulating film 14 that is thicker than the oxide film 13 is formed at a portion of the oxide film 13 where wiring is to be formed.

The thick insulating film 14 is made of a silicon oxide film here, and is formed, for example, by the following method. That is, the semiconductor substrate 11 after forming the epitaxial growth layer 12
On the other hand, only the area where the thick insulating film 14 is to be formed is selectively etched to a required depth. On top of that, a silicon oxide film that is sufficiently thick relative to the depth is grown using chemical vapor deposition (C
VD method) etc. A desired shape can then be obtained by polishing the surface and removing unnecessary silicon oxide films.

After this, an oxide film 1 for isolation between devices is formed using a selective oxidation method similar to the conventional method, etc., to suit the thickness of the epitaxial growth layer 12.
form 3. A bipolar transistor 1 is formed in the device region defined by this oxide film 13 by a known method.
form 5.

Then, a first wiring 16 made of a conductive material such as aluminum and formed in a desired pattern is formed on the thick insulating film 14. In this case, it is not necessary to form all the wirings on the thick insulating film 14, and it is sufficient to form only the wirings where parasitic capacitance is a particular problem.

Note that 17 is an insulating film between the eyebrows, 18 is a second wiring, and 19 is a protective film.

FIG. 2 is a perspective view schematically showing the wiring portion of the semiconductor integrated circuit shown in FIG. 1, and parts corresponding to those in FIG. 1 are given the same reference numerals. In the wiring structure modeled in this way, the semiconductor substrate 11 when the oxide film thickness between the semiconductor substrate and the wiring is changed. First wiring 16. FIG. 3 shows the results of calculating the change in capacitance between the second wirings 18.

From this figure, when the thickness of the oxide film between the semiconductor substrate and the wiring increases by 1.5 times, the C+-sum (capacitance between the first wiring and the semiconductor substrate) component decreases by 26%, and when t further doubles, it decreases by 41%.
% decrease. Also, at this time, the capacitance C+-+ between interconnects in the same layer (capacitance between adjacent first interconnects).

C2-□ (capacitance between adjacent second wirings), and capacitance between different layer wirings C+-z (capacitance between first wiring and second wiring).

It can be seen that CC2-5u (second wiring-semiconductor substrate capacitance) hardly changes, and only the Cl-3LIII component, which has a large capacitance value, decreases dramatically.

Therefore, the parasitic capacitance can be reduced without particularly reducing the surface area of the first wiring 160. In addition, at this time, the thick insulating film 1
4 is formed in a separate process from the oxide film 13 for isolation between elements, so the thickness of the oxide film 13 for isolation between elements can be kept to the minimum necessary thickness, making @ fine processing of elements possible. do.

FIG. 4 is a longitudinal cross-sectional view of a second embodiment of the present invention, in which the same or equivalent parts as in FIG. 1 are given the same reference numerals.

In this embodiment, the surface of the region where the first wiring 16 is to be formed in the oxide film 13 for element isolation is made of a material 20 with a low dielectric constant. Organic materials such as polyimide are used as this material. Further, this material 20 is applied to the oxide film 13 after forming elements such as the bipolar transistor 15.
It can be formed by etching the surface in the depth direction and embedding it in the formed recess by a coating method or the like.

According to this configuration, the electrical distance between the semiconductor substrate 11 and the first wiring 16 can be increased by the material 20 having a low dielectric constant, and the capacitance generated between the two can be reduced. Furthermore, in reality, the thickness of the oxide film 13 is the same as before, and fine processing is not hindered.

In particular, when the present invention is applied to a gate array type semiconductor integrated circuit consisting of an element region and a wiring channel region, by applying the present invention structure to the channel region, it is possible to It becomes possible to reduce the wiring capacitance without imposing layout restrictions.

[Effects of the Invention] As explained above, the present invention consists of a part of the oxide film for element isolation made of a thick insulating film or an insulating film with a small dielectric constant, and has a small number of interconnections (some of which are made of this insulating film). Since it is formed on a film, it is possible to electrically increase the distance between the wiring on the insulating film formed on a part of the oxide film and the semiconductor substrate without increasing the thickness of the oxide film, and to increase the distance between the two. This makes it possible to realize microfabrication of the oxide film and miniaturize the integrated circuit, while reducing the parasitic capacitance of the wiring and achieving faster operation.

[Brief explanation of the drawing]

FIG. 1 is a vertical cross-sectional view of the first embodiment of the present invention, and FIG.
FIG. 3 is a diagram showing the relationship between the thickness of the oxide film and the parasitic capacitance, and FIG. 4 is a vertical cross-section of the second embodiment of the present invention. The plan view and FIG. 5 are longitudinal cross-sectional views of a conventional wiring structure. DESCRIPTION OF SYMBOLS 11... Semiconductor substrate, 12... Epitaxial growth layer, 13... Oxide film for isolation between elements, 14... Thick insulating film, 15... Bipolar transistor, 16...
First wiring, 17... Interlayer insulating film, 18... Second wiring, 19... Protective film, 20... Low dielectric constant material, Fig. 2

Claims (1)

[Claims] 1. Define elements on a semiconductor substrate with an oxide film for element isolation,
In a semiconductor integrated circuit in which various elements are formed in this element region and wiring is formed on the oxide film, a part of the oxide film is formed of a thick insulating film or an insulating film with a small dielectric constant. . A wiring structure for a semiconductor integrated circuit, wherein at least a part of the wiring is formed on the insulating film.