JPS6249734B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of a semiconductor integrated circuit device (IC), and particularly to the structure of wiring in a high-speed, highly integrated IC using a semi-insulating semiconductor substrate.

In highly integrated semiconductor ICs, the chip size generally becomes larger and the length of the power supply wiring becomes longer. Therefore, the self-inductance and resistance of the wiring increases, and the power source impedance increases at the power receiving end (the part to which the logic element is connected), making it susceptible to induction of noise and the like.

As a result, problems such as (1) slow switching speed, (2) failure of normal switching operation, and (3) malfunction occur. To improve this point, you can lower the power supply impedance by inserting bypass capacitors at important points in the power supply wiring. Therefore, in conventional MOSICs and bipolar ICs that use relatively low-resistance semiconductor substrates such as silicon (Si), regions of different conductivity types are provided on the upper surface of the substrate, and a power source is directly connected to the regions of different conductivity types. A method of wiring is generally used. In this method, a depletion layer in the PN junction is created by applying a potential between the power supply wiring and the substrate so that the PN junction formed between the different conductivity type region and the substrate is biased in the opposite direction. The capacitance generated by the expansion of the
Since it contributes as a capacitor, the power source impedance decreases.

However, recently, semiconductors developed for high speed
In the case of an IC, the above means cannot be effectively applied because the IC is formed on a semi-insulating semiconductor substrate. Therefore, in high-speed ICs using semi-insulating substrates, in order to lower the power supply impedance, it is necessary to resort to widening the power supply wiring or shortening its length. The problem was that it was extremely difficult to realize an IC with high integration (high density, large area).

In order to eliminate the above-mentioned problems, the present invention provides a wiring structure having reduced impedance that can be formed on a semi-insulating semiconductor substrate.

That is, the present invention provides a semiconductor IC using a semi-insulating semiconductor substrate, in which a low resistivity region is provided in the semi-insulating semiconductor substrate, and a first wiring electrode and an insulating film that are in direct contact with the low resistivity region are provided on the semi-insulating semiconductor substrate. a second wiring electrode is provided on the insulating film adjacent to the first wiring electrode,
A feature is that the capacitance of the insulating film between the low resistivity region and the second wiring electrode is used as a bypass capacitor for the second wiring electrode.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the figures.

1A and 1B are partial cross-sectional views for explaining the functions of the present invention, FIGS. 2A to 2F are process cross-sectional views of an embodiment of the method for forming the structure of the present invention, and FIGS. FIG. 4 is a schematic perspective view of a different embodiment, FIG. 5a is a schematic perspective view of another embodiment,
FIG. 5b is a sectional view taken along the line A-A', FIG. 6a is a schematic perspective view of another embodiment, and FIGS. FIG.

In the structure of the present invention, for example, as shown in FIG ^. 2 is provided, and a first wiring electrode 3 made of gold germanium/gold (AuGeAu) or the like is formed on a part of the upper surface of the N ⁺ type region 2 and has a relatively wide area and is in direct contact with the region. An insulating film 4 such as silicon dioxide (SiO ₂ ) is formed on the first wiring electrode 3 and the N ⁺ type region 2 to cover them, and the first wiring electrode 3 is formed on the insulating film 4. One or two second wiring electrodes 5 or 5a, 5b made of titanium/platinum/gold (Ti/Pt/Au) or the like are formed adjacent to the electrodes. In the above structure, for example, when the first wiring electrode 3 is grounded and the desired drive power supplies B, Ba, and Bb are connected to the second wirings 5, 5a, and 5b, the first wiring electrode 3 is grounded. Capacitances C, Ca, and Cb commensurate with the dielectric constant and thickness of the insulating film are formed between the N ⁺ type region 2 ohmicly connected to the first wiring electrode 3 and the second wirings 5, 5a, and 5b. . Therefore, these second wirings 5, 5a,
5b is grounded by the bypass capacitor made of the above-mentioned capacitance, and the impedance of the wiring is reduced.

Although the structure of the present invention has the above functions,
When forming this structure, there is no need to add particularly complicated steps compared to the conventional method. Next, an example of the method will be explained in order of steps along FIGS. 2a to 2f.

Figure 2a shows that, for example, silicon ions (Si ⁺ ) are selectively implanted onto the surface of a semi-insulating GaAs substrate 11 using a SiO ₂ film or the like as a mask at an energy of 54 [KeV] and an implantation force of 54 [KeV].
After implantation under conditions of approximately 1.08×10 ¹² [atm/cm ² ], the substrate surface is covered with a SiO ₂ film, etc., and annealing treatment is performed at approximately 800 [°C] to form an N-type active material in which devices are to be provided. A state in which a region 12 is formed is shown.
Next, FIG. 2b shows a state in which a shot gate electrode 13 made of titanium/tungsten (TiW) silicide or the like is formed on the N-type active region 12 using a conventional sputtering method and plasma etching method. Next, FIG. 2c shows that the substrate has a window that exposes the N ⁺ region forming surface and the active region surface used in the wiring structure of the present invention.
A SiO ₂ film or the like is formed, and the injection energy is 175 (KeV) and the implantation amount is 1.7×10 ¹³ [ _atm /
After selectively implanting Si ⁺ under conditions of approximately 1 cm ² ], the same annealing process as described above is performed to form an N ⁺ type source region 14 and an N ⁺ type drain region 1 in the active region 12.
5 and 1×10 ¹⁸ on the upper surface of the GaAs substrate 11.
A state in which an N ⁺ type region 16 having a Si peak concentration of about [atm/cm ³ ] is formed is shown. Note that in this state, an FET is formed in the active region. Next, FIG. 2b shows that a source electrode 17 and a drain electrode 18 made of, for example, gold germanium/gold are formed on the source and drain regions by sequentially using a conventional photo process, vapor deposition, and lift-off method, and also on the N ⁺ type region. 16 shows a state in which a first wiring electrode 19 is formed on top of the wiring electrode 16. Note that these electrodes are subjected to an alloying process at about 450 [° C.] in order to establish ohmic connection with the underlying semiconductor layer. Next, FIG. 2e shows a state in which, for example, a SiO ₂ film 20 is formed to cover the electrodes using a chemical vapor deposition (CVD) method or the like. Next, as shown in FIG. 2f, after forming desired through holes in the SiO ₂ film 20 by plasma etching or the like, Ti/Ti/N film is formed on the SiO ₂ film 20 through processes such as sputtering and ion milling.
The source electrode 1 has a three-layer structure such as Pt/Au.
7, a drain wiring 22 in contact with the drain electrode 18, and a power supply wiring 23 are shown. Note that the power supply wiring 23 connected to the drain wiring 22 is formed in the upper region of the N ⁺ type region 16. Therefore, the power supply wiring 2
3, that is, the second wiring electrode has an N ⁺ type region that is ohmicly connected to the ground electrode, that is, the first wiring electrode 19;
The structure is bypassed by a capacitor having the SiO ₂ film 20 as a dielectric layer.

Next, an embodiment in which the structure of the present invention is applied to a high-speed IC will be described using a schematic perspective plan view and a cross-sectional view of a main part.

Figure 3 shows the power supply wiring (e.g. ground electrode) in Figure 1.
31 is formed widely (low impedance shape),
This is an embodiment of a single power supply IC in which a single second power supply wiring (for example, power supply wiring) 32 is provided adjacent to this and above an N ⁺ type region 33. And 31', 3 in the figure
2' is a branch wiring, 34a to 34x are unit circuits, B is a drive power supply, and G is a ground.

Figure 5a shows an embodiment of a single power supply IC in which first wiring electrodes are provided at two locations, each wiring electrode is used as a ground electrode or a drive power supply electrode, and a bypass capacitor is interposed between the two main parts. FIG. 5b is a sectional view taken along the line A-A'. In the figure, 31a and 31b are first wiring electrodes, 31a' and 31b' are control lines, and 32a and 32
b is a second wiring electrode, 33a and 33b are N ⁺ type regions, 34a to 34x are unit circuits, and 35 is SiO ₂
36 is a through hole, B is a driving power supply, and G is a ground. Note that in this structure, the first wiring electrode 3
1a and 31b are formed in the lower layer, and these first wiring electrodes are connected to the second wiring electrode 23a on the other N ⁺ type region by branch wirings 31a' and 31b' led out to the upper layer through the through hole 36. Alternatively, it is connected to 32b.

In Figure 6a, N ⁺ type regions are provided at two locations, first wiring electrodes connected to each other are provided in the lower layer above both N ⁺ type regions, and second wiring electrodes connected to each other are provided at both locations. This is a perspective plan view schematic diagram of an embodiment of a single power supply IC in which a bypass capacitor is provided in the upper layer above the N ⁺ type region, and FIGS. 6b and 6c are B. -B' and CC' arrow sectional views. In the figure, 31a and 31b are first wiring electrodes, 31' are branch wirings thereof, 32a and 32b are second wiring electrodes, 32' are branch wirings, 33a,
33b is an N ⁺ type region 34a to 34x is a unit circuit;
35 is a SiO ₂ film, B is a drive power supply, and G is a ground.

As explained above, by applying the structure of the present invention, it is extremely easy to add a bypass capacitor to the power supply wiring in a high-speed IC formed using a semi-insulating semiconductor substrate such as GaAs.

Therefore, according to the present invention, a highly integrated high-speed semiconductor with high switching speed and no malfunction can be realized.
IC can be formed.

[Brief explanation of the drawing]

1A and 1B are partial cross-sectional views for explaining the functions of the present invention, FIGS. 2A to 2F are process cross-sectional views of an embodiment of the method for forming the structure of the present invention, and FIGS. FIG. 4 is a schematic perspective view of a different embodiment, FIG. 5a is a schematic perspective view of another embodiment,
FIG. 5b is a sectional view taken along the line A-A', FIG. 6a is a schematic perspective view of another embodiment, and FIGS. FIG. In the figure, 1 is a semi-insulating semiconductor substrate, 2, 3
3, 33a, 33b are N ⁺ type regions, 3, 31, 3
1a and 31b are first wiring electrodes, 4 is an insulating film,
5, 32, 32a, 32b are second wiring electrodes, 3
1', 31a', 31b', 32', 32a', 32b' are branch wirings, 34a to 34x are unit circuits, 35 is a silicon dioxide film, 36 is a through hole, C, Ca,
Cb is the capacitance, G is the ground, and B, Ba, Bb, -B are the drive power supplies.

Claims (1)

[Claims] 1. In a semiconductor integrated circuit device using a semi-insulating semiconductor substrate, a first wiring electrode and an insulating film formed directly on a low resistivity region, and a first wiring electrode and an insulating film formed on the insulating film and the first wiring electrode formed directly on the low resistivity region. The second electrode adjacent to the wiring electrode of
1. A semiconductor integrated circuit device comprising a wiring electrode.