JPS5864048A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain a wiring structure having a low impedance by forming the first wiring electrode contacted directly with a low specific resistance region formed on a semi-insulating semiconductor substrate and an insulating layer, and employing as a bypass condenser of the second wiring electrode the capacity of the insulating film between the low specific resistance region and the second wiring electrode. CONSTITUTION:An N<+> type region 2 having a low specific resistance is formed on a semi-insulating semiconductor substrate 1 made of Gallium arsenide (GaAs) or the like is formed, the first wiring electrode 3 made of gold germanium/gold contacted directly with part of the upper surface of the region 2 is formed, an insulating film 4 made of silicon dioxide (SiO2) or the like which covers the electrode 3 and the region 2 are formed, and one or two second titanium/platinum/ gold wiring electrode 5 or 5a, 6b are formed adjacent to the electrode 3 on the film 4. When the electrode 3 is contacted with the ground G and desired drive sources B, Ba, Bb are connected to the second wirings 5, 5a, 5b, the dielectric constant of the insulating film and capacities C, Ca, Cb matched to the thicknesses are formed between the regions 2 and the wirings 5, 5a, 5b, which are grounded with the bypass capacitor, thereby decreasing the impedance.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit fit (IC)0 structure, and is a high-speed, highly integrated IC using a semi-insulating semiconductor substrate for n, *.
Regarding the wiring structure in k.

In highly integrated semiconductor ICKs, the chip size is generally large and the length of the power supply wiring is also long, so the self-inductance and resistance of the wiring become large, and the power receiving end (
(where logic elements are connected) [8 Impedance increases, so it becomes more susceptible to noise and other O-induction00 And as a result, (1) the switching speed increases1 (
Problems such as 2) failure of normal switching operation, and (3) malfunction may occur. To re-emphasize this point, it is sufficient to insert a bypass capacitor at the important point of the W# circuit to lower the voltage resistance. In eMO8IC and bipolar ICK, there are different types of conductors on the board and on the surface.
#IW1. A region is provided, and Kw is directly placed on the region of different conductivity type.
A method of applying m connections is generally used. In the nuclear force method, a potential is applied between the electrical wiring and the substrate so that the PN junction formed between the different conductivity type region and the substrate is biased in the opposite direction. The depletion layer expands and decreases. However, the above-mentioned method cannot be effectively applied to semiconductor ICs manufactured by ICk, which has recently been developed for high-speed applications, because the ICs are formed on semi-insulating semiconductor substrates.

Therefore, in high-speed ICE using semi-cell green substrates, in order to lower the W# impedance, it is necessary to resort to measures such as widening the width of the 1st line and shortening the length of the 1st line. It is extremely difficult to form a highly integrated yItC (high-density, large-area) RCT on a medium-insulating semiconductor substrate in order to eliminate the above-mentioned IiA. In other words, the present invention uses a semi-insulating semiconductor substrate and provides a wiring electrode with low specific resistance 2 on the semi-insulating semiconductor substrate in a stone semiconductor IC1r. , the capacitance f of the insulating film between the low resistivity region and the electrode 20 wiring 11i is characterized by being used as a bypass capacitor.Hereinafter, examples will be explained in detail using the present invention tat and g. - Figures 1 (Ji) and (b) are partial sectional views for explaining the functions of the present invention, and Figures 2 (a) to (fl are the 910 parts of the present invention).
A process sectional view of an embodiment of a method for forming a structure, a perspective plan view schematic diagram of a different embodiment of the 3rd cabinet and 411p,
Fig. 5 (Otori) is a perspective plan schematic diagram of another embodiment, 115
11(b) is a cross-sectional view taken from the direction of the arrow A', and FIG. 6(a) &
; iFurthermore, see-through plane 1iI schematic diagram of 〇1 Example% rattan 6 figure (
b) and U (Cud sot) B-B' and c-cl arrow section'
For example, in the structure shown in Figure 1 (a) or (b) K, the upper surface W & For example, an N''ll region 2 having a low specific resistance is provided, and a portion of the upper surface of the N+ type region 20 is directly connected to the region with a relatively large area of gold germanium (AuG). /Au) etc. 0@10 wiring voltage lk3 is formed, lj! 10th wiring voltage 11
3 and the above N, OI such as silicon dioxide (gins) covering these on region 2? After the hoe film 4 is formed, one or two titanium/platinum/gold (Tdoro/Pt/Au) wires are placed adjacent to the first wiring conductor 1Ik3 on the insulation film 4 IIc.
A second wiring electrode 5 or S to lb is formed.

In the above structure, for example, the IIEIO arrangement-electrode piping electrode 3, the second arrangement 418.5m, and the sb#c location m.

When the drive voltage 11B, Ha, Bb 841 is connected, the N which is orthically connected to the wiring electrode 3 of #B1 which has been replaced with G
+#IIJl area 2 and 8g2 wiring -5# At the junction of 5m and 5b, capacitance C-Catc commensurate with the dielectric constant and thickness of the insulating film.
b is formed.Therefore, these 20th wiring 5゜5ae5
b is replaced by a bypass capacitor consisting of a capacitance, and the impedance of the circuit decreases.

Although the structure of the present invention has the above-mentioned mechanical strength, V! When forming the structure, there is no need to add any particularly complicated process compared to the conventional method.
) to (f) #c along 9th process Ill K iiQ Mingsu h *Glue 2 & 1 (a) is selective # as an 81 can agricultural pipe mask on the 11th surface of the semi-insulating Gim S base glue! c For example, silicon ions (Sl'') are implanted with energy 54 (Key),
Injection amount 1.08X10”Catm/d]f1MPtt)
After implantation under the following conditions, the surface of the substrate is covered with an 810@ film layer and annealing treatment of approximately 800 (b) is performed to form an N-type active region 12 in which an element is to be provided. Then, as shown in FIG. 2(b), a silicon gate electrode made of titanium/tungsten (TOW) silicide or the like was formed on the NWA active region 12 using conventional sputtering and plasma etching methods. Figure 2 (C) shows the formation of an N region used in the wiring structure of the present invention on the scissors base plate, and the formation of a film 810 having a window exposing the active region surface. , the Si
Using the 0g film etc. and the gate electrode in the blind dot as a mask, the implantation energy is 175 (Key) and the implantation amount is about 1.7×10"(atm7'crd).
After selectively implanting N!, the same annealing treatment as for the previous P is applied to the KNW source region 14 within the active region 12 and the N!
The It drain region 15 and the upper surface i of the GIAI substrate 11
ll: I XIO'(atm/Cm") qof3
It shows that an N+ type region 1et having a peak density It is formed. In this state, the active area kFiF
ET is formed. Next, in step 211(b), a source electrode 1 and a drain electrode 18 made of, for example, gold/genimanium/gold are formed on the source and drain regions using a conventional Fosci process, evaporation, and method. It also shows a state in which a tenth power distribution circuit 1t19 is formed on the N+ wetted area 16. These electrodes are connected to the lower conductor layer with an A4 angle of about 450 (B). ◎ Then, FIG. 2(e) shows a state in which, for example, an SIO-film 209 is formed to cover the electrode by chemical vapor deposition (CVD) or the like.

Next, after forming a desired through hole in the 810@membrane 20 using a good mask etching method or the like, a process 11 such as sputtering/damping, ion/electro-ring, etc. is applied to the peritoneum 20 of the Si can. The source electrode [21
, a drain y wiring 22. which is superior to the drain electrode 18. The electrode wiring 23a, which is connected to the drain wiring 2211C* and 01 showing the state in which the electrode wiring 23 is formed, is formed in the upper region of the anchor region 16, and therefore the electrode wiring 2211C* is formed in the upper region of the anchor region 16. 12B, that is, the second wiring electrode is connected to the ground electrode, that is, the first wiring electrode 19, and has a structure in which it is bypassed by a capacitor having the dielectric layer 810 and the membrane 20. An example in which the 11O structure of the present invention is applied to a high-speed ICK will be described using a schematic perspective plan view and a cross section of the main part Ill.

Placed in No. 311 #1ll1101111/a (Example L Ham
1/1411 pole) 31 is formed smoothly and widely (low invinidance shape), and a single second electrode (for example, electrical wiring) 32 is provided on the upper part of the r#IILN''W region 33. It is a part of electric IC II/IAf1.And 31' in the figure
, 32' indicates the branch wiring %34, 34X indicates the unit circuit, B indicates the drive power supply, and G indicates the ground.The irises 4■ form the first electrode wiring 31 broadly, and are close to this and are located above the Xs region 33. Two second electrode wirings 328
．． Dual-IC〇1 embodiment with 32b T:h2h@
Soshite TIJ middle 31'e 32m'# 32b' company branch wiring, 341 to 34X are unit circuits, B and -B are drive power -
1G indicates grounding.

Figure 5 (The ridge is a single power supply IC with wiring electrodes in two places, each O wiring electrode being used as a grounding electrode or a driving electrode, and a bypass container interposed in the two-tatami S. 〇This is a perspective plan schematic diagram in one embodiment, No. 5 *φ)
FIG. 2 is a cross-sectional view taken along line AA' of FIG. And 31" in the figure
s'311) IIi first wiring electrode, 31"*31" is branch wiring, 32 heat, 32b is second wiring electrode, 33-33
haN"1 area 134a to 34X are unit circuits % 35 is 5iOt expansion q 36 is a through hole, B is a drive power supply, G
ii Indicates grounding.In this structure, the first wiring electrode 3
11 and 31b are formed in the lower layer, and these 10th wiring electrodes are connected to the 20th wiring electrodes on other ON ten-shaped regions by branch wirings 31''*31b' led out to the upper layer through the through holes 36t.
It is connected to the wiring electrode 32m or $2b.

FIG. 6 (11 shows N'' layer regions are provided in two places, and mutually connected 10th wiring electrodes are provided in both N~ regions upper and O lower layer parts,
By providing the second wiring electrodes connected to each other in the upper layer sK above both N+ wave regions, a transparent view of an embodiment of a single-voltage IC with bypass capacitors interposed in the two main parts. In the schematic plan view, 1st 6 @ Φ) and (C) are its B-B'
and c-c' arrow sectional view 0 and 31m, 3 in the figure.
1b is the first wiring electrode - 31' is its branch wiring% 3
2m, 32bijlli2 wiring electrode・32/ is its branch wiring・331, 33b is N+IM area 34m-34X
Fi unit circuit, 35 is SIO, membrane, B is vertical power supply, GI
/i indicates grounding. As explained above, if the structure of the present invention is applied, lGmA
High-speed ICK formed using semi-insulating semiconductor substrate such as s
It is extremely easy to add a bypass capacitor to the I#7iυ wiring in the I#7iυ wiring. Therefore, according to the present invention, a highly integrated high-speed semiconductor IC with a high switching speed and a high probability of malfunction can be formed. I can do it...

[Brief explanation of drawings]

1 (1) and (b) are partial sectional views for explaining the present invention in detail, and FIG. 3 and 4 are schematic perspective views of one embodiment, and FIG. 5 (1) is a schematic perspective view of another embodiment.
b) A sectional view taken along the line A-A' of the company, FIG.
) is a sectional view taken along arrows 0B-B' and c-c'. A semi-insulating semiconductor substrate, L3L33Jl
, 33b is the N~ region 3, 33, 3111.31b is the 10th wiring electrode, 4 is the insulating film, 5e 32132 mm
32b is the second wiring electrode, 31/, 31m'e 31b
'32'#321'#32b' is branch wiring, 34M4
34 is a unit circuit, 35 is a silicon dioxide film, 36 is a through hole, CI (a, Cb are capacitances, G#i is the base, B
.

Claims (1)

[Claims] ・Semiconductor integrated circuit device f using a semi-insulating semiconductor substrate
llK, a first wiring electrode and an insulating film formed directly on the low resistivity region, and a 20th wiring electrode tube formed on the insulating film and connected to the first wiring electrode. A semiconductor integrated circuit device characterized by: