JP2001223275A - Semiconductor device and manufacturing method for the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing an antenna ratio in a standard cell type semiconductor device and realizing the semiconductor device having high reliability by preventing an antenna error and a method for manufacturing it. SOLUTION: In the standard cell type semiconductor device comprises an output side buffer 20 connected to an output terminal 11 of a front stage circuit 10 constituted of a block layout BL1 having MOS transistors P1, N1. In this case, the block layout in which a gate width size of the gate electrode 105 is larger than a standard with the result that the area of the electrode 105 is larger than the area of the standard is selected so that the antenna ratio of a ratio of an area of a gate electrode 105 of the transistors P1, N1 for constituting the buffer 20 to an area of a wiring film 120 connected to the gate electrode 105 of the MOS transistor becomes smaller than a predetermined antenna ratio, and the layout of the semiconductor device is executed. Thus, the antenna ratio of the electrodes 105 of the transistors P1, N1 is reduced to prevent the antenna error.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a standard cell type semiconductor device, and more particularly to a semiconductor device in which damage to an insulating film due to electric charges charged to an electrode formed on a thin insulating film is prevented, and a method of manufacturing the same. .

[0002]

2. Description of the Related Art Semiconductor devices having an insulated gate field effect transistor (MOS transistor) as a circuit element are becoming increasingly larger in gate dimensions of MOS transistors as semiconductor devices become more highly integrated and dense in recent years. Accordingly, the thickness of the gate insulating film immediately below the gate electrode is also extremely reduced. Such M
An MO is placed on a semiconductor wafer on which an OS type transistor is formed.
In the case of forming a wiring for connecting the S-type transistors, usually, an interlayer insulating film covering the MOS transistor is formed, and a contact hole is opened to the gate electrode of the MOS transistor to be connected. Then, an upper conductive film for wiring is formed on the entire surface of the interlayer insulating film, that is, in a region including the contact hole, and then the upper conductive film is etched into a required pattern by a plasma etching method or the like. Are formed, and a wiring for each MOS transistor is formed by the formed wiring.

In a semiconductor device adopting such a manufacturing method, as described above, when an upper conductive film on an interlayer insulating film is patterned by a plasma etching method to form a wiring, the upper conductive film is formed. When exposed to the plasma, electric charges caused by the plasma are charged. This charge amount is proportional to the area of the upper conductive film as the formed wiring. Since the gate electrode electrically connected to the charged upper conductive film is also charged, an electric field due to charging is applied to the gate insulating film, and the electric field causes deterioration of the film quality of the gate insulating film. As a result, the threshold voltage of the MOS transistor fluctuates, and furthermore, the gate insulating film is broken, and the operation of the MOS transistor is hindered. In particular, when the gate length of the MOS transistor is 0.2
With the reduction from 5 μm to 0.18 μm, M
The impurity concentration of the substrate forming the OS-type transistor is increased, so that the withstand voltage of the gate insulating film is relatively smaller than the reverse withstand voltage of the diode constituted by the impurity of the MOS-type transistor. Is likely to be destroyed.

[0004] Such a phenomenon is referred to herein as an antenna error. To prevent this antenna error, the antenna ratio, that is, the area of the gate electrode of the MOS transistor and the area formed on the interlayer insulating film are reduced. Thus, it is preferable to reduce the area ratio with respect to the upper conductive film for wiring electrically connected to the gate electrode. If the antenna ratio is reduced, the density of the charge distributed to the gate electrode due to the charge in the upper conductive film is reduced, and the electric field applied to the gate insulating film is reduced. Deterioration and destruction of the film quality can be prevented. In the above description of the antenna error, the pattern forming step by the plasma etching method has been described as an example. However, the present invention is not limited to this, and the resist removing step by plasma and the interlayer insulating film forming step by plasma CVD method are not limited thereto. Since a similar phenomenon occurs in a semiconductor manufacturing apparatus using plasma as described above, it is preferable to similarly reduce the antenna ratio. Further, as an area of the upper conductive film for wiring used in calculating the antenna ratio, an area of a portion exposed to plasma during a process using plasma must be used. Therefore, in the plasma etching step, it is appropriate to use the total area of the side surfaces, excluding the area of the upper surface covered with the resist, as the area of the upper conductive film, in the interlayer insulating film forming step and the resist peeling step. It is appropriate to use, as the area of the upper conductive film, the total purpose of the exposed upper surface and side surface. However, when the total area of the upper surface and the side surface is used, the calculation is performed based on only the larger one of the area of the upper surface and the side surface depending on the ratio of the width and the thickness of the upper conductive film. I don't mind.

In order to prevent such an antenna error, it is conceivable to reduce the substantial area of the upper conductive film for wiring electrically connected to the gate electrode of the MOS transistor. For example, as shown in FIGS. 13A and 13B, a circuit diagram and a conceptual sectional view of an example thereof, a gate oxide film 204 and a gate oxide film 204 are formed in an element forming region 203 defined by an element insulating film 202 of a silicon substrate 201. Electrode 205
Is formed, and impurities are further introduced to form source / drain regions 206 to form MOS type transistor P1.
1 and N11 are formed, and a buffer 50 composed of these MOS transistors P11 and N11 is electrically connected to the output terminal 11 of the pre-stage circuit 10. The gate electrodes 2 of the MOS transistors P11 and N11
Wiring film 22 on interlayer insulating film 210 connected to substrate 05
Reference numeral 0 denotes a second wiring film 240 and a third wiring film 2 which are formed in a state where the area is reduced as much as possible, and are further reduced thereon in the same manner via interlayer insulating films 230 and 250.
60 are sequentially formed, and these wiring films 220, 240, 2
The electrical connection to the pre-stage circuit 10 is made by connecting the 60 in order. Thus, the first through third
By making the areas of the wiring films 220, 240, and 260 small, respectively, it is possible to reduce the substantial area when each wiring film is formed, and to reduce the effective antenna ratio with respect to the gate electrode 205. Will be possible.

As another technique, it has been considered to increase the effective area on the gate electrode side of a MOS transistor. For example, in the technique described in JP-A-9-199606, a gate array or the like is disclosed. In the semiconductor device of the master slice type, the wiring connected to the gate electrode of the transistor to which the wiring is connected is also connected to the gate electrode of the unused transistor. By connecting the gate electrode as a dummy gate electrode, the area of the gate electrode is increased, and as a result, the antenna ratio is reduced to prevent an antenna error. Also, Japanese Unexamined Patent Application Publication No.
The same applies to the technique described in JP-A-204767, in which a wiring is also connected to the gate electrode of a transistor that is not used in the gate array, thereby reducing the antenna ratio and preventing an antenna error. Japanese Patent Application Laid-Open No. H11-204767 also discloses a technique in which a wiring is connected to a diffusion layer of a transistor that is not used and a charged charge is released to a semiconductor substrate via the diffusion layer. Thus, the same operation and effect as when the antenna ratio is substantially reduced are obtained.

[0007]

In such a conventional technique, in the former technique of reducing the substantial area on the conductive film side, it is necessary to form wiring in multiple layers, and the conductive film of each layer is formed through. The connection via the hole is an obstacle to achieving high integration and high density of the semiconductor device, and the number of manufacturing steps is unnecessarily increased. In particular, in the case of forming a 0.18 μm-level MOS transistor, the area allowed for the conductive film in each layer is extremely small, and it is extremely difficult to actually apply such a technique.

The technique described in the above-mentioned publication is applied to a master slice system in which a gate array formed on a semiconductor substrate is selected in advance and wiring is performed. The semiconductor device formed in this way includes a transistor that is not used, which is an obstacle to achieving high integration and high density of the semiconductor device. In recent years, in order to solve such a problem in the master slice method, a standard cell (cell-based) semiconductor device in which only necessary transistors are formed on a semiconductor substrate has been proposed. Therefore, in a semiconductor device adopting such a standard cell method, only transistors originally required are present on the semiconductor substrate, and there is no unused transistor as described above. As described in each of the above publications, the technology for reducing the antenna ratio based on the unused transistors cannot be applied as it is, and as a result, the reduction of the antenna ratio in the standard cell type semiconductor device is realized. Becomes difficult.

An object of the present invention is to reduce the antenna ratio in a standard cell type semiconductor device, to prevent the occurrence of an antenna error, and to realize a highly reliable semiconductor device and its semiconductor device. It is intended to provide a manufacturing method.

[0010]

A first semiconductor device according to the present invention is a standard cell type semiconductor device having a block layout including MOS transistors, and is a semiconductor device having a circuit layout having the block layout. The gate area of the gate electrode is set such that the antenna ratio, which is the ratio of the area of the wiring film connected to the gate electrode of the MOS transistor to the area of the gate electrode of the MOS transistor, is smaller than a predetermined antenna ratio. It is characterized by being set.

A second semiconductor device according to the present invention is a standard cell type semiconductor device having a block layout including MOS transistors, wherein a plurality of circuits having the block layout are connected in cascade. The antenna ratio, which is the ratio of the area of the wiring film connected to the gate electrode of the MOS transistor of each circuit to the area of the gate electrode of the MOS transistor of each circuit, is smaller than a predetermined antenna ratio. The gate area of the gate electrode of each of the circuits is set so as to be as follows.

Further, a third semiconductor device according to the present invention is a standard cell type semiconductor device having a block layout including MOS transistors, and a MOS transistor of a circuit having the block layout.
A MOS capacitor having a dummy gate electrode is connected to the gate electrode of the
An antenna ratio which is a ratio of the area of the wiring film connected to the gate electrode of the MOS transistor of each circuit to the area obtained by adding the area of the gate electrode of the S type transistor and the area of the dummy gate electrode of the MOS capacitor. Is set such that the dummy gate area of the MOS-type capacitor is smaller than a predetermined antenna ratio.

As a first method for manufacturing a semiconductor device,
When selecting a block layout for configuring a required circuit from a library storing a plurality of different block layouts, an area of a gate electrode of a MOS transistor included in the selected block layout is determined. An antenna ratio is calculated from an area of a wiring film connected to a gate electrode of a transistor, the calculated antenna ratio is compared with a predetermined antenna ratio, and the calculated antenna ratio is smaller than the predetermined antenna ratio. Is selected.

As a method for manufacturing the second semiconductor device,
An antenna ratio obtained from the area of the gate electrode of the MOS transistor constituting the predetermined circuit and the area of the wiring film connected to the gate electrode of the MOS transistor is calculated, and the calculated antenna ratio is determined by the predetermined antenna ratio. When larger than, the wiring film is divided into a plurality of wiring portions in its length direction, and a block layout selected from a library storing a plurality of block layouts is interposed at the divided portion, and The antenna ratio is determined from the area of the gate electrode of the MOS transistor constituting the circuit and the selected block layout and the area of each wiring portion of the wiring film connected to the gate electrode of each MOS transistor. Calculating, comparing the calculated antenna ratio with a predetermined antenna ratio, and calculating the calculated antenna ratio. Tena ratio, characterized in that it comprises the step of selecting the smaller becomes the block layout than the predetermined antenna ratio.

As a third method of manufacturing a semiconductor device,
An antenna ratio obtained from the area of the gate electrode of the MOS transistor constituting the predetermined circuit and the area of the wiring film connected to the gate electrode of the MOS transistor is calculated, and the calculated antenna ratio is determined by the predetermined antenna ratio. When the block layout is larger than the block layout, a block layout of a MOS capacitor having a dummy gate electrode is selected from a library storing a plurality of block layouts and connected to the wiring film to form a block layout forming the circuit. The area of the gate electrode of the MOS transistor and the MOS
The antenna ratio is calculated from the area obtained by adding the area of the dummy gate electrode of the mold capacitance and the area of the wiring film, and the calculated antenna ratio is compared with a predetermined antenna ratio. The method includes a step of selecting a block layout of a MOS capacitor having a smaller antenna ratio than a predetermined antenna ratio.

In the semiconductor device and the manufacturing method of the present invention, the antenna calculated from the area of the gate electrode of the MOS transistor constituting the required circuit and the area of the wiring film connected to the gate electrode of the MOS transistor Ratio or the area obtained by adding the area of the dummy gate electrode of the MOS capacitor to the area of the gate electrode of the MOS transistor constituting the required circuit and the area of the wiring film connected to the gate electrode of the MOS transistor. A standard cell type semiconductor device in which the calculated antenna ratio is smaller than a predetermined antenna ratio can be realized. As a result, when manufacturing a semiconductor device, a circuit is configured by selecting only a required block layout from a library, thereby realizing high integration and high density of the semiconductor device, while destruction of a gate insulating film. It is possible to obtain a highly reliable semiconductor device which is not performed.

[0017]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing a part of a circuit of a first embodiment of a semiconductor device to be manufactured in the present invention, and has a configuration in which an output-side buffer 20 is connected to a subsequent stage of a former-stage circuit 10 which is not described in detail. . The output side buffer 20 includes a P-channel MOS transistor P1 and an N-channel MOS transistor P1.
Inverter having CMOS circuit configuration with channel MOS transistor N1 (hereinafter referred to as CMOS inverter)
Is composed. The output terminal 1 of the preceding-stage circuit 10
1, a P-channel M constituting the CMOS inverter
The gates of the OS transistor P1 and the N-channel MOS transistor N1 are electrically connected.

FIG. 2 is a plan layout view of the circuit of FIG. 1, and FIG. 3 is a schematic sectional view of a portion along the line AA. An element formation region (transistor) is formed on the main surface of the silicon substrate 101 by an element isolation insulating film 102. A formation region) 103 is partitioned, and a gate oxide film 104 and a gate electrode 105 constituting the MOS transistors P1 and N1 of each CMOS inverter of the output buffer 20 are formed on the main surface of the silicon substrate 101. . The element formation region 103 of the silicon substrate 101 has P
-Type and N-type impurities are introduced to make the source / drain region 1
06 is formed. Then, an interlayer insulating film 111 is formed on each of the MOS transistors, and the interlayer insulating film 1 is formed.
The gate electrode 105 and the output terminal 11 of the pre-stage circuit 10 are respectively connected by a part of a first wiring film 120 made of aluminum or the like formed on the interlayer insulating film 111 via a through hole 112 opened to the gate electrode 105. You. The drains of the MOS transistors P1 and N1 are connected to an output side circuit (not shown) by another part 121 of the first wiring film. The source of each MOS transistor is connected to the power supply VDD and the ground GND by the other portions 122 and 123 of the first wiring film. Thereby, the circuit shown in FIG. 1 is formed.

Here, each of the pair of MOS transistors P1 and N1 constituting the CMOS inverter constituting the output buffer 20 has a gate width of the gate electrode 105 (dimension in a direction orthogonal to the gate length) as compared with the standard. Are also large. The gate width dimension is set according to the area of the first wiring film 120, and the gate electrode 105 and the gate electrode 10
5 (antenna ratio) = (area of the first wiring film)
/ (Area of gate electrode)] is set to a dimension that does not become larger than a preset reference antenna ratio. Usually, the preset reference antenna ratio is about several thousands to 10,000, but this value is appropriately changed depending on the process to be applied, the type of manufacturing apparatus, and the conditions of the manufacturing process.

That is, the semiconductor device is manufactured by a standard cell method. That is, when forming the output-side buffer 20 of the semiconductor device of FIG. 2 based on the circuit of FIG. 1, blocks necessary for configuring the circuit are obtained from a library in which various block layouts are stored in advance. A layout is selected, and the data is read to configure the layout of the semiconductor device. Here, among the block layouts stored in the library, in a block layout including MOS transistors, the gate length of each MOS transistor is the gate length required for the semiconductor device to be manufactured, for example, 0.1.
Although a gate length of 8 μm is stored, a block layout including MOS transistors having various gate widths is stored for the gate width.

As shown in FIG. 2, when the block layout BL1 is selected from the library as the block layout of the output buffer 20,
As shown in the flowchart of FIG. 4, the area of the gate electrode 105 is calculated based on the data of the gate electrodes 105 of the MOS transistors P1 and N1 constituting the CMOS inverter of the selected block layout BL1 (S101). At the same time, the area of the first wiring film 120 required to connect the block layout BL1 and the preceding circuit 10 is calculated (S10).
2). Then, an antenna ratio is calculated from the calculated areas of the gate electrode and the first wiring film (S103). Next, the calculated antenna ratio is compared with the reference antenna ratio set in advance as described above (S104), and when the calculated antenna ratio is smaller than the reference antenna ratio, the selected block layout is adopted. The layout of the semiconductor device is executed using this block layout (S105). If the calculated antenna ratio is larger than the reference antenna ratio, the selected block layout is discarded (S106), and another block layout having a larger gate width than the block layout is selected (S107). Then, for the reselected block layout, the above-described step S10
Execute the steps from 1 again. Then, a layout of the semiconductor device is executed by adopting a block layout smaller than the reference antenna ratio (S105).

In this way, the output buffer 20
By selecting the CMOS inverter block layout BL1 and manufacturing the semiconductor device having the layout arrangement shown in FIG. 2, the MOS transistors P1 and N1 constituting the CMOS inverter of the output-side buffer 20 are The antenna ratio is smaller than a predetermined antenna ratio with respect to the first wiring film 120 electrically connected to the output end 11. Therefore, as shown in FIG.
The MOS type transistors P1 and N1 of the output buffer are manufactured on a silicon substrate 101, an interlayer insulating film 111 is formed thereon, and a material film of a first wiring film is formed on the entire surface after opening a through hole 112. When the material film of the first wiring film is formed into a required wiring pattern by a plasma etching method, the formed first wiring film 120 is formed.
Even if the gate electrode 105 of each of the MOS transistors P1 and N1 is charged with this charge, the gate oxide film 104 of each of the MOS transistors P1 and N1 may be destroyed. That is, it is possible to prevent an antenna error.

Further, since the semiconductor device is manufactured by a standard cell method, a circuit is formed by selecting only a necessary block layout, so that the semiconductor device is used in the same manner as the gate array method described in the prior art publication. A transistor that does not exist does not exist in the semiconductor device, which is advantageous in achieving high integration and high density of the semiconductor device.
In this case, in the first embodiment, the output-side buffer 2
For the MOS type transistors P1 and N1 of 0, a block layout having a larger gate width dimension than the standard block layout is selected. In this regard, the area occupied by the block layout increases, but the gate array type semiconductor device The increase in the area is small as compared with that of the first embodiment, and there is no obstacle to realizing high integration and high density of the semiconductor device. In the above description, the antenna ratios are sequentially calculated for each block layout, and the adjustment is performed so that the antenna ratio becomes smaller than the reference antenna ratio. However, the present invention is not limited to this. After completing the above, the antenna ratio may be calculated for each block layout, and necessary adjustment may be performed.

FIG. 5 is a circuit diagram of a part of the circuit according to the second embodiment of the present invention. The configuration in which the output side buffer 20 is connected to the output terminal 11 of the pre-stage circuit 10 is the same as that of the first embodiment. However, here, a configuration is adopted in which a pre-stage buffer 30 is interposed on the input side of the output side buffer 20. The output side buffer 20 includes a P-channel MOS transistor P1 and an N-channel MOS transistor N1
The configuration of the OS inverter is the same as that of the first embodiment. The former-stage buffer 30 is also similar in circuit configuration to the P-channel MO as in the output-side buffer.
This is a configuration of a CMOS inverter including an S-type transistor P2 and an N-channel MOS type transistor N2. The output terminal 11 of the pre-stage circuit 10 and the P-channel MO constituting the CMOS inverter of the output-side buffer 20
The pre-stage buffer 30 is interposed between the S-type transistor P1 and each gate of the N-channel MOS transistor N1, and these are electrically connected by a first wiring film 120. That is, the output terminal 11 of the preceding-stage circuit 10 is connected to the gates of the respective MOS-type transistors P2 and N2 of the CMOS inverter of the preceding-stage buffer 30, and the respective MOS-type transistors P2 and N2 of the preceding-stage buffer 30 are connected.
Is connected to the C of the output buffer 20.
MOS type transistors P1 and N1 of the MOS inverter
Connected to the gate.

FIG. 6 is a plan layout view of the circuit of FIG. 5, and FIG. 7 is a schematic sectional view taken along the line BB. On the main surface of the silicon substrate 101, element formation regions 103A and 103 are defined by an element isolation insulating film 102, and
Each MOS of the preceding buffer 30 and the output buffer 20
Oxide Films 104A, 10 Constituting Type Transistor
4 and gate electrodes 105A and 105 are formed on the main surface of the silicon substrate 101. Further, P-type and N-type impurities are introduced into the element formation regions 103A and 103 of the silicon substrate 101 to form source / drain regions 106A and 106, respectively. And each MO
An interlayer insulating film 111 is formed on the S-type transistor, and a through hole 112 opened in the interlayer insulating film 111 is formed.
A, a first wiring film 120 of aluminum or the like formed on the interlayer insulating film 111 via the
0 and the gate electrode 105A of each MOS transistor of the preceding buffer 30. The output terminal (source / drain region) of the preceding buffer 30 and the gate of each MOS transistor of the output buffer 20 are connected. The circuit shown in FIG. 5 is formed by being connected to the electrode 105.

Here, the first-stage buffer 30 electrically connected to the first-stage circuit 11 by the first wiring film 120 is used.
In each of the MOS type transistors P2 and N2, the gate width of the gate electrode is formed large. The gate width is determined by the area of the gate electrode 105A of each of the MOS transistors P2 and N2 of the preceding buffer 30 and a part of the first wiring film 120 connecting the gate electrode 105A to the preceding circuit 10. 1st part wiring film) 1
The antenna ratio obtained from the area of 20a is set to a dimension that does not become larger than a preset reference antenna ratio. Similarly, each MOS transistor of the output-side buffer 20 electrically connected to the output terminal of the pre-stage buffer 30 by the first wiring film 120 is formed such that the gate width of the gate electrode 105 is slightly larger than the standard. ing. The gate width dimension is determined by the area of the gate electrode 105 of the output buffer 20 and the gate electrode 1.
The other part (second partial wiring film) 12 of the first wiring film 120 connecting the output line 05 to the output terminal of the pre-stage buffer 30
The antenna ratio obtained from the area of 0b is set to a dimension that does not become larger than the reference antenna ratio.

In the second embodiment, as in the first embodiment, the semiconductor device uses a library in which various block layouts are stored in advance to obtain a block layout necessary for configuring the circuit. Selected,
In addition, the semiconductor memory device is configured by a standard cell system that reads out the data and configures the layout of the semiconductor device. In FIG. 6, block layouts BL1 and BL2 are respectively formed. That is, as shown in the flowchart of FIG. 8, when selecting the block layouts BL1 and BL2, the preferred arrangement positions of the front-stage buffer 30 and the output-side buffer 20 with respect to the front-stage circuit 10 are determined (S201). The first partial wiring film 120a is formed based on the layout of the first wiring film 120 that sequentially connects the preceding circuit 10, the preceding buffer 30, and the output buffer 20.
And the respective wiring lengths of the second partial wiring film 120b are calculated (S2
02).

Then, first, the area of the gate electrode 105A is calculated for the pre-stage buffer 30 based on the data of the gate electrodes 105A of the MOS transistors P2 and N2 of the selected block layout (S20).
3). At the same time, the area of the first partial wiring film 120a of the first wiring film required to connect the block layout to the preceding circuit 10 is calculated (S204). Then, the calculated gate electrode and first partial wiring film 12 are formed.
The antenna ratio is calculated from the area of 0a (S205). Next, the calculated antenna ratio is compared with the reference antenna ratio (S206). If the calculated antenna ratio is smaller than the reference antenna ratio, the selected block layout is adopted and the layout of the semiconductor device is executed (S2).
07). When the calculated antenna ratio is larger than the reference antenna ratio, the selected block layout is discarded (S208), and a block layout having a larger gate width than the block layout is selected again (S209). Then, the steps from step S203 are executed again on the reselected block layout. When the antenna ratio becomes smaller than the reference antenna ratio due to the selected block layout,
The layout based on the block layout is executed (S207).

Next, this time, for the output side buffer 20, the area of the gate electrode 105 is calculated based on the data of the gate electrodes 105 of the MOS transistors P1 and N1 of the selected block layout (S210).
At the same time, the preceding buffer 3 is added to the block layout.
0 of the first wiring film 120 required to connect
The area of the partial wiring film 120b is calculated (S211). Then, the antenna ratio is calculated from the calculated areas of the gate electrode 105 and the second partial wiring film 120b (S21).
2). Next, as in the case of the preceding buffer 30,
The calculated antenna ratio is compared with the reference antenna ratio (S2
13) When the calculated antenna ratio is smaller than the reference antenna ratio, the selected block layout is permanently selected and the layout of the semiconductor device is executed (S21).
4). When the calculated antenna ratio is larger than the reference antenna ratio, the selected block layout is discarded (S215), and a block layout having a larger gate width than the selected block layout is reselected (S216). Then, the steps from step S210 are executed again on the reselected block layout. When the antenna ratio becomes smaller than the reference antenna ratio by the selected block layout, the layout according to the block layout is executed (S
214).

As described above, the block layout of each MOS transistor of the pre-stage buffer 30 and the output-side buffer 20 is selected to manufacture a semiconductor device having the layout arrangement shown in FIG. The MOS type transistor of the CMOS inverter is
The first circuit electrically connected to the output terminal 11 of the pre-stage circuit 10
The antenna ratio becomes smaller than the predetermined antenna ratio with respect to the partial wiring film 120a.
The MOS type transistor of the 0 CMOS inverter has an antenna ratio smaller than a predetermined antenna ratio with respect to the second partial wiring film 120b electrically connected to the output terminal of the pre-stage buffer 30. Therefore, when the first wiring film 120 is formed in a required pattern by the plasma etching method, the formed first partial wiring film 120 is formed.
a and the second partial wiring film 120b are each charged with an electric charge, and even if the charged electric charge is charged on the gate electrode of each MOS transistor of each buffer, the gate oxide film 104A of each MOS transistor is charged. , 10
4 is not destroyed, and an antenna error can be prevented.

In the second embodiment, when the first wiring film 120 is divided into the first partial wiring film 120a and the second partial wiring film 120b in the step S202,
The area of the second partial wiring film 120b is equal to the output-side buffer 2
If the length in the length direction of the first wiring film 120 can be appropriately divided so as to satisfy a predetermined antenna ratio with respect to the gate electrode 105 of the MOS transistor of the CMOS inverter of 0, the output buffer 20 For, a block layout as originally designed may be selected. In this case, the above-described step may be performed only when the block layout of the pre-stage buffer 30 is selected, and the above-described step becomes unnecessary when the output-side buffer 20 is formed. There is no complication.

Also in the second embodiment, since the semiconductor device is manufactured by the standard cell method and a circuit is formed by selecting only a required block layout, the gate device described in the prior art is disclosed. Unused transistors such as those in the array method do not exist in the semiconductor device, which is advantageous in realizing high integration and high density of the semiconductor device. In the second embodiment,
The front-stage buffer 30 is newly laid out in addition to the output-side buffer 20. In this respect, the area occupied by the block layout for configuring the front-stage buffer 30 increases, but compared with a gate array type semiconductor device. The increase in the area is slight, and does not hinder the realization of high integration and high density of the semiconductor device.

FIG. 9 is a partial circuit diagram of the third embodiment of the present invention.
Is the same as that of the first embodiment, except that the MOS type capacitor 40 is connected to a part of the first wiring film 120 connected to the input terminal of the output buffer 20. ing. The output side buffer 20 is the same as the first and second embodiments in that a CMOS inverter is formed by a P-channel MOS transistor P1 and an N-channel MOS transistor N1. The output terminal 11 of the pre-stage circuit 10 and the output-side buffer 20
P-channel MOS constituting CMOS inverter
The configuration is such that the type transistor P1 and each gate of the N-channel MOS type transistor N1 are electrically connected by a first wiring film 120, and a MOS type capacitor 40 is connected to a part of the first wiring film 120.

FIG. 10 is a plan layout diagram of the circuit of FIG.
FIG. 11 is a schematic sectional view along the CC line. On the main surface of the silicon substrate 101, device forming regions 103 and 103B are defined by a device isolation insulating film 102, and a gate oxide film 104 and a gate electrode 105 constituting each MOS transistor of the output side buffer 20 are formed of the silicon. It is formed on the main surface of the substrate 101. Also,
Source / drain regions 106 are formed in the element formation region 103 of the silicon substrate 101 by introducing respective P-type and N-type impurities. Further, a dummy silicon oxide film 104B and a dummy gate electrode 10B are formed on the main surface of the silicon substrate 101 in the element formation region 103B.
5B, and a MOS type capacitor using the silicon oxide film 104B as a capacitor insulating film is formed. Each of the MOS transistors P1, N1 and the MOS capacitor 4
0, an interlayer insulating film 111 is formed,
A first wiring film 12 made of aluminum or the like formed on the interlayer insulating film 111 through a through hole opened in
0 is each M of the pre-stage circuit 10 and the output buffer 20.
The first wiring film 120 is connected to the gate electrode 105 of the OS-type transistor, and a part of the first wiring film 120 is
MOS through a through hole 112B opened to
The circuit shown in FIG. 9 is formed by being connected to the dummy gate electrode 105B of the capacitor 40. Here, the MOS
When the area of the dummy gate electrode 105 </ b> B is added to the area of the gate electrode 105 of the output-side buffer 20, the mold ratio 40 is such that the antenna ratio obtained from the comparison with the area of the first wiring film 120 is set in advance. The dimensions are set so as not to be larger than the reference antenna ratio.

Also in the third embodiment, the semiconductor device selects a block layout necessary for configuring the circuit from a library in which various block layouts are stored in advance, as in the above embodiments. And
In addition, the semiconductor memory device is configured by a standard cell system that reads out the data and configures the layout of the semiconductor device. In this case, the library stores a block layout of MOS-type capacitors composed of dummy gate electrodes having different areas, as well as a block layout of each circuit for forming the semiconductor device.

Therefore, as shown in the flowchart of FIG. 12, after selecting each block layout of the pre-stage circuit 10 and the output side buffer 20 and laying out the first wiring film 120 connecting these, the output side buffer 10 For the buffer 20, each MOS of the selected block layout
The area of the gate electrode 105 is calculated based on the data of the gate electrode 105 of the type transistor (S30).
1). Further, the area of the first wiring film 120 is calculated (S302). Then, these calculated gate electrodes 1
The antenna ratio is calculated from the area of the first wiring film 120 and the area of the first wiring film 120 (S303). Next, the calculated antenna ratio is compared with the reference antenna ratio (S304). If the calculated antenna ratio is smaller than the reference antenna ratio, the selected block layout is adopted and the layout of the semiconductor device is executed (S305). ). When the calculated antenna ratio is larger than the reference antenna ratio, a block layout of one of the MOS capacitors is selected from the library (S306), and the area of the dummy gate electrode 105B of the selected MOS capacitor is calculated. (S30
7) The calculated area is added to the area of the gate electrode 105B of the output buffer 20 (S308). Then, the antenna ratio is calculated again based on the added area of the gate electrodes 105 and 105B and the area of the first wiring film 120 (S309), and is compared with the reference antenna ratio (S310). Then, when the antenna ratio becomes smaller than the reference antenna ratio by selecting the MOS capacitor, the block layout of the MOS capacitor is selected and the layout of the semiconductor device is executed (S311). When the antenna ratio is larger than the reference antenna ratio also by the MOS type capacitor, the M
The block layout of the OS type capacity is discarded (S31).
2) Reselect a block layout of a MOS capacitor having a larger dummy gate electrode area (S313).
Then, for this reselected block layout,
The steps from step S307 are executed again.
When the antenna ratio becomes smaller than the reference antenna ratio, the block layout of the MOS capacitor selected at that time is selected and the layout is executed (S311).

In this manner, by selecting the block layout of the MOS capacitor and manufacturing the semiconductor device having the layout arrangement shown in FIG.
MOS transistors P1 and N1 have an antenna ratio smaller than a predetermined antenna ratio with respect to the first wiring film 120 electrically connected to the preceding circuit 10. Therefore, when the first wiring film 120 is formed in a required pattern by the plasma etching method, the formed first wiring film 120 is charged with electric charge, and the charged electric charge is applied to each MOS transistor of the output side buffer 20. P1,
Even if the gate electrode 105 of N1 is charged, the gate oxide film 104 of each MOS transistor is not destroyed, and an antenna error can be prevented.

Also in the third embodiment, since the semiconductor device is manufactured by the standard cell method and a circuit is formed by selecting only a necessary block layout, the gate device described in the prior art is disclosed. Unused transistors such as those in the array method do not exist in the semiconductor device, which is advantageous in realizing high integration and high density of the semiconductor device. Further, similarly to the second embodiment, a block layout of a MOS capacitor is newly arranged in addition to the output side buffer. In this respect, the area occupied by the block layout increases. The increase in area is small compared to the device,
There is no obstacle to realizing high integration and high density of the semiconductor device.

In the third embodiment, the pattern of the dummy gate electrode 105B constituting the MOS type capacitor is arbitrary, and may be an annular or frame-like pattern in addition to the linear pattern as shown in FIG. , A lattice shape or the like, and by selecting this pattern, dummy gate electrodes having different areas can be formed even with the same block layout area.
This is advantageous in increasing the density.

[0040]

As described above, according to the present invention, when configuring a standard cell type semiconductor device, the area of the gate electrode of a MOS transistor constituting a required circuit and the gate electrode of the MOS transistor are connected. The antenna ratio calculated from the area of the wiring film, or the area obtained by adding the area of the dummy gate electrode of the MOS capacitor to the area of the gate electrode of the MOS transistor constituting the required circuit, and the gate of the MOS transistor. By configuring a standard cell type semiconductor device in which the antenna ratio calculated from the area of the wiring film connected to the electrode is smaller than a predetermined antenna ratio, only the necessary block layout is selected from the library. By realizing high integration and high density of semiconductor devices by configuring circuits, The gate insulating film makes it possible to obtain is not highly reliable semiconductor device can be destroyed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a part of a circuit of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a layout diagram for configuring the circuit of FIG. 1;

FIG. 3 is a schematic sectional view taken along the line AA in FIG.

FIG. 4 is a flowchart illustrating a part of the steps of the manufacturing method according to the first embodiment of the present invention.

FIG. 5 is a circuit diagram showing a part of a circuit of a semiconductor device according to a second embodiment of the present invention.

FIG. 6 is a layout diagram for configuring the circuit of FIG. 5;

FIG. 7 is a schematic sectional view taken along the line BB of FIG. 6;

FIG. 8 is a flowchart for explaining a part of the steps of the manufacturing method according to the second embodiment of the present invention.

FIG. 9 is a circuit diagram showing a part of a circuit of a semiconductor device according to a third embodiment of the present invention.

FIG. 10 is a layout diagram for configuring the circuit of FIG. 9;

11 is a schematic sectional view taken along the line CC in FIG.

FIG. 12 is a flowchart illustrating a part of the steps of the manufacturing method according to the third embodiment of the present invention.

FIG. 13 is a circuit diagram and a schematic cross-sectional structure diagram for explaining a conventional technique for dealing with an antenna error.

[Explanation of symbols]

 Reference Signs List 10 pre-stage circuit 20 output-side buffer 30 pre-stage buffer 40 MOS-type capacitor 101 silicon substrate 102 element isolation insulating film 103, 103A, 103B element formation region 104, 104A, 104B gate oxide film 105, 105A, 105B gate electrode 106, 106A source Drain region 111 Interlayer insulating film 112, 112A, 112B Through hole 120 First wiring film 120a First partial wiring film 120b Second partial wiring film

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat ゛ (Reference) H01L 21/822 F-term (Reference) 5F033 HH04 HH08 QQ12 RR04 SS04 UU02 UU04 VV01 VV17 XX03 5F038 AC05 AC14 AV06 BH20 CA01 CA04 CA05 CA18 CD10 DF20 EZ08 EZ11 EZ15 EZ20 5F048 AA01 AA07 AB02 AB05 AB07 AC03 AC10 BA01 BB05 BD02 BF00 BF15 BG12 5F064 AA04 BB02 CC10 CC23 DD03 DD26 DD32 EE33 EE45 GG03

Claims (9)

[Claims] 1. A standard cell type semiconductor device comprising a block layout including a MOS transistor, wherein a circuit having the block layout has an area corresponding to an area of a gate electrode of the MOS transistor.
A semiconductor, wherein the gate area of the gate electrode is set such that the antenna ratio, which is the ratio of the area of the wiring film connected to the gate electrode of the MOS transistor, is smaller than a predetermined antenna ratio. apparatus. 2. A standard cell type semiconductor device having a block layout including MOS transistors, wherein a plurality of circuits having the block layout are cascaded, and a MOS transistor of each circuit is provided. The antenna ratio, which is the ratio of the area of the wiring film connected to the gate electrode of the MOS transistor of each circuit to the area of the gate electrode of each circuit, is smaller than a predetermined antenna ratio. A semiconductor device having a gate area set. 3. A standard cell type semiconductor device comprising a block layout including MOS transistors, wherein a MOS transistor having a dummy gate electrode is provided as a gate electrode of a MOS transistor of a circuit comprising the block layout. Type capacitor is connected, and the area of the gate electrode of the MOS transistor of the circuit and the M
The antenna ratio, which is the ratio of the area of the wiring film connected to the gate electrode of the MOS transistor of each circuit to the area obtained by adding the area of the dummy gate electrode of the OS-type capacitor, is smaller than a predetermined antenna ratio. In addition, the MOS
A semiconductor device, wherein a dummy gate area of a mold capacitor is set. 4. A gate electrode of the MOS transistor is formed to have the same gate length, and a gate electrode of the MOS transistor of the selected block layout has a gate width dimension satisfying a required gate area. The semiconductor device according to claim 1, wherein the semiconductor device is formed. 5. A method of manufacturing a standard cell type semiconductor device comprising a block layout including MOS transistors, wherein a required circuit is configured from a library storing a plurality of different block layouts. When selecting the block layout, the antenna ratio is calculated from the area of the gate electrode of the MOS transistor constituting the selected block layout and the area of the wiring film connected to the gate electrode of the MOS transistor. Comparing the calculated antenna ratio with a predetermined antenna ratio and selecting a block layout in which the calculated antenna ratio is smaller than the predetermined antenna ratio. 6. A method of manufacturing a standard cell type semiconductor device having a block layout including a MOS transistor, wherein the area of a gate electrode of the MOS transistor forming a predetermined circuit is determined. The antenna ratio obtained from the area of the wiring film connected to the gate electrode is calculated, and when the calculated antenna ratio is larger than a predetermined antenna ratio, the wiring film is divided into a plurality of wiring portions in the length direction. In addition, a block layout selected from a library storing a plurality of block layouts is interposed and arranged at a divided portion, and a gate electrode of a MOS transistor configuring the circuit and a MOS type transistor configuring the selected block layout are interposed. And the area connected to the gate electrode of each of the MOS transistors. The antenna ratio is calculated from the area of each wiring portion of the wiring film to be calculated, the calculated antenna ratio is compared with a predetermined antenna ratio, and a block layout in which the calculated antenna ratio is smaller than the predetermined antenna ratio is selected. A method of manufacturing a semiconductor device, comprising the steps of: 7. A method of manufacturing a standard cell type semiconductor device having a block layout including a MOS transistor, wherein the area of a gate electrode of the MOS transistor forming a predetermined circuit is determined. The antenna ratio obtained from the area of the wiring film connected to the gate electrode is calculated, and when the calculated antenna ratio is larger than the predetermined antenna ratio, the dummy gate electrode is stored in a library storing a plurality of block layouts. The area of the gate electrode of the MOS transistor and the area of the dummy gate electrode of the MOS capacitor which are connected to the wiring film by selecting the block layout of the MOS capacitor having And the antenna ratio is calculated from the area obtained by adding Manufacturing the semiconductor device, comprising comparing the calculated antenna ratio with a predetermined antenna ratio, and selecting a block layout of a MOS capacitor in which the calculated antenna ratio is smaller than the predetermined antenna ratio. Method. 8. The block layout according to claim 5, wherein the plurality of block layouts are configured as block layouts in which the gate lengths of the gate electrodes of the respective MOS transistors are equal and the gate widths are different. The manufacturing method of the semiconductor device described in the above. 9. The method of manufacturing a semiconductor device according to claim 7, wherein the plurality of block layouts of the MOS type capacitors are configured by dummy gate electrodes having different gate areas.