JPS58137243A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS58137243A JPS58137243A JP1909182A JP1909182A JPS58137243A JP S58137243 A JPS58137243 A JP S58137243A JP 1909182 A JP1909182 A JP 1909182A JP 1909182 A JP1909182 A JP 1909182A JP S58137243 A JPS58137243 A JP S58137243A
- Authority
- JP
- Japan
- Prior art keywords
- wiring layer
- power supply
- power feeding
- cells
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 239000011159 matrix material Substances 0.000 claims description 6
- 238000009792 diffusion process Methods 0.000 abstract description 40
- 239000006185 dispersion Substances 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 59
- 239000011229 interlayer Substances 0.000 description 11
- 230000008054 signal transmission Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体集積回路装置に係り、特に多層配線層を
有し、セル内に給電手段を持つ半導体集積回路装置に関
する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having multilayer interconnection layers and having power supply means in its cells.
従来、−塩セルと給電用セルとをマトリクス的に組合せ
て作られた半導体集積回路装置は、給電用セル内に積極
的にキャパシタンスを形成させていなかったために、論
理セル列中央付近の給電ラインのインピーダンスが高く
なって給電ラインの電位が揺れることにより、信号の伝
達速度が遅くなったり、論理糾動作を行う恐れがあった
。Conventionally, in semiconductor integrated circuit devices made by combining salt cells and power supply cells in a matrix, capacitance was not actively formed in the power supply cells, and therefore the power supply line near the center of the logic cell row If the impedance of the power supply line becomes high and the potential of the power supply line fluctuates, there is a risk that the signal transmission speed may become slow or a logical operation may occur.
本発明の目的はかかる従来技術の欠点を除去した半導体
集積回路装置ＩＬを提供することであり、その特徴は給
電用セル内にジャンクシ冒ン谷童、ゲート容量１層問答
量を積極的にとりこんでキャパシタンスを形成し、適尚
な間隔でもってｉｂ理セル列内に該給電用セルを配置す
ることによって上ＨＣ欠点を除去し、論理セル列中央付
近の給電ラインのインピーダンスを低下させ、信号の伝
達速度を論理動作への影曽を少なくできるようにした半
導体集積回路装置である。An object of the present invention is to provide a semiconductor integrated circuit device IL that eliminates the drawbacks of the prior art, and its feature is that a single layer of gate capacitance is actively incorporated into the power supply cell. By forming a capacitance in the logic cell array and arranging the power supply cells in the ib logic cell array at appropriate intervals, the above HC defect is eliminated, the impedance of the power supply line near the center of the logic cell array is lowered, and the signal This is a semiconductor integrated circuit device in which transmission speed has less influence on logic operations.
すなわち本発明は、多層配？ＩＭ層を有し、一つまたは
複数の単位回路機能を有し、訳回路機能に紺電する複数
の給電手段とを持ち基板上での一方向の長さを統一した
論理セルと＃＠理セルで統一された一方向の長さとを同
一の一方向の長さで、核給電手段のみを有する給電用セ
ルとを複数個マトリクス的に並べて作られる牛尋体集積
回路装置にオイテ該給電用セルに積極的にキャパシタン
ｘ２形成し過当な間隔でもって＃１Ｉｌｉｉ埋セル列内
に該給電用セルを配置することを特徴とする牛導体集積
回路装置である。In other words, does the present invention have a multilayer structure? A logic cell that has an IM layer, has one or more unit circuit functions, has multiple power supply means for supplying low power to the translation circuit function, and has a unified length in one direction on the board. This power supply is applied to an integrated circuit device made by arranging a plurality of power supply cells having only a nuclear power supply means in a matrix with the same length in one direction and a power supply cell having only a nuclear power supply means. This conductor integrated circuit device is characterized in that two capacitors are actively formed in the cells, and the power feeding cells are arranged in the #1Ilii buried cell row with an excessive interval.
次に本発明の実施例について図面を参照して説明する。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例でｉ！１ｉｆｊＪＡセルのＴ
ｈｌ配廁層の給電ラインと同一間隔で配置されたｗ、１
配一層の給電ライン１１．１２、Ｐ型拡散慣域２１、ｈ
型拡散領域２２、第１配線層−拡散コンタクト３１．３
２．サブストレート−縞ｌ配ＩＮ！ｉ１層コンタク）５
１．５２、基板８１表面絶縁膜９１％第１配線層一基板
拡散領域絶縁＠９２．９３．９４で構成されている給電
用セルを示す０なお、第１図−（ａ）Ｉｄ、それを平面
的に示し、第１図（ａ）ＯＡ−に断面を第１図（ｂ）で
示している。FIG. 1 shows an embodiment of the present invention. 1ifjJA cell T
w,1 arranged at the same interval as the power supply line of the hl distribution layer
Distribution single-layer power supply line 11.12, P-type diffusion zone 21, h
Type diffusion region 22, first wiring layer-diffusion contact 31.3
2. Substrate - striped pattern IN! i1 layer contact) 5
1.52, 91% of substrate 81 surface insulating film 91% first wiring layer - substrate diffusion region insulation @92.93.94 It is shown in plan, and the cross section is shown in FIG. 1(a) OA- and FIG. 1(b).
収給１用セルにおいてはＰ型拡散領域２１と基板８１と
の間と、ｈ型拡散領域２２と基板８１との間にはジャン
クシ璽ン容量が形成され、給電ライン１１．１２とＰ型
拡歓領域２１％Ｎ型拡散顎域２２とはそれぞれ第１配線
層−拡散コンタクト３１．３２で接続されているため給
電ライン１１．１２間にはジャンクシ冒ン容量が存在す
ることになる。In the feeder 1 cell, a junction capacitance is formed between the P-type diffusion region 21 and the substrate 81 and between the H-type diffusion region 22 and the substrate 81. Since the 21% N-type diffusion jaw region 22 is connected to the first wiring layer-diffusion contacts 31 and 32, a jump capacitance exists between the power supply lines 11 and 12.
ζこで第４図（ａＪ 、 （ｂＪ 、 （Ｃｊ 、 （
ｄＪで示すようにマ） リクス的に配置された論理セル
列２にあ５図（ａＪ 、 （ｂＪ、（Ｃ）で示すように
論理セル４０間に過当な間隔で核給電用セル３を配置す
れに該給電用セル３のジャンクシ冒ン容蓋によりて給電
ラインの電位の帰れを少なくすることができひいては信
号の伝達速度と論理動作への悪影譬を少なくすることが
できる〇
また、サブストレー）−Ｍｌ配ＩｗｉＩ階コンタクト５
１．５２はサブストレート電位を決めるためのもので隣
の＠珈セル内にサブストレー）−１１自己一層コンタク
トが存在する場合はサブストレート−第１配線層コンタ
ク）５１．５２は該給電用セル内になくてもよい。ζNow, in Figure 4 (aJ, (bJ, (Cj, (
Nuclear power supply cells 3 are arranged at excessive intervals between the logic cells 40 as shown in Figure 5 (aJ, (bJ, (C)) in the logic cell array 2 arranged in a matrix as shown by dJ. In addition, the leakage of the potential of the power supply line can be reduced by using the junk cover of the power supply cell 3, thereby reducing the negative influence on the signal transmission speed and logic operation. )-Ml IwiI floor contact 5
1.52 is for determining the substrate potential, and 51.52 is for determining the substrate potential (substrate in the adjacent cell)-11 (substrate-first wiring layer contact if there is a self-single layer contact) 51.52 is in the power supply cell It doesn't have to be.
さらに本実施例においては給電ラインが２本の場合に鮫
明しているが３本以上の給電ラインの有する場合でも同
様に説明できることは明白である。Further, in this embodiment, the case where there are two power supply lines is explained, but it is clear that the same explanation can be applied to the case where there are three or more power supply lines.
第２図は本発明の一実施例で論理セルの第１配線層の給
電ラインと同一間隔で配置された第１配？＃ｊ層の給電
ライン１３．１４拡散領域２３．第１配線層４１１サブ
ストレート−第１配線層コンタクト５３、第１配線層−
拡散コンタクト３３、基板８２、表面絶縁膜９５、第１
配線層一基板拡散領域絶縁膜９６．９０で構成されてい
る給電用セルと、第２図（ｍでは平面的に示し、ｔＪＩ
Ｖ、２図（ｂＪでは第２図（１）のＨ−１１１１’断面
を示している。FIG. 2 shows an embodiment of the present invention in which first wiring lines are arranged at the same intervals as the power supply lines of the first wiring layer of the logic cell. #j layer power supply line 13.14 diffusion region 23. First wiring layer 411 substrate - first wiring layer contact 53, first wiring layer -
Diffusion contact 33, substrate 82, surface insulating film 95, first
A power supply cell composed of a wiring layer, a substrate diffusion region, and an insulating film 96.
Figure V, 2 (bJ shows the H-1111' cross section of Figure 2 (1).
骸給電用セルにおいては拡散領域２３と第１配線層４１
との閣で層間容重が形成され、拡散領域２３線第１ｆｆ
ｉ線層−拡散コンタクト３３にて給電ライン１３に接続
され、第１配線層４１は直接給電ライン１４に接続され
ているため給電ライン１３．１４間には層間容重が存在
することになる。In the skeleton power supply cell, the diffusion region 23 and the first wiring layer 41
The interlayer volume is formed in the cabinet, and the diffusion area 23 line 1ff
Since the i-line layer is connected to the power supply line 13 through the diffusion contact 33 and the first wiring layer 41 is directly connected to the power supply line 14, an interlayer volume exists between the power supply lines 13 and 14.
ここで、第４図（ａｌ 、 （ｂ） 、 （Ｃ） 、
（ｄ）で示すようにマトリクス的に配置された論理セル
列２に第５図＋８）、 （ｂＪ Ｉ （Ｃ１で示すよう
に論理セル４の間に適当な間隔で該給電用セル３を配置
すれば該給電用セル３の層間容量によって給電ツインの
電位の層れを少なくすることができ、ひいては、信号の
伝達速度と論理動作への恩影智を少なくすることができ
る。Here, Fig. 4 (al, (b), (C),
As shown in (d), the power supply cells 3 are arranged at appropriate intervals between the logic cells 4 as shown in FIG. Then, the interlayer capacitance of the power supply cell 3 can reduce the potential layering of the power supply twin, and in turn, the influence on the signal transmission speed and logic operation can be reduced.
またサブストレート−第１配線層コ／タクト５３社サブ
ストレート電位を決めるためのもので、隣の論理セル内
にサブストレート−第１配ｍ／ｉｌｉコンタクトが存在
する場合に拡、サブストレート−第１配線層コンタクト
５３は該給電用セル内になくてもよい。It is also used to determine the substrate potential of the substrate-first wiring layer. The first wiring layer contact 53 does not need to be within the power supply cell.
さらに、第２図においては拡散−第１配一層の層間容重
を利用しているが拡散領域のかわりに、他の配線層たと
えば第２配線層を利用して、第１配線層−第２配線層の
層間容を會利用しても、また、ｔａ１配縁層−＃！２配
線層の層間容量と、拡散−第１配融層の層間容量と、拡
散−第２虻巌層の層間容量を組合せて利用しても同様に
説明できることは明白である〇
さらに本実施例においては給電ラインが２本の場合につ
いて説明しているが、３本以上の場合についても同様に
説明できることは明白である。Furthermore, in FIG. 2, the interlayer volume between the diffusion region and the first wiring layer is used, but instead of the diffusion region, another wiring layer, for example, the second wiring layer, is used to connect the first wiring layer to the second wiring layer. Even if the interlayer volume of the layer is utilized, the ta1 alignment layer-#! It is clear that the same explanation can be achieved by using a combination of the interlayer capacitance of the two wiring layers, the interlayer capacitance of the diffusion-first distribution layer, and the interlayer capacitance of the diffusion-second distribution layer.Furthermore, this example Although the case where there are two power supply lines is explained in , it is clear that the same explanation can be applied to the case where there are three or more power supply lines.
第３図も本発明の一実施例で論理セルの第２配線層の給
電ラインの同一間隔で配置された第２配線層の給電ライ
ン１５．１６、Ｐ型拡散領域２４、Ｎｕ拡散領域２５、
第１配線層−第２配線層コンタクト７１．７２、第２配
線層−拡散コンタクト３５．３６．３７．３８、サブス
トレート−第１配置層コンｐクト５４．５５、第１配線
層６１．６２、Ｍ２に線層４２．４３、基板８３表面絶
縁膜９７．１９１ 。FIG. 3 also shows an embodiment of the present invention, in which the power supply lines 15 and 16 of the second wiring layer, the P-type diffusion region 24, the Nu diffusion region 25, and
1st wiring layer - 2nd wiring layer contact 71.72, 2nd wiring layer - diffusion contact 35.36.37.38, substrate - 1st arrangement layer compact 54.55, 1st wiring layer 61.62 , a line layer 42.43 on M2, and an insulating film 97.191 on the surface of the substrate 83.
ｍｌ配線層−第２配線層絶縁膜９８．１９２、第１配線
層゛一基板・拡散領域絶縁膜９９．１９３で構成されて
いる給電用セルを第３図（ａＪで平面的に示し、第３図
（ｂＪ 、 （Ｃ）では第３図（１３のｃ−ｃ’断面、
Ｄ−Ｄ’断面をそれぞれ示している。ml wiring layer - second wiring layer insulating film 98.192, first wiring layer - one substrate/diffusion region insulating film 99.193. Figure 3 (bJ, (C) shows Figure 3 (cc' cross section of 13,
A DD' cross section is shown.
該給電用セルにおいて嬬、Ｐ製拡散領域２４と基板８３
との間と、Ｊｌ拡散領域２５と基板８３との関にジャン
クシ冒ン容量が形成され、＃Ｉ２配線層４２とＰＷ拡散
領域２４との間と、第１配線層６１とＰＷ拡散領域２４
との間と、第２配線層４３とＮｆｉ拡散領域２５との間
と、第１配線層６２とΔ型拡散領域２５この間にそれぞ
れ層間容量が形成され、Ｐ型拡散領域２４は第２配線層
−拡散コンタク）３５．３６で、第２配線層４３は直接
、第１配線層６２拡第１配線層−第２配線層コンタクト
７２で第２配線層４３に接続されて給電ライン１５に接
続され、へ型拡散領域２５は第２配線層−拡散コンタク
ト３７．３８で、第２配線Ａｍ）４２は直接第１配線層
６１は第１配線層−第２配線層コンタク）７１で、第２
配線層４２に接続されて、給電ライン１６に接続されて
いる丸め、給電ライン１５．１６関には層間容量、ジャ
ンクシ冒ン容重が存在することになる。In the power supply cell, the P diffusion region 24 and the substrate 83
A junction capacitance is formed between the Jl diffusion region 25 and the substrate 83, and between the #I2 wiring layer 42 and the PW diffusion region 24, and between the first wiring layer 61 and the PW diffusion region 24.
interlayer capacitances are formed between the second wiring layer 43 and the Nfi diffusion region 25, and between the first wiring layer 62 and the Δ type diffusion region 25, and the P type diffusion region 24 is connected to the second wiring layer 43. - diffusion contact) 35.36, the second wiring layer 43 is directly connected to the second wiring layer 43 through the first wiring layer 62 expanded first wiring layer-second wiring layer contact 72 and connected to the power supply line 15. , the hemi-shaped diffusion region 25 is the second wiring layer-diffusion contact 37, 38, the second wiring Am) 42 is directly the first wiring layer 61 is the first wiring layer-second wiring layer contact) 71, the second wiring Am) 42 is
Interlayer capacitance and jump capacitance exist in the round and power supply lines 15 and 16 connected to the wiring layer 42 and connected to the power supply line 16.
ここで５１１４図（ａＪ 、 （ｂ） 、 （ＣＪ 、
（ｄＪで示すようにマトリクス的に配置された論理セ
ル列２に＃Ｉ５図（（転）。Here, 5114 figures (aJ, (b), (CJ,
(Figure #I5 in the logic cell column 2 arranged in a matrix as shown by dJ ((transfer)).
（ｂ） 、 （Ｃ）で示すように論理セル４の間に適当
な間隔で該給電用セル３を配置すれば、該給電用セル３
の層間容量、ジャンクシ冒ン容量によって給電う。If the power supply cells 3 are arranged at appropriate intervals between the logic cells 4 as shown in (b) and (C), the power supply cells 3
The power is supplied by the interlayer capacitance and the junction capacitance.
インの電位の揺れを少なくすることができ、ひいては信
号の伝達速度と論理動作への患影ＩＩＩを少なくするこ
とができる。It is possible to reduce fluctuations in the potential of the input terminal, thereby reducing the influence on the signal transmission speed and logic operation.
ｔ＋、サブストレート−第２配線層コンタクト５４．５
５は、サブストレート電位を決めるためのもので、隣の
論理セル内にサブストレー）−１２配線層コンタクトが
存在する場合はサブストレート−第２配線層コンタクト
５４．５５は該給電用セル内になくてもよい。t+, substrate-second wiring layer contact 54.5
5 is for determining the substrate potential, and if there is a substrate-12 wiring layer contact in the adjacent logic cell, the substrate-2nd wiring layer contact 54.55 is not in the power supply cell. You can.
さらに本冥施例においては給電ラインが２本の場合につ
いて説明しているが３本以上の給電ラインを有する場合
についても同様に説明できることビ明白である。Further, in this embodiment, the case where there are two power supply lines is explained, but it is obvious that the same explanation can be applied to the case where there are three or more power supply lines.
本発明は以上説明したように積極的に給電用セル内にキ
ャパシタンスを構成し、適当な間隔でもって論理セル列
内に該給電用セル内に配置することによって給電ライン
のインピーダンスを低下させる。As explained above, the present invention actively configures capacitance in the power supply cells, and lowers the impedance of the power supply line by arranging the capacitance in the power supply cells within the logic cell column at appropriate intervals.
第１図（−は本発明の給電用セルの一実施例の平面図、
第１図（ｂ）は第ｌ崗（（転）ＯＡ−Ａ’断面図、第２
図（ａｈａ本発明の給電用セルの一実施例の平面図、第
２図（ｂ）は第２図（ａ）の１１−Ｈ’断面図、第３図
（ａ）は本発明の給電用セルの一実施例の平面図、第３
図（ｂａａ第３図（ａ） （Ｄ Ｃ−Ｃ／断面図、第３
図（Ｃ）は輛３図（ａＪＯＤ−Ｄ’断面図、第４図（ａ
Ｊ 、 （ｂ） 、 （ｃ） 、 （ｄｌｒＩｉマトリ
クス的に並べられた論理セルの配置図、第５図（１、（
ｂ） 、 （Ｃ）は縞４図で示され九論理セル列内の論
理セルと、本発明の給電用セルとの配置関係を示した図
である。
尚、図において、１・・・・・・半導体基板、２・・・
・・・−塩セル列、３・・・・・・給電用セル、４・・
・・・・ｓｉ１埋セル、１１．１２．１３．１４・・・
・・・第１配線層の給電ライン、・・・・・・Ｎ型拡散
領域、３１．３２．３３・・・・・・第１配線層−拡散
コンタクト、３４．３５．３６．３７・・・・・・１Ｍ
２配線層−拡散コンタク）、４１．６１．６２・・・・
・・第１配線層、４２．４３・・・・・・＃Ｉ２配縁層
、５１．５２．５３°°。
サブストレート−第１配線層コンタクト、５４゜５５・
・・・・・サブストレート−第２配線層コンタクト、７
１ 、７２・・・・・・第１配線層−第２配線層コンタ
クト、８１．８２．８３・・・・・・基板、９１．９５
．９７．１９１・旧・・表面絶縁膜、９２．９３．９４
．９６．９０．９９．１９３−・・・・・第１配線層一
基板拡散絶縁膜、９８．１９２・旧・・第１配線層−第
２配線層絶縁膜である。
８ｌ−）−一
第１図
３
（ｂ）
（（：１）
第２図
榮４図（α）
２
第４図（ｂ）
第４図（Ｃ）
第４図（ｄ−）FIG. 1 (- is a plan view of an embodiment of the power supply cell of the present invention,
Figure 1(b) is the 1st section ((rotated) OA-A' sectional view,
Figures (aha) A plan view of an embodiment of the power supply cell of the present invention, Figure 2 (b) is a 11-H' sectional view of Figure 2 (a), and Figure 3 (a) is a plan view of an embodiment of the power supply cell of the present invention. Top view of one embodiment of the cell, 3rd
Figure (baa Figure 3 (a) (D CC/cross-sectional view, 3rd
Figure (C) is the 3rd view of the vehicle (a JOD-D' sectional view, and Figure 4 (a
J, (b), (c), (dlrIi Arrangement diagram of logic cells arranged in matrix, Fig. 5 (1, (
b) and (C) are diagrams showing the arrangement relationship between the logic cells in the nine logic cell columns and the power feeding cells of the present invention, which are shown in four striped diagrams. In the figure, 1... semiconductor substrate, 2...
...-Salt cell row, 3...Power supply cell, 4...
...si1 buried cell, 11.12.13.14...
...Power supply line of first wiring layer, ...N-type diffusion region, 31.32.33...First wiring layer-diffusion contact, 34.35.36.37... ...1M
2 wiring layer - diffusion contact), 41.61.62...
...First wiring layer, 42.43...#I2 wiring layer, 51.52.53°°. Substrate-first wiring layer contact, 54°55・
...Substrate-second wiring layer contact, 7
1, 72...First wiring layer-second wiring layer contact, 81.82.83...Substrate, 91.95
．． 97.191・Old・・Surface insulation film, 92.93.94
．． 96.90.99.193--first wiring layer-substrate diffusion insulating film, 98.192-old...first wiring layer-second wiring layer insulating film. 8l-)-1 Figure 1 3 (b) ((:1) Figure 2 Ei 4 Figure (α) 2 Figure 4 (b) Figure 4 (C) Figure 4 (d-)
Claims (1)
し、該回路機能に給電する複数の給電手段を有し、基板
上での一方向の長さを統一した論理セルと、該論理セル
で統一された一方向の長さと同一の一方向の長さで、該
給電手段のみを有する給電用セルとを複数個マトリクス
的に並べて作られる半導体集積回路装置において、該給
電用セルにキャパシタンスを形成し、所定の間隔で核論
理セル列内に骸給電用セルを配置することｆ：特徴とす
る半導体集積回路装置。A logic cell having a multilayer wiring layer, having one or more unit circuit functions, having a plurality of power supply means for supplying power to the circuit function, and having a uniform length in one direction on the substrate; In a semiconductor integrated circuit device made by arranging in a matrix a plurality of power feeding cells having only the power feeding means and having the same length in one direction as the unified length of the logic cells, the power feeding cells A semiconductor integrated circuit device characterized by forming a capacitance and arranging skeleton power supply cells in a core logic cell column at predetermined intervals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1909182A JPS58137243A (en) | 1982-02-09 | 1982-02-09 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1909182A JPS58137243A (en) | 1982-02-09 | 1982-02-09 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58137243A true JPS58137243A (en) | 1983-08-15 |
Family
ID=11989787
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1909182A Pending JPS58137243A (en) | 1982-02-09 | 1982-02-09 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58137243A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61166060A (en) * | 1985-01-17 | 1986-07-26 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| US7016089B2 (en) * | 1999-12-06 | 2006-03-21 | Canon Kabushiki Kaisha | Amplification-type solid state imaging device with reduced shading |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5248985A (en) * | 1975-10-17 | 1977-04-19 | Hitachi Ltd | Large scale integrated circuit |
-
1982
- 1982-02-09 JP JP1909182A patent/JPS58137243A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5248985A (en) * | 1975-10-17 | 1977-04-19 | Hitachi Ltd | Large scale integrated circuit |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61166060A (en) * | 1985-01-17 | 1986-07-26 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| US7016089B2 (en) * | 1999-12-06 | 2006-03-21 | Canon Kabushiki Kaisha | Amplification-type solid state imaging device with reduced shading |
| US7616355B2 (en) | 1999-12-06 | 2009-11-10 | Canon Kabushiki Kaisha | Solid-state imaging device |
| US7864384B2 (en) | 1999-12-06 | 2011-01-04 | Canon Kabushiki Kaisha | Solid-state imaging device |
| US7936487B2 (en) | 1999-12-06 | 2011-05-03 | Canon Kabushiki Kaisha | Solid-state imaging device |
| US8248677B2 (en) | 1999-12-06 | 2012-08-21 | Canon Kabushiki Kaisha | Solid-state imaging device |
| US8416473B2 (en) | 1999-12-06 | 2013-04-09 | Canon Kabushiki Kaisha | Solid-state imaging device |
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