KR20080004285A - Bitline of semiconductor device and method for fabricating the same - Google Patents

Abstract

A bitline of a semiconductor device and a method for fabricating the same are provided to reduce the loading capacitance of the bitline by extending a gap between the bitlines. A bitline of a semiconductor device includes a first lower bitline(13a), an upper bitline(15), and a second lower bitline(13c). The bitlines are arrayed on a semiconductor substrate composed of a cell region and a page buffer region. The bitlines belonging to any one of odd number-th groups and even number-th groups among the bitlines include the first upper bitline and the upper bitline. The first lower bitline is formed in a predetermined part of the cell region. The upper bit line is formed on the first lower bitline. The upper bit line extends from the page buffer region to connect the first lower bitline and the page buffer region. Bitlines belonging to the other group are formed on the same plane as the first lower bitline and connect the cell region and the page buffer region.

Description

Bitline of semiconductor device and manufacturing method thereof {Bitline of semiconductor device and method for fabricating the same}

1 is a plan view of a semiconductor device in accordance with an embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along line AA ′ of FIG. 1.

3 is a cross-sectional view taken along the line B-B 'of FIG.

4 is a cross-sectional view taken along the line CC 'of FIG.

<Explanation of symbols for the main parts of the drawings>

10 semiconductor substrate 11 first interlayer insulating film

12a, 12b, 12c, 12d: contact

13a and 13c: first and second lower bit lines

13b: conductive film

14: second interlayer insulating film

15: upper bit line

TECHNICAL FIELD The present invention relates to a bit line of a semiconductor device and a method of manufacturing the same, and more particularly, to a bit line of a semiconductor device and a method of manufacturing the same for reducing bitline loading capacitance and simplifying a process.

Currently, in the NAND flash memory, the pitch of the bit line is small and the loading capacitance of the bit line is very large. In particular, in the page buffer having a smaller pitch than the cell, the bit line loading capacitance is larger, which causes problems such as current drop and speed decrease.

Particularly, in the 70 nm technology, the page buffer is not divided into the upper and lower ends of the memory cell array in order to reduce the input / output time of the signal arriving at the page buffer and to reduce the power line delivered to the page buffer. One side page buffer scheme is used, which consists of two page buffers on either the top or bottom of the array. In this one side page buffer scheme, a metal layer must be additionally formed in order to connect between the page buffer and the bit line.

Accordingly, an object of the present invention is to provide a bit line of a semiconductor device and a method of manufacturing the same, which are devised to solve the above-described problems of the related art and can reduce bit line loading capacitance.

Another object of the present invention is to provide a bit line of a semiconductor device and a method of manufacturing the same, which can simplify the process by omitting a metal layer forming process for connecting a page buffer and a bit line.

A bit line of a semiconductor device according to an embodiment of the present invention is a semiconductor device having a plurality of bit lines arrayed on the semiconductor substrate having a cell region and a page buffer region, odd number group of the bit lines Or bit lines belonging to any one of the even-numbered groups are formed on the first lower bit line and the first lower bit line formed in a predetermined portion of the cell area and extend to the page buffer area to extend the first lower bit line. And a bit line and an upper bit line connecting the page buffer area, and bit lines belonging to another group are configured on the same plane as the first lower bit line and connect the cell area and the page buffer area. And a second lower bit line.

A method of manufacturing a bit line of a semiconductor device according to an embodiment of the present invention includes forming a conductive layer for a lower bit line on a semiconductor substrate having a cell region and a page buffer region, and etching the conductive layer for the lower bit line. Forming first lower bit lines in a predetermined portion of the region and forming second lower bit lines connecting the cell region and the page buffer region between neighboring first lower bit lines; Forming an interlayer insulating film in a portion where the conductive film is etched, forming an upper bit line conductive film on the entire surface including the first lower bit lines, and patterning the upper bit line conductive film to form the first lower bit. Forming upper bit lines connecting the lines with the page buffer area.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

1 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present invention, FIG. 2 is a cross-sectional view taken along the line A-A ', and FIG. 3 is a cross-sectional view taken along the line B-B'. 4 is a cross-sectional view taken along the line CC ′ of FIG. 1.

Referring to FIG. 1, a plurality of bit lines are arrayed on a semiconductor substrate 10 having a cell region and a page buffer region. The bit lines are divided into odd-numbered bit lines and even-numbered bit lines according to the structure.

1 and 2, the odd-numbered bit lines are formed on the first lower bit line 13a and the first lower bit line 13a formed in a predetermined portion of the cell region, and the page buffer region. The upper bit line 15 is formed to extend to connect the first lower bit line 13a and the page buffer.

The first lower bit line 13a is insulated from the semiconductor substrate 10 in the cell region by the first interlayer insulating film 11 formed on the semiconductor substrate 10, and the contact is formed in the first interlayer insulating film 11. It is electrically connected to a predetermined lower structure formed in the cell region via 12a. On the other hand, a contact 12b is formed in the first interlayer insulating film 11 of the page buffer area, and the first lower bit line 13a and a predetermined region of the contact 12b and the first interlayer insulating film 11 adjacent thereto are formed. A conductive film 13b made of the same material is formed so that the upper bit line 15 is electrically connected to a predetermined lower structure formed in the page buffer region through the conductive film 13b and the contact 12b.

Referring to FIGS. 1 and 3, the even-numbered bit line is formed on the same plane as the first lower bit line 13a and the conductive layer 13b and connects between the cell area and the page buffer area. It consists of a single layer of bit line 13c.

The second lower bit line 13c is insulated from the semiconductor substrate 10 through the first interlayer insulating layer 11, and is formed in the cell region through the contact 12c formed in the first interlayer insulating layer 11. It is electrically connected to the structure, and is electrically connected to a predetermined lower structure formed in the lower page buffer area through the contact 12d formed in the first interlayer insulating film 11.

A second interlayer insulating film 14 is formed on the first interlayer insulating film 11 on which the first and second lower bit lines 13a and 13c and the conductive film 13b are not formed. The second interlayer insulating film 14 is formed of either an oxide film or a nitride film.

The manufacturing method of such a semiconductor device is as follows.

First, a first interlayer insulating film 11 is formed on a semiconductor substrate 10 on which a cell region and a page buffer region are defined and a predetermined lower structure is formed. A plurality of contact holes are formed in the first interlayer insulating film 11 in the cell region and the peripheral circuit region, and the conductive films are filled in the contact holes to form the contacts 12a, 12b, 12c, and 12d.

Subsequently, a first lower bit line 13a is formed on a predetermined portion of the cell region including the contact 12a by etching and forming a conductive layer for the lower bit line on the entire surface of the page buffer region including the contact 12b. A conductive film 13b is formed on a predetermined portion, the cell region and the page buffer region are connected between the adjacent first lower bit lines 13a, and are connected to the lower structure of the cell region through the contact 12c. A second lower bit line 13c is formed to be connected to the lower structure of the page buffer area through 12d.

Subsequently, an insulating film is formed on the entire surface including the first lower bit line 13a, the conductive film 13b, and the second lower bit line 13c, and planarized to form a second insulating interlayer film on the portion where the lower bit line conductive film is etched. 14). The second interlayer insulating film 14 is formed of either an oxide film or a nitride film.

Subsequently, an upper bit line conductive layer is formed and patterned on the entire surface to form an upper bit line 15 connecting the first lower bit line 13a and the conductive layer 13b.

Thus, the semiconductor device manufacturing according to the embodiment of the present invention is completed.

In the above embodiment, the case where the odd-numbered bit line is configured as the first lower bit line 13a and the upper bit line 15 and the even-numbered bit line is configured as the second lower bit line 13c has been described. On the contrary, the odd bit line may be configured as the second lower bit line 13c, and the even bit line may be configured as the first lower bit line 13a and the upper bit line 15.

According to the present invention, since the adjacent bit lines are not formed on the same plane but on different planes, the interval between the bit lines, in particular, the interval between the bit lines in the page buffer area having a small pitch can be increased.

이 된다. 따라서, a'=

은 a보다 크므로 비트라인간 간격이 늘어나게 된다.Referring to FIG. 4, in the prior art in which the bit lines are arranged on the same plane, the interval between the bit lines is a, and the height of the second lower bit line 13c is h. The interval between the bit lines of 'a'

Becomes Thus, a '=

Since is larger than a, the interval between bit lines is increased.

In addition, when the bit line is formed in such a structure, the upper bit line may play a role of the metal layer in the existing one side page buffer scheme, and thus the metal layer does not need to be formed.

As described above, the present invention has the following effects.

First, the bit line loading capacitance can be reduced by increasing the interval between bit lines.

Second, since the metal layer does not need to be formed, the number of process steps can be reduced.

Claims (7)

A semiconductor device having a plurality of bit lines arrayed on a semiconductor substrate having a cell region and a page buffer region. Bit lines belonging to any one of an odd-numbered group and an even-numbered group among the bit lines may include a first lower bit line formed in a predetermined portion of the cell area and a first lower bit line formed on the first lower bit line. An upper bit line extending to a buffer area and connecting the first lower bit line and the page buffer area; The bit lines belonging to another group are formed on the same plane as the first lower bit line and include a second lower bit line connecting the cell area and the page buffer area. The semiconductor device of claim 1, wherein the first lower bit line and the second lower bit line are insulated with the semiconductor substrate and the first interlayer insulating layer interposed therebetween, and one end of the first lower bit line is disposed on the first interlayer insulating layer. A predetermined lower portion formed in the cell region through a second contact and a third contact formed in the first interlayer insulating layer, the second lower bit line being connected to a predetermined lower structure formed in the cell region through a first contact formed A bit line of a semiconductor device connected to a structure and a predetermined lower structure formed in the page buffer area. The semiconductor device of claim 1, further comprising: a conductive layer formed on a predetermined portion of the page buffer area and positioned on the same plane as the first and second lower bit lines and contacting a lower portion of the upper bit line. The bit line of the semiconductor device is insulated from the semiconductor substrate with an interlayer insulating film interposed therebetween, and connected to a predetermined structure of the page buffer region through a fourth contact formed in the first interlayer insulating film. Forming a conductive film for the lower bit line on the semiconductor substrate in which the cell region and the page buffer region are defined; A second lower bit for etching the lower bit line conductive layer to form first lower bit lines in a predetermined portion of the cell region, and connecting the cell region and the page buffer region between adjacent first lower bit lines; Forming lines; Forming an interlayer insulating film on a portion where the lower bit line conductive film is etched; Forming an upper bit line conductive film on an entire surface including the first lower bit lines; And Patterning the conductive layer for the upper bit line to form upper bit lines connecting the first lower bit lines and the page buffer region. The method of claim 4, wherein the interlayer insulating layer is formed by forming and planarizing an insulating layer on the entire surface of the first and second lower bit lines. The method of claim 4, wherein the interlayer insulating layer is formed of one of an oxide film and a nitride film. The method of claim 4, wherein a conductive film is formed on a predetermined portion of the page buffer region during the lower bit line conductive film etching process.

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