JP2005236201A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To ensure an alignment margin for a plug, and to reduce a contact resistance. <P>SOLUTION: In a semiconductor device in which a conductor film laminated on a semiconductor substrate or the conductor film through an insulating film is connected by the plugs penetrated to the insulating film, the sectional shape of the plugs is formed in a forward tapered shape. A manufacturing method for the semiconductor device has a process in which metallic films as the plugs are formed on the whole surface of the semiconductor substrate, the process, in which the metallic films are patterned in the shape of the plugs, and the process in which sections among the plugs are filled with the insulating film. According to these constitutions, the effect that the contact resistances of the plugs can be reduced is displayed because the shape of the plugs can be formed in the downward expanded forward tapered shape. Since the contact areas of the plugs are further extended, the manufacturing method is effective for ensuring alignment margins for the plugs. Since the manufacturing method can afford to a machining width, the manufacturing method can also correspond to the further shrinkage of a memory cell. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a technique effective when applied to a semiconductor device having fine contacts.

  In a semiconductor memory device such as SRAM (Static Random Access Memory), a peripheral circuit such as a decoder or an I / O control circuit for transferring data to and from the memory cell is formed around a memory cell array in which many memory cells are formed. Has been. In a memory cell array of a semiconductor memory device, memory cells are usually formed on an enormous scale of M bits, and even if a unit memory cell is slightly reduced, the entire chip is greatly reduced. Therefore, it is necessary to reduce the memory cell to the limit. There is.

  The SRAM memory cell has a configuration in which the input and output of two inverters are connected to each other. Two FETs for transfer, drive and load are formed, and a total of six FETs are formed. Metal wiring formed on the surface via an interlayer insulating film is connected. The metal wiring and the main surface of the semiconductor substrate or other metal wiring are connected by a plug penetrating the interlayer insulating film.

  In order to reduce the memory cell area and reduce the cost or increase the storage capacity, the miniaturization of the FET constituting the SRAM has been promoted. Therefore, a contact plug for connecting the wiring is formed. In this case, it is necessary to form a fine contact hole for forming a plug in a narrow source region or drain region adjacent to the gate electrode, and the contact hole alignment margin is reduced.

  For this reason, for example, Patent Document 1 below discloses a technique for securing a matching margin by using materials having different etching selection ratios for the sidewalls of the gate electrode and the interlayer insulating film.

Japanese Patent Laid-Open No. 11-87657

  However, in the technique disclosed in Patent Document 1, the etching selectivity is limited to the insulating film material used for the interlayer insulating film and the sidewall, and in some cases, the optimum material may not be selected.

  Further, when the contact hole is processed by dry etching using gas, the shape of the hole is a reverse taper shape in which the upper part of the wall surface is expanded by about 5 ° to 10 °. For this reason, for example, when an opening having a width of 160 nm is provided in an interlayer insulating film having a thickness of 500 nm, the width of the bottom surface of the contact hole is narrowed to about 116 nm to 72 nm due to the inclination. This causes a problem that the contact resistance with the substrate increases. In order to prevent this, if the interlayer insulating film is thinned, the interlayer dielectric strength is deteriorated.

An object of the present invention is to provide a technique capable of solving these problems, ensuring a plug alignment margin, and reducing contact resistance.
The above and other problems and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
In a semiconductor device in which a conductor film laminated on a semiconductor substrate or conductor film via an insulating film is connected by a plug penetrating the insulating film, the cross-sectional shape of the plug is a forward tapered shape.

  The manufacturing method includes a step of forming a metal film to be the plug over the entire surface of the semiconductor substrate, a step of patterning the metal film into a shape of a plug, and a step of filling an insulating film between the plugs.

  According to the present invention described above, the plug can have a forward taper shape that extends downward, thereby reducing the contact resistance of the plug. In addition, since the connection area of the plug is increased, it is effective for securing a plug alignment margin. Further, since there is a margin for the etching process, it is possible to cope with further reduction of the memory cell.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
(1) According to the present invention, there is an effect that the shape of the plug can be a forward taper shape extending downward.
(2) According to the present invention, due to the effect (1), since the connection area of the plug is secured, the contact resistance of the plug can be reduced.
(3) According to the present invention, the connection area of the plug is increased by the effect (1), and therefore, there is an effect that it is effective for securing a plug alignment margin.
(4) According to the present invention, the interlayer insulating film is filled between the plugs formed by etching away the metal film, so that there is an effect that the processing becomes easy.
(5) According to the present invention, due to the effect (4), since there is a margin in the processing width, there is an effect that it is possible to cope with further reduction of the memory cell.
(6) According to the present invention, due to the effect (4), it is possible to secure a plug alignment margin even when the memory cell is further reduced.
(7) According to the present invention, the above effect (5) has an effect of improving the yield of the semiconductor device because the position defect of the plug is reduced.

Embodiments of the present invention will be described below.
Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  1 and 2 are partial plan views showing SRAM memory cells which are semiconductor devices according to an embodiment of the present invention. FIG. 1 shows a state before plug formation, and FIG. 2 shows a state after plug formation. ing. FIG. 3 is a partial longitudinal sectional view taken along line aa in FIG. 1, and FIG. 4 is a partial longitudinal sectional view taken along line aa in FIG.

  In the SRAM shown in FIG. 1 or FIG. 2, the area surrounded by a two-dot chain line is one memory cell, and the n-type driving FET Qd and transfer FET Qt are combined with the p-type load FET Ql. The complementary inverter is cross-connected.

  In the active region where each FET is formed, the source region 4 and the drain region 4 of the FET are formed in the active region of the FET in which the well 2 formed in the semiconductor substrate 1 using silicon is separated by the trench-shaped isolation insulating film 3. A gate electrode 6 is formed on the main surface of the semiconductor substrate with a gate insulating film 5 interposed therebetween. Sidewalls 7 are formed on the side surfaces of the gate electrode 6, and the upper surface of the gate electrode 6 is covered with an insulating film 8 such as silicon oxide.

  In the memory cell circuit, the common gate electrode 4 serving as an input of one inverter, the drain region 4 of the driving FET serving as the output of the other inverter, the drain region 4 of the load FET, and one end of the transfer FET Qt are broken lines. Are connected by an in-cell wiring L shown in FIG. Each gate electrode 4 of the memory cell extends in the x direction in FIGS.

  In the memory cell array, a large number of these memory cells are arranged in a vertical and horizontal pattern in a symmetrical pattern, and are connected to each other by an upper layer metal wiring to constitute a memory cell array. In the upper metal wiring, the power supply wiring is connected to the source region 4 of the load FET Ql, the ground wiring is connected to the source region 4 of the driving FET Qd, the gate electrode 4 of the transfer FET Qt is connected to the word line, The other end 4 of the FET Qt is connected to the data line. The metal wiring and the main surface of the semiconductor substrate are connected by a contact plug 9, adjacent memory cells share the contact plug 9, and the space between the contact plugs 9 is filled with an interlayer insulating film 10.

  In a semiconductor memory device, a plurality of memory cell arrays in which a large number of memory cells are formed are formed, and a peripheral circuit such as a decoder or an I / O control circuit for transferring data to and from the memory cell array is formed around each memory cell array. Has been.

  In the case of a memory cell, since the entire circuit scale is large, even if the memory cell is slightly reduced, the entire chip has a large area. Therefore, it is necessary to reduce the memory cell to the limit. However, in the case of a peripheral circuit, since the circuit scale is small, the influence of the reduction on the entire semiconductor chip is small. Therefore, as shown in the partial plan view in FIG. 5, the FET is formed with a margin for the element area. Yes.

  Each FET source region 4, drain region 4 and gate electrode 6 is connected to a plug 9 for electrical connection with an upper wiring layer. The contact layer plug 9 of the present embodiment is shown in FIG. Thus, the shape is a forward tapered shape in which the lower surface of the wall surface is expanded to about 5 ° to 10 °.

  In the present embodiment, unlike the conventional plug having a reverse tapered shape, the shape of the plug 9 is a forward tapered shape extending downward, so that the source region 4 or the drain region 4 and the plug 9 Since the connection area can be secured, the contact resistance of the plug 9 can be reduced.

Subsequently, a method for manufacturing a semiconductor device in which the plug 9 is formed will be described step by step with reference to FIGS.
First, an impurity is implanted into a semiconductor substrate 1 such as n-type single crystal silicon using a mask patterned with an oxide film, and the implanted impurity is annealed to form a well 2. Subsequently, a trench-shaped isolation insulating film 3 is formed on the main surface of the semiconductor substrate 1 to isolate the active regions of the FETs. A gate insulating film 5 such as silicon oxide is formed in the active region of the FET, a metal film is laminated on the polycrystalline silicon film, and a gate electrode 6 patterned by covering the upper surface with the insulating film 8 is formed.

  Subsequently, impurities are implanted using the gate electrode 6 as a mask, the implanted impurities are annealed by heat treatment to form the source region 4 and the drain region 4, and silicon oxide is deposited on the entire surface of the semiconductor substrate 1, for example. Etching is performed to form sidewalls 7 on the side surfaces of the gate electrode 6. This state is the state shown in FIGS.

  Next, as shown in FIG. 6 which is a longitudinal sectional view taken along line bb in FIG. 1, a metal film 9 'using tungsten is formed on the entire surface of the semiconductor substrate, and planarized by CMP (Chemical Mechanical Polishing). Then, a slit-like resist mask 11 extending in the y direction is formed by photolithography. Using this resist mask 11, the metal film 9 ′ is patterned into a line pattern extending in the y direction in FIGS. 1 and 2 by dry etching using gas, as shown in a partial plan view in FIG. 7. The cross-sectional shape of the line pattern is a forward taper shape in which the lower side of the wall surface is expanded by about 5 ° to 10 °.

  Next, as shown in a longitudinal sectional view along the line aa in FIG. 8, a slit-like resist mask 12 extending in the x direction is formed by photolithography, and the resist mask 12 is used to supply gas. The metal film 9 ′ having a line pattern is separated into the y-direction and patterned into contact plugs 9 by dry etching that is used.

  The FET of the peripheral circuit may be similarly patterned from the metal film 9 ′ in the line pattern to the contact plug 9, or the metal film 9 ′ may be patterned into the contact plug 9 by one patterning. Since the necessity for miniaturization is lower than that of the memory cell, various methods can be considered for forming the plug.

  Next, as shown in a longitudinal sectional view along the line aa in FIG. 10, an interlayer insulating film 10 using a silicon oxide film or the like is formed on the entire surface of the semiconductor substrate, and planarized by CMP. As shown in FIG. 4, the upper surface of the plug 9 is exposed. Thus, the space between the plugs 9 is filled with the interlayer insulating film 10 to form a contact layer of the wiring layer.

  Thereafter, a metal wiring layer of a metal film using copper is separated and laminated on the contact layer by an interlayer insulating film, and as a wiring between memory cells or a power wiring, between each memory cell and between the memory cell array and the peripheral circuit Are connected to each other to form a memory circuit, and a protective film covering the whole is formed, and openings such as pads are provided in the protective film to complete a semiconductor memory device.

  On the other hand, in the conventional plug formation, an interlayer insulating film 10 using silicon oxide is first formed on the entire surface of the semiconductor substrate 1 from the state shown in FIGS. A planarization process is performed by CMP (Chemical Mechanical Polishing), and a resist mask 13 having an opening in the plug formation region is formed by photolithography. Using this resist mask 13, holes of a pattern of plugs 9 are formed by dry etching using a gas as shown in FIG. Next, as shown in FIG. 13, a metal film 9 ′ using tungsten or the like is formed on the entire surface of the semiconductor substrate 1, and planarization is performed by CMP to form plugs 9 as shown in FIG. 14.

  Thus, unlike the conventional method of forming the contact plug by etching the interlayer insulating film 10, in this embodiment, the contact plug 9 is formed by etching the metal film 9 ′. It is a forward tapered shape whose shape is expanded downward. For this reason, since a connection area with the source region 4 or the drain region 4 can be secured, the contact resistance can be reduced.

  Further, in the memory cell shown in FIG. 2, the size of the entire memory cell is 2000 nm × 870 nm, and the processing of the wiring layer is accurate in the processing in the y direction orthogonal to the gate electrode 6 extending in the x direction. It will be required. For example, in processing in the y direction, if the width of the gate electrode 6 is 80 nm and the width of the sidewall 7 is 55 nm to 60 nm, the width to both ends of the sidewall 7 is 190 nm to 200 nm, and the remaining width of 470 nm to 490 nm is 160 nm. Two contact plugs 9 are formed.

  In the conventional method in which the hole is formed by etching the interlayer insulating film 10, a 160 nm hole has to be formed for the plug 9, but the interlayer between the plug 9 formed by removing the metal film 9 ′ is removed. In the plug of the present embodiment that fills the insulating film 10, since the processing with a width of 235 nm to 245 nm is performed for the interlayer insulating film 10, the processing becomes easy.

  Further, even when finer processing is performed in order to reduce the memory cell, it is difficult to reduce the contact hole due to the resolution limit in the conventional contact hole formation, and the alignment margin can be reduced as shown in FIG. However, since the processing width of the method of this embodiment has a margin, the processing width of the interlayer insulating film 10 can be reduced as shown in FIG. 16 to cope with further reduction of the memory cell. It is possible.

  For this reason, in this embodiment, the alignment margin of the plug 9 does not need to be reduced, so that the position defect of the plug 9 is reduced, and the yield of the semiconductor device is improved. In addition, the shape of the plug 9 is a forward tapered shape, and the connection area is increased, which is effective for securing the alignment margin of the plug 9.

  Further, in this embodiment, the metal film 9 ′ is removed by etching, and the insulating interlayer insulating film 10 is filled thereafter, so that even if the etching reaches the sidewall 7 or the insulating film 8, Since the insulator is filled by the subsequent formation of the interlayer insulating film 10, there is no possibility of short circuit.

  Although the present invention has been specifically described based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and it is needless to say that various changes can be made without departing from the scope of the invention. It is.

  For example, in the above description, the plug connected to the source region, the drain region, or the gate electrode has been described as an example. However, the present invention may be applied to a plug that connects a wiring and a wiring stacked through an interlayer insulating film. Good. Further, although the semiconductor memory device has been described, other semiconductor devices such as an SRAM embedded system LSI can be applied as long as the semiconductor device has a plug.

It is a fragmentary top view which shows the memory cell of the semiconductor device which is one embodiment of this invention. It is a fragmentary top view which shows the memory cell of the semiconductor device which is one embodiment of this invention. It is a longitudinal cross-sectional view along the aa line in FIG. It is a longitudinal cross-sectional view along the aa line in FIG. It is a fragmentary top view which shows FET of the peripheral circuit of the semiconductor device which is one embodiment of this invention. It is a longitudinal cross-sectional view which shows the semiconductor device which is one embodiment of this invention for every process. It is a fragmentary top view which shows the semiconductor device which is one embodiment of this invention for every process. It is a longitudinal cross-sectional view which shows the semiconductor device which is one embodiment of this invention for every process. It is a longitudinal cross-sectional view which shows the semiconductor device which is one embodiment of this invention for every process. It is a longitudinal cross-sectional view which shows the semiconductor device which is one embodiment of this invention for every process. It is a longitudinal cross-sectional view which shows the conventional semiconductor device for every process. It is a longitudinal cross-sectional view which shows the conventional semiconductor device for every process. It is a longitudinal cross-sectional view which shows the conventional semiconductor device for every process. It is a longitudinal cross-sectional view which shows the conventional semiconductor device for every process. It is a longitudinal cross-sectional view which shows the case where the conventional semiconductor device is miniaturized. It is a longitudinal cross-sectional view which shows the case where the semiconductor device which is one embodiment of this invention is miniaturized.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Well, 3 ... Isolation insulating film, 4 ... Source region, drain region, 5 ... Gate insulating film, 6 ... Gate electrode, 7 ... Side wall, 8 ... Insulating film, 9 ... Plug, 10 ... Interlayer insulating film 11, 12, 13 ... resist mask, L ... in-cell wiring, Qd ... drive FET, Qt ... transfer FET, Ql ... load FET.

Claims (5)

In a semiconductor device in which a conductor film laminated via an insulating film on a semiconductor substrate or a conductor film is connected by a plug penetrating the insulating film,
A semiconductor device characterized in that a cross-sectional shape of the plug is a forward tapered shape. 2. The semiconductor device according to claim 1, wherein a cross-sectional shape of the plug is a forward taper shape in which a wall surface is inclined downward at about 5 ° to 10 °. In a semiconductor device manufacturing method in which a conductor film laminated on a semiconductor substrate or a conductor film via an insulating film is connected by a plug penetrating the insulating film,
Forming a metal film to be the plug on the entire surface of the semiconductor substrate;
Patterning the metal film into a plug shape;
And a step of filling an insulating film between the plugs. In a semiconductor device manufacturing method in which a conductor film laminated on a semiconductor substrate or a conductor film via an insulating film is connected by a plug penetrating the insulating film,
Forming a metal film to be the plug on the entire surface of the semiconductor substrate;
A step of planarizing the metal film;
Forming a slit-like resist mask extending in one direction, and using this resist mask, patterning the metal film into a line pattern;
Forming a slit-like resist mask extending in another direction orthogonal to the one direction, and using this resist mask, patterning the metal film of the line pattern into a plug shape;
Forming an insulating film on the entire surface of the semiconductor substrate;
A method of manufacturing a semiconductor device, comprising: planarizing the insulating film, exposing the upper surface of the plug by the planarizing process, and filling the insulating film between the plugs. The semiconductor device according to claim 3, wherein the patterning is performed by dry etching using a gas.

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