CN215600368U

CN215600368U - Semiconductor structure

Info

Publication number: CN215600368U
Application number: CN202121406701.7U
Authority: CN
Inventors: 詹益旺; 林刚毅; 刘安淇; 颜逸飞; 童宇诚
Original assignee: Fujian Jinhua Integrated Circuit Co Ltd
Current assignee: Fujian Jinhua Integrated Circuit Co Ltd
Priority date: 2021-06-23
Filing date: 2021-06-23
Publication date: 2022-01-21
Anticipated expiration: 2031-06-23

Abstract

The utility model discloses a semiconductor structure, which comprises a substrate, wherein the substrate comprises a peripheral area and a memory area. A first dielectric layer is on the substrate. A contact structure is located in the first dielectric layer on the peripheral region of the substrate. A second dielectric layer is on the first dielectric layer and on both sides of the contact structure. An interconnect structure is located on the second dielectric layer. A passivation layer covers a top surface of the contact structure, a sidewall of the second dielectric layer, and a sidewall of the interconnect structure.

Description

Semiconductor structure

Technical Field

The present invention relates to a semiconductor structure. More particularly, the present invention relates to a Dynamic Random Access Memory (DRAM) including a memory region and a peripheral region.

Background

A Dynamic Random Access Memory (DRAM) is a type of volatile memory. DRAM devices generally include a memory area composed of a memory cell array, and a peripheral area composed of a control circuit. The control circuitry in the peripheral region may address and electrically connect to each memory cell in the memory region via a plurality of column word lines (word lines) and a plurality of row bit lines (bit lines) that traverse the memory region to perform reading, writing or erasing of data. In advanced semiconductor manufacturing, the chip size of DRAM devices can be greatly reduced by adopting an architecture of buried word lines or buried bit lines, by which the active regions of memory cells can be arranged at a dense pitch to achieve higher cell density.

In the process of manufacturing a DRAM device, semiconductor devices of a memory cell and a peripheral circuit are simultaneously formed through the same manufacturing process. Therefore, it is important to provide a peripheral semiconductor device that is compatible with the fabrication process of the memory cell.

SUMMERY OF THE UTILITY MODEL

An object of the present invention is to provide a semiconductor structure. The semiconductor structure has a memory region and a peripheral region, wherein a contact structure of the peripheral region of the semiconductor structure is formed simultaneously with a storage node contact of a memory cell in the memory region by the same manufacturing process. The contact structure provided by the utility model can be used as an interconnection element of a peripheral circuit in a peripheral area of a semiconductor structure.

In one aspect, a semiconductor structure is provided that includes a substrate including a peripheral region and a memory region. A first dielectric layer is on the substrate. A contact structure is located in the first dielectric layer on the peripheral region of the substrate. A second dielectric layer is on the first dielectric layer and on both sides of the contact structure. An interconnect structure is located on the second dielectric layer. A passivation layer covers a top surface of the contact structure, a sidewall of the second dielectric layer, and a sidewall of the interconnect structure.

In another aspect, a semiconductor structure is provided that includes a substrate including a peripheral region and a memory region. A first dielectric layer is on the substrate. A second dielectric layer is on the first dielectric layer. An opening is located in the peripheral region of the substrate and includes a lower portion through the first dielectric layer and an upper portion through the second dielectric layer. An interconnect structure is located on the second dielectric layer and on both sides of the opening. A contact structure is located within the lower portion of the opening. A passivation layer covers a top surface of the contact structure, a sidewall of the second dielectric layer, and a sidewall of the interconnect structure.

In yet another aspect, the present invention provides a semiconductor structure comprising a substrate, a first dielectric layer on the substrate, a contact structure in the first dielectric layer, a second dielectric layer on the first dielectric layer and on both sides of the contact structure, wherein a distance between the second dielectric layers on both sides of the contact structure is greater than a width of the contact structure, and a passivation layer covering a top surface of the contact structure and a sidewall of the second dielectric layer.

In yet another aspect, the present invention provides a semiconductor structure that includes a substrate, a first dielectric layer on the substrate, and a second dielectric layer on the first dielectric layer. An opening including a lower portion through the first dielectric layer and an upper portion through the second dielectric layer, wherein a width of the upper portion is greater than a width of the lower portion. A contact structure is located within the lower portion of the opening. A passivation layer covers a top surface of the contact structure and a sidewall of the second dielectric layer.

Drawings

The accompanying drawings are included to provide a further understanding of the embodiments, and are incorporated in and constitute a part of this specification. The drawings and description serve to explain the principles of some embodiments. It should be noted that all the drawings are schematic drawings, and the relative sizes and proportions are adjusted for the purpose of illustration and drawing convenience. The same reference signs represent corresponding or similar features in different embodiments.

Figure 1 is a schematic top view of a semiconductor structure according to one embodiment of the present invention.

Fig. 2 to 10 are schematic diagrams illustrating sequential steps of a method for fabricating a semiconductor structure according to a first embodiment of the present invention.

Fig. 11 and 12 are schematic cross-sectional views illustrating a semiconductor structure according to a second embodiment of the present invention, wherein fig. 11 and 12 correspond to the steps shown in fig. 7 and 8, respectively.

Fig. 13 is a cross-sectional view of a semiconductor structure according to a third embodiment of the present invention, and corresponds to the step shown in fig. 10.

Fig. 14 is a cross-sectional view of a semiconductor structure according to a fourth embodiment of the present invention, and corresponds to the step shown in fig. 10.

Wherein the reference numerals are as follows:

100 semiconductor structure

200 semiconductor structure

300 semiconductor structure

400 semiconductor structure

10 substrate

10A peripheral region

10B memory area

14 isolation structure

22 semiconductor part

24 metal part

26 hard mask portion

32 spacer

34 first dielectric layer

36 second dielectric layer

38 patterned masking layer

38a mask opening

42 first contact opening

42a lower part

42b upper part

44 second contact opening

46 storage node contact opening

52 conductive layer

53A air gap

53B air gap

54 passivation layer

62 third dielectric layer

63A air gap

161 doped region

162 doped region

AA area

BB region

CC region

BL bit line

C1 contact structure

C2 contact structure

CP contact pad

E1 etching process

E2 recessing process

E3 etching process

G2 gate structure

M1 interconnection structure

S1 semiconductor part

SNC storage node contact

SNCP contact pad

Width of W1

Width of W2

P air gap opening

Detailed Description

In order to make the present invention more comprehensible to those skilled in the art, preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings. It is to be understood that the following illustrative embodiments may be implemented by replacing, recombining, and mixing features of several different embodiments without departing from the spirit of the present disclosure.

Fig. 1 is a schematic top view of a semiconductor structure 100 according to an embodiment of the present invention. As shown in fig. 1, the semiconductor structure 100 includes a substrate 10, and a peripheral region 10A and a memory region 10B are defined on the substrate 10. It should be noted that the shape and layout of the peripheral region 10A and the memory region 10B shown in fig. 1 are for convenience of illustration and are not intended to limit the present invention.

The peripheral area 10A may be provided with peripheral circuits for controlling the operation and input/output of the memory cells in the memory area 10B, such as drivers, buffers, amplifiers, and decoders, but is not limited thereto. The peripheral region 10A may further include a circuit for repairing an abnormal memory cell, such as a fuse (fuse) circuit. According to an embodiment of the present invention, as shown in fig. 1, the peripheral area 10A may include an area AA and an area BB for disposing different types of circuits. The memory area 10B may include an area CC for arranging an array of memory cells, such as DRAM cells. According to an embodiment of the present invention, the semiconductor devices of the peripheral circuits in the peripheral region 10A and the DRAM cells in the memory region 10B are integrally fabricated and simultaneously formed on the substrate 10 by the same fabrication process.

Fig. 2 to 10 are schematic diagrams illustrating sequential steps of a method for fabricating a semiconductor structure 100 according to a first embodiment of the present invention. The semiconductor structure 100 shown in fig. 2-10 may have the substrate 10 as well as the peripheral region 10A and the memory region 10B as shown in fig. 1. The left portion of fig. 2-10 are cross-sectional views of area AA of the peripheral area 10A of the semiconductor structure 100. The middle portion of fig. 2 to 10 is a schematic cross-sectional view of a region BB of the peripheral region 10A of the semiconductor structure 100. The right portion of fig. 2-10 are cross-sectional views of region CC of memory region 10B of semiconductor structure 100.

Referring to fig. 2, a substrate 10 is provided, and a plurality of isolation structures 14, such as Shallow Trench Isolations (STI), are formed in the substrate 10 to define a plurality of active regions (active regions) of a semiconductor device (not shown) in a peripheral region 10A of the substrate 10 and to define a plurality of active regions of a memory cell (not shown) in a memory region 10B of the substrate 10. In addition, a plurality of buried word lines (not shown) may be formed in the substrate 10 through active regions (not shown) of the memory cells.

As shown in fig. 2, the gate structure G2 and the plurality of bit lines BL may be simultaneously formed on the peripheral region 10A and the memory region 10B of the substrate 10 through the same manufacturing process. For example, a semiconductor material layer (not shown), a metal material layer (not shown) and a hard mask material layer (not shown) may be sequentially formed on the peripheral region and the memory region of the substrate 10. Then, a patterning process (e.g., a photolithography and etching process) may be performed to pattern the hard mask material layer, and then an etching process may be performed using the patterned hard mask material layer as an etching mask to etch and remove the unnecessary portions of the semiconductor material layer and the metal material layer, thereby obtaining the gate structure G2 and the bit line BL.

As shown in fig. 2, gate structure G2 and bit line BL include semiconductor portion 22, metal portion 24 on semiconductor portion 22, and hard mask portion 26 on metal portion 24, respectively. The material of semiconductor portion 22 may comprise polysilicon, in accordance with an embodiment of the present invention. The material of the metal portion 24 may include aluminum (Al), tungsten (W), copper (Cu), titanium (Ti), titanium-aluminum alloy (TiAl), or other low resistivity metal material. The material of the hard mask portion 26 may include silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), or other suitable dielectric material. A gate dielectric layer (not shown) may be disposed between substrate 10 and semiconductor portion 22 of gate structure G2.

Please refer to fig. 3. Next, spacers 32 may be formed on sidewalls of the gate structure G2 and the bit line BL, and the area AA of the peripheral area 10A of the substrate 10 may be

formedDoped regions

161 and 162 are formed within the active region (not shown) in BB. It should be noted that the positions of the doped

regions

161 and 162 shown in fig. 3 are for example and should not be taken as a limitation of the present invention. Subsequently, a first dielectric layer 34 may be formed on the substrate 10, and the first dielectric layer 34 may be planarized to remove a portion of the first dielectric layer 34 until the top surfaces of the gate structure G2 and the bit line BL are exposed from the first dielectric layer 34. Next, a second dielectric layer 36 is formed on the first dielectric layer 34 and covers the exposed top surfaces of the gate structure G2 and the bit line BL. According to an embodiment of the present invention, the material of the first dielectric layer 34 and the second dielectric layer 36 may include silicon oxide (SiO)₂) Silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), or other suitable dielectric material. According to an embodiment of the utility model, the first dielectric layer 34 may comprise silicon oxide (SiO)₂) The second dielectric layer 36 may include silicon nitride (SiN), but is not limited thereto.

According to an embodiment of the present invention, the method for forming the spacers 32 may include, for example, first depositing at least one spacer material layer (not shown) on the substrate 10 and conformally covering the top surfaces and sidewalls of the gate structure G2 and the bit line BL. The spacer material layer may then be subjected to an etching process, such as a dry etching process, to anisotropically etch and remove the undesired portions of the spacer material layer, while the remaining portions of the spacer material layer on the sidewalls of the gate structure G2 and the bit line BL become the spacers 32. According to an embodiment of the present invention, the material of the spacer 32 may include silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), or other suitable dielectric material. According to an embodiment of the present invention, the spacers 32 on the sidewalls of the gate structure G2 and the bit line BL may have a single-layer structure or a multi-layer structure, respectively.

Please refer to fig. 4. Subsequently, a patterned masking layer 38 may be formed on second dielectric layer 36. Patterned masking layer 38 may include a plurality of mask openings 38a that expose predetermined portions of second dielectric layer 36.

Please refer to fig. 5. Subsequently, an etch process E1, such as a dry etch process, is performed using patterned masking layer 38 as an etch mask to etch away exposed portions of second dielectric layer 36 and first dielectric layer 34 through mask opening 38a, thereby forming first contact opening 42, second contact opening 44, and storage node contact opening 46. In detail, the first contact opening 42 is located on an area AA of the peripheral area 10A of the substrate 10, passes through the second dielectric layer 36 and the first dielectric layer 34 and exposes a portion of the doped region 161. The second contact opening 44 is located on a region BB of the peripheral region 10A of the substrate 10, passes through the second dielectric layer 36 and the first dielectric layer 34 and exposes portions of the doped regions 162 on both sides of the gate structure G2. The storage node contact opening 46 is located on a region CC of the memory region 10B of the substrate 10, passes through the first dielectric layer 34 between the second dielectric layer 36 and the bit line BL and exposes a portion of the active area of the memory cell (the exposed portion of the substrate 10 of the region CC).

Please refer to fig. 6. After removal of patterned masking layer 38, semiconductor portion S1 is then selectively formed over the exposed active area of the memory cell (the exposed portion of substrate 10 of region CC), such that semiconductor portion S1 fills the lower portion of storage node contact opening 46. Subsequently, a conductive layer 52 is formed on the second dielectric layer 36, and the conductive layer 52 fills the first contact opening 42, the second contact opening 44 and the storage node contact opening 46. The material of the conductive layer 52 may include a metal, such as tungsten (W). According to an embodiment of the present invention, as shown in fig. 6, when the widths of the first contact opening 42 and the second contact opening 44 are small, and/or by controlling the gap filling capability of the conductive layer 52, an air gap 53A and an air gap 53B sealed by the conductive layer 52 may be formed in the first contact opening 42 and the second contact opening 44, respectively.

Please refer to fig. 7. Subsequently, another patterned mask layer (not shown) is formed on the conductive layer 52 to cover a predetermined portion of the conductive layer 52, and then a recess process E2 is performed using the patterned mask layer (not shown) as an etching mask to etch and pattern the conductive layer 52 on the second dielectric layer 36 while removing a portion of the conductive layer 52 located in the upper portion 42b of the first contact opening 42, thereby simultaneously forming a contact structure C1 located in the lower portion 42a of the first contact opening 42, a contact structure C2 located in the second contact opening 44, and a contact pad CP of the contact structure C2, a storage node contact SNC located in the storage node contact opening 46, and a contact pad SNCP of the storage node contact SNC, and an interconnect structure M1 located above the second dielectric layer 36 on both sides of the first contact opening 42. It is noted that the portion of the second dielectric layer 36 exposed from the upper portion 42b of the first contact opening 42 is also removed in the recess process E2, and thus the width W2 of the upper portion 42b of the first contact opening 42 is greater than the width W1 of the lower portion 42a of the first contact opening 42 after the recess process E2, as shown in fig. 7.

According to an embodiment of the present invention, the sidewalls of the interconnect structure M1 and the sidewalls of the second dielectric layer 36 on both sides of the upper portion 42b of the first contact opening 42 may be aligned with each other, as shown in fig. 7.

In accordance with an embodiment of the present invention, the recess process E2 may remove portions of the first dielectric layer 34 by down-etching while widening the upper portion 42b of the first contact opening 42, resulting in recessed sidewalls of the first dielectric layer 34 exposed from the upper portion 42b of the first contact opening 42. Due to the different etch rates of the first dielectric layer 34 and the conductive layer 52 at the recess process E2, the top surface of the contact structure C1 may protrude from the concave sidewalls of the first dielectric layer 34. According to an embodiment of the present invention, after the recessing process E2, the air gap 53A may still be sealed in the conductive layer 52 of the first contact opening 42 without being exposed.

Please continue to refer to fig. 7. The contact pad CP of the contact structure C2 protrudes from the second contact opening 44 and extends laterally to cover portions of the second dielectric layer 36 on both sides of the second contact opening 44. The contact pads SNCP of the storage node contacts SNC protrude from the storage node contact openings 46 and laterally extend to cover portions of the second dielectric layer 36 on both sides of the storage node contact openings 46. According to an embodiment of the present invention, during the recess process E2, the portion of the second dielectric layer 36 not covered by the contact pad CP of the interconnect structure M1, the contact structure C2, and the contact pad SNCP of the storage node contact SNC is also removed, thereby exposing the portion of the upper surface of the first dielectric layer 34 around the second contact opening 44. According to an embodiment of the present invention, the exposed upper surface of the first dielectric layer 34 may have a concave profile.

Please refer to fig. 8. Subsequently, a passivation layer 54 is formed on the substrate 10 such that the passivation layer 54 covers the contact structure C1, the interconnect structure M1, and sidewalls and a top surface of the contact pad CP of the contact structure C2 and the contact pad SNCP of the storage node contact SNC. According to an embodiment of the present invention, the material of the passivation layer 54 may include silicon nitride (SiN).

Please refer to fig. 9. Subsequently, an etching process E3, for example, an anisotropic dry etching process, may be performed to remove portions of the passivation layer 54 until the top surface of the interconnect structure M1, the top surface of the contact pad CP of the contact structure C2, and the top surface of the contact pad SNCP of the storage node contact SNC are exposed.

It is noted that, as shown in the left portion of fig. 9, after the etching process E3, a portion of the remaining passivation layer 54 may become a spacer covered along a portion of the top surface of the contact structure C1, the sidewalls of the second dielectric layer 36 exposed from the upper portion 42b of the first contact opening 42, and the sidewalls of the interconnect structure M1, and the bottom is lower than the bottom of the second dielectric layer 36. According to an embodiment of the present invention, the contact structure C1 may be partially removed in the etching process E3, such that a portion of the top surface of the contact structure C1 is exposed from the passivation layer 54 and the air gap 53A in the contact structure C1 is opened. In other words, the top of the air gap 53A may have an air gap opening P.

It is also noted that, as shown in the middle portion of fig. 9, after the etching process E3, a portion of the remaining passivation layer 54 may become a spacer along the sidewall of the contact pad CP of the contact structure C2 and the sidewall of the second dielectric layer 36 under the contact pad CP. The surfaces of the hard mask portion 26 and the first dielectric layer 34 of the gate structure G2 may be exposed from the passivation layer 54. As shown in the right portion of fig. 9, a portion of the remaining passivation layer 54 may fill the hard mask portion 26 between the contact pads SNCP of the storage node contacts SNC and completely cover the bit lines BL.

Please refer to fig. 10. Subsequently, a third dielectric layer is formed on the interconnect structure M1, the contact pad CP and the contact pad SNCP62 and the third dielectric layer 62 completely fills the gap between the upper portion 42b of the first contact opening 42 and the contact pad CP and is in direct contact with the contact structure C1. Notably, the air gaps 53A opened by the etch process E3 are in turn sealed by the third dielectric layer 62. The material of the third dielectric layer 62 may include silicon oxide (SiO)₂) Or silicon nitride (SiN), but is not limited thereto. In a subsequent fabrication process (not shown), the third dielectric layer 62 may be planarized, and then interconnection structures (not shown) electrically connected to the contact pads CP of the contact structure C1, the contact structure C2, and the contact pad SNCP of the storage node contact SNC, respectively, may be formed in the third dielectric layer 62.

In summary, one aspect of the present invention provides a semiconductor structure 100 including a substrate 10, the substrate 10 including a peripheral region 10A and a memory region 10B, a first dielectric layer 34 on the substrate 10, and a contact structure C1 in the first dielectric layer 34 on the peripheral region 10A. The second dielectric layer 36 is located on the first dielectric layer 34 and on both sides of the contact structure C1. An interconnect structure M1 is located on the second dielectric layer 36. The passivation layer 54 covers a top surface of the contact structure C1, a sidewall of the second dielectric layer 36, and a sidewall of the interconnect structure M1.

Another aspect of the present invention provides a semiconductor structure 100 comprising a substrate 10, a first dielectric layer 34 located on the substrate 10, a second dielectric layer 36 located on the first dielectric layer 34, and an opening (first contact opening) 42 located on the substrate 10, wherein the opening comprises a lower portion 42a extending through the first dielectric layer 34 and an upper portion 42b extending through the second dielectric layer 36. The semiconductor structure 100 further includes an interconnect structure M1 on the second dielectric layer 36 on both sides of the opening (first contact opening) 42, a contact structure C1 on the lower portion 42a of the opening (first contact opening) 42, and a passivation layer 54 covering the top surface of the contact structure C1, the sidewalls of the second dielectric layer 36, and the sidewalls of the interconnect structure M1.

According to an embodiment of the present invention, the width W2 of the upper portion 42b of the opening (first contact opening) 42 is greater than the width W1 of the lower portion 42a of the opening (first contact opening) 42. The distance between the second dielectric layers 36 on both sides of the contact structure C1 is substantially equal to the width W2, and the width of the contact structure C1 is substantially equal to the width W1, i.e., the distance between the second dielectric layers 36 on both sides of the contact structure C1 is greater than the width of the contact structure.

According to an embodiment of the utility model, a portion of the top surface of the contact structure C1 may be exposed from the passivation layer 54. That is, the passivation layer 54 covers a portion of the top surface of the contact structure C1.

According to an embodiment of the utility model, the air gap 53A in the contact structure C1 may be exposed from the passivation layer 54. The top of the air gap 53A has an air gap opening P.

According to an embodiment of the present invention, the sidewalls of the second dielectric layer 36 and the sidewalls of the interconnect structure M1 are aligned with each other.

According to an embodiment of the present invention, the passivation layer 54 covers a concave sidewall of the first dielectric layer 34. The top surface of the contact structure C1 may protrude from the concave sidewalls of the first dielectric layer 34.

According to an embodiment of the present invention, the semiconductor structure 100 further includes a third dielectric layer 62 on the interconnect structure M1, filling in between the second dielectric layer 36 and the interconnect structure M1 on both sides of the contact structure C1, filling the upper portion 42b of the opening (first contact opening) 42 and sealing the air gap 53A.

According to an embodiment of the present invention, the semiconductor structure 100 further comprises a plurality of bit lines BL on the substrate 10 and a plurality of storage node contacts SNC on the substrate 10 and between the bit lines BL, wherein a top surface of the interconnect structure M1 and a top surface of the storage node contacts SNC are flush with each other.

Hereinafter, various embodiments of the present invention will be described in detail. For simplicity of description, the same components in the following embodiments are denoted by the same reference numerals. To facilitate understanding of differences between the various embodiments, differences between the different embodiments will be described below, and like features will not be described again.

Fig. 11 and 12 are schematic cross-sectional views of a semiconductor structure 200 according to a second embodiment of the present invention, wherein fig. 11 and 12 correspond to the steps shown in fig. 7 and 8, respectively. The second embodiment shown in fig. 11 and 12 is different from the first embodiment shown in fig. 7 and 8 in that the top of the air gap 53A in the contact structure C1 can be opened during the recess process E2 to have the air gap opening P by adjusting the position of the top of the air gap 53A and/or the amount of over-etching of the first dielectric layer 34 in the recess process E2 as shown in fig. 11, and then the air gap 53A can be sealed again by the passivation layer 54 as shown in fig. 12 and subsequently opened again by the etching process E3 (see fig. 9).

Fig. 13 is a cross-sectional view of a semiconductor structure 300 according to a third embodiment of the present invention, and corresponds to the step shown in fig. 10. The third embodiment shown in fig. 13 differs from the first embodiment shown in fig. 10 in that, as shown in fig. 13, the conductive layer 52 may completely fill the first contact opening 42 and the second contact opening 44 without forming an air gap in the first contact opening 42 and the second contact opening 44. Thereafter, a passivation layer 54 is formed to cover the top surface of the contact structure C1, the sidewalls of the second dielectric layer 36 and the sidewalls of the interconnect structure M1, and then a third dielectric layer 62 is formed on the interconnect structure M1 such that the opening (first contact opening) 42 is completely filled with the third dielectric layer 62.

Fig. 14 is a cross-sectional view of a semiconductor structure 400 according to a fourth embodiment of the present invention, and corresponds to the step shown in fig. 10. The fourth embodiment shown in fig. 14 differs from the first embodiment shown in fig. 10 in that, as shown in fig. 14, the conductive layer 52 may completely fill the first contact opening 42 and the second contact opening 44 without forming an air gap in the first contact opening 42 and the second contact opening 44, and the third dielectric layer 62 filled in the upper portion 42b of the first contact opening 42 may form a sealed air gap 63A between the spacer (the remaining passivation layer 54).

In summary, the present invention provides a semiconductor structure having a contact structure formed in a peripheral region by the same manufacturing process as a storage node contact of a memory cell of a memory region, which can be used as an interconnection element of a peripheral circuit.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor structure, comprising:

a substrate including a peripheral region and a memory region;

a first dielectric layer on the substrate;

a contact structure in the first dielectric layer on the peripheral region of the substrate;

a second dielectric layer on the first dielectric layer and on both sides of the contact structure; an interconnect structure on the second dielectric layer; and

a passivation layer covers a top surface of the contact structure, a sidewall of the second dielectric layer, and a sidewall of the interconnect structure.

2. The semiconductor structure of claim 1, wherein a distance between the second dielectric layers on both sides of the contact structure is greater than a width of the contact structure.

3. The semiconductor structure of claim 1, wherein the passivation layer covers a portion of the top surface of the contact structure.

4. The semiconductor structure of claim 1, wherein the contact structure comprises a gap and a top portion of the gap has a gap opening.

5. The semiconductor structure of claim 1, wherein the sidewalls of the second dielectric layer and the sidewalls of the interconnect structure are aligned with each other.

6. The semiconductor structure of claim 1, wherein the first dielectric layer comprises a concave sidewall, the concave sidewall being covered by the passivation layer.

7. The semiconductor structure of claim 6, wherein the top surface of the contact structure protrudes from the recessed sidewalls of the first dielectric layer.

8. The semiconductor structure of claim 1, further comprising a third dielectric layer on the interconnect structure and filling between the second dielectric layers on both sides of the contact structure.

9. The semiconductor structure of claim 1, further comprising:

a plurality of bit lines on the memory region of the substrate;

and a plurality of storage node contacts on the substrate and between the bit lines, wherein a top surface of the interconnect structure and a top surface of the storage nodes are flush with each other.

10. A semiconductor structure, comprising:

a substrate;

a first dielectric layer on the substrate;

a contact structure in the first dielectric layer;

a second dielectric layer on the first dielectric layer and on both sides of the contact structure, wherein a distance between the second dielectric layers on both sides of the contact structure is greater than a width of the contact structure; and

a passivation layer covers a top surface of the contact structure and a sidewall of the second dielectric layer.

11. The semiconductor structure of claim 10, wherein the contact structure comprises a gap and a top portion of the gap has a gap opening.

12. The semiconductor structure of claim 10, further comprising a third dielectric layer on the passivation layer and filling in between the second dielectric layers on both sides of the contact structure.