JPS63202941A - Wiring path for semiconductor device - Google Patents
Wiring path for semiconductor deviceInfo
- Publication number
- JPS63202941A JPS63202941A JP3645387A JP3645387A JPS63202941A JP S63202941 A JPS63202941 A JP S63202941A JP 3645387 A JP3645387 A JP 3645387A JP 3645387 A JP3645387 A JP 3645387A JP S63202941 A JPS63202941 A JP S63202941A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- type semiconductor
- electromagnetic waves
- wiring path
- signal transmission
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 239000004020 conductor Substances 0.000 claims abstract description 18
- 230000008054 signal transmission Effects 0.000 claims abstract description 12
- 239000012212 insulator Substances 0.000 claims abstract description 5
- 230000000694 effects Effects 0.000 abstract description 7
- 239000000758 substrate Substances 0.000 abstract description 7
- 230000006698 induction Effects 0.000 abstract description 3
- 230000007257 malfunction Effects 0.000 abstract description 3
- 230000002238 attenuated effect Effects 0.000 description 3
- 230000003313 weakening effect Effects 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000002500 effect on skin Effects 0.000 description 1
- 230000005674 electromagnetic induction Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の配線路の構造に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to the structure of a wiring path in a semiconductor device.
従来、半導体装置の配線路は、アルミ金属などの電導膜
または不純物をドーピングし活性化した多結晶シリコン
膜或いはそれらの合金から成る単一膜によって構成され
る。Conventionally, a wiring path in a semiconductor device is constituted by a single film made of a conductive film such as aluminum metal, a polycrystalline silicon film doped with impurities and activated, or an alloy thereof.
しかし、この単一膜からなる従来の配線路は、外部から
到達する電磁波または隣接する他の内部配線路に流れる
スイッチング電流の影響を受は誘導電圧を発生して回路
装置を誤動作せしめる要因を作る。特に回路動作が高速
になると配線路自身のスイッチング動作による電磁誘導
効果も無視できなくなり、配線路に対して分布定数系の
考慮をしなければなれなくなる。However, conventional wiring paths made of a single film are affected by electromagnetic waves arriving from the outside or switching currents flowing in other adjacent internal wiring paths, which generates induced voltages that cause circuit devices to malfunction. . In particular, as circuit operation becomes faster, the electromagnetic induction effect due to the switching operation of the wiring path itself cannot be ignored, and a distributed constant system must be taken into account for the wiring path.
本発明の目的は、上記の状況に鑑み、それ自身が電磁波
の発生源となることは勿論他からの電極誘導効果の影響
を受けることなき半導体装置の配線路を提供することで
ある。In view of the above circumstances, an object of the present invention is to provide a wiring path for a semiconductor device that does not itself become a source of electromagnetic waves and is not affected by electrode induction effects from other sources.
本発明によれば、半導体装置の配線路は、信号伝路層と
、前記信号伝送路を絶縁体層を介し静電遮蔽する接地導
体層とを含む積層体から構成される。According to the present invention, a wiring path of a semiconductor device is composed of a laminate including a signal transmission layer and a ground conductor layer that electrostatically shields the signal transmission path via an insulating layer.
以下図面を参照して本発明の詳細な説明する。 The present invention will be described in detail below with reference to the drawings.
第１図は本発明の一実施例を示す一部断面を含む斜視図
である。本実施例によればＰ型半導体基板１と、この基
板上にドーピングされたｎ型半導体層２と、ｎ型半導体
層２上に載置された絶縁体層３．信号伝路層４．絶絶縁
層５および接地導体層６の積層体からなる配線路１０を
含む。さらにここで、Ｉ！、およびｅ２はｎ型半導体層
２と接地電導体層６とをそれぞれ接地する導体を示す。FIG. 1 is a partially sectional perspective view showing an embodiment of the present invention. According to this embodiment, a P-type semiconductor substrate 1, an n-type semiconductor layer 2 doped on this substrate, an insulator layer 3 placed on the n-type semiconductor layer 2. Signal transmission layer 4. It includes a wiring path 10 made of a laminate of an insulating layer 5 and a ground conductor layer 6. Furthermore, I! , and e2 indicate conductors that ground the n-type semiconductor layer 2 and the ground conductor layer 6, respectively.
かかる構造の配線路−１０によれば、外部の発生源から
到来する電磁波は接地されたｎ型半導体層２と接地導体
層６の表皮効果により減衰されるので信号伝路層４に誘
導される誘導電圧は微弱である。According to the wiring path 10 having such a structure, electromagnetic waves arriving from an external source are attenuated by the skin effect of the grounded n-type semiconductor layer 2 and the grounded conductor layer 6, and are therefore guided to the signal transmission layer 4. The induced voltage is weak.
また、信号伝路層４の電圧が高速にスイッチングしたと
きに発生ずる電磁波も同様にｎ型半導体層２と接地導体
層６との表面効果によって減衰され、他への影響を微弱
にし、更に信号伝路層４自身に対する分布定数系の効果
も減少させることか可能となる。In addition, the electromagnetic waves generated when the voltage of the signal transmission layer 4 is switched at high speed are similarly attenuated by the surface effect of the n-type semiconductor layer 2 and the ground conductor layer 6, weakening the influence on others, and further weakening the signal. It is also possible to reduce the effect of the distributed constant system on the transmission layer 4 itself.
第２図は本発明の他の実施例を示す一部断面を含む斜視
図である。本実施例によれば、Ｐ型半導体基板１と、フ
ィールド絶縁膜７と、フィールド絶縁膜７上に載置され
た信号伝路層４．絶絶縁層５および接地導体層６の積層
体から成る配線路−λ曳を含む。ここで、ａ２は接地導
体層２を接地する導体である。本実施例によれば、配線
路２０は配線路上面からの到来電磁波を接地導体層６に
よって減衰させ、また、下面からの電磁波は接地された
半導体基板１の裏面によって減衰される。FIG. 2 is a partially sectional perspective view showing another embodiment of the present invention. According to this embodiment, a P-type semiconductor substrate 1, a field insulating film 7, and a signal transmission layer 4 placed on the field insulating film 7. It includes a wiring path-λ track consisting of a laminate of an insulating layer 5 and a ground conductor layer 6. Here, a2 is a conductor that grounds the ground conductor layer 2. According to this embodiment, the wiring path 20 attenuates electromagnetic waves arriving from the top surface of the wiring path by the grounded conductor layer 6, and electromagnetic waves coming from the bottom surface are attenuated by the grounded back surface of the semiconductor substrate 1.
本実施例によれば配線構造を簡略化し得る利点がある。This embodiment has the advantage of simplifying the wiring structure.
以上詳細に説明したように、本発明によれば、半導体装
置の配線路は信号伝路層を静電遮蔽する接地導体を備え
るので、外部からの到来電磁波によって誘導電圧を誘起
して回路装置を誤動作せしめなり、或いは配線自身が電
磁波の発生源となる問題点が解決される。特に高集積化
、高速化が要求される今日の半導体装置では内部配線相
互の各信号間による電磁波の相互影響の度合がまずます
大きくなりつつあるので、これを防ぎ得る本発明の効果
はきわめて顕著である。As described above in detail, according to the present invention, the wiring path of a semiconductor device is provided with a ground conductor that electrostatically shields the signal transmission layer, so that an induced voltage is induced by electromagnetic waves arriving from the outside, and the circuit device is Problems such as malfunction or the wiring itself becoming a source of electromagnetic waves are solved. In particular, in today's semiconductor devices that require higher integration and higher speed, the degree of mutual influence of electromagnetic waves between signals in internal wiring is becoming increasingly large, so the effect of the present invention in preventing this is extremely significant. It is.
第１図は本発明の一実施例を示す一部断面を含む斜視図
、第２図は本発明の他の実施例を示す一部断面を含む斜
視図である。
１０．２０・・・配線路、１・・・Ｐ型半導体基板、２
・・・ｎ型半導体層、３．５・・・絶縁体層、４・・・
信号伝路層、６・・・接地導体層、７・・・フィールド
絶縁膜、ｌｌ、（２２・・・接地導体。
−５＝
革Ｊ 図
第２図FIG. 1 is a partially cross-sectional perspective view showing one embodiment of the present invention, and FIG. 2 is a partially cross-sectional perspective view showing another embodiment of the present invention. 10.20... Wiring path, 1... P-type semiconductor substrate, 2
... n-type semiconductor layer, 3.5 ... insulator layer, 4 ...
Signal transmission layer, 6... Ground conductor layer, 7... Field insulating film, ll, (22... Ground conductor. -5= Leather J Figure 2
Claims (1)
遮蔽する接地導体層とを含む積層体から成ることを特徴
とする半導体装置の配線路。1. A wiring path for a semiconductor device, comprising a laminate including a signal transmission layer and a ground conductor layer that electrostatically shields the signal transmission layer via an insulator layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3645387A JPS63202941A (en) | 1987-02-18 | 1987-02-18 | Wiring path for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3645387A JPS63202941A (en) | 1987-02-18 | 1987-02-18 | Wiring path for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63202941A true JPS63202941A (en) | 1988-08-22 |
Family
ID=12470238
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3645387A Pending JPS63202941A (en) | 1987-02-18 | 1987-02-18 | Wiring path for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63202941A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6490549A (en) * | 1987-10-01 | 1989-04-07 | Seiko Epson Corp | Wiring method for metallic oxide film semiconductor type high breakdown-voltage driver |
| JPH0282531A (en) * | 1988-09-19 | 1990-03-23 | Nec Corp | Semiconductor device |
| JPH0430452A (en) * | 1990-05-25 | 1992-02-03 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit device |
-
1987
- 1987-02-18 JP JP3645387A patent/JPS63202941A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6490549A (en) * | 1987-10-01 | 1989-04-07 | Seiko Epson Corp | Wiring method for metallic oxide film semiconductor type high breakdown-voltage driver |
| JPH0282531A (en) * | 1988-09-19 | 1990-03-23 | Nec Corp | Semiconductor device |
| JPH0430452A (en) * | 1990-05-25 | 1992-02-03 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit device |
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