JPH0456355A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To arrange a larger number of input/output interface cells by providing power supply wirings including the linear portions overlapping with arrangement of input/output interface cells and angular portions bent along the angular portions of a semiconductor chip and forming the angular portions as the multilayer portion which is narrower than the linear portions. CONSTITUTION:The linear portions 15a, 15b are respectively formed by a single conductive metal layer. Meanwhile, the angular portions 16a, 16b are respectively formed as a multilayer portion of a plurality of conductive metal layers which are thicker and narrower than the linear portions 15a, 15b. Since the angular portions 16a, 16b are narrow, the linear portions 15a, 15b are formed longer corresponding to reduction of width and the areas on the surface 13 occupied by the angular portions 16a, 16b are reduced. Thereby, the areas allowing formation of interface cell is increasing at the areas near the angular portions of surface 13 depending on such reduced areas and the interface cell 11a indicated by a broken line is provided adjacent to the arrangement of interface cell 11 in such increased region.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit device, and in particular to a semiconductor integrated circuit device having a plurality of input/output interface cells on the outer periphery of a semiconductor chip, such as a mask slice method, a gelt array method, a standard cell method, etc. The present invention relates to a semiconductor integrated circuit device in which are arranged.

[Prior Art] A mask slice type semiconductor integrated circuit device has a desired wiring pattern formed on a semiconductor chip called a mask slice in which a large number of basic cells and a large number of input/output interface cells are regularly arranged. It is configured.

A large number of basic cells constitute a functional block, and electrical connections are made through internal wiring such as signal lines and basic cell power supply wiring in wiring channels on the semiconductor chip. Further, a large number of interface cells constitute an input/output interface circuit, and are electrically connected to power supply wiring for the input/output interface circuit formed on the semiconductor chip.

FIG. 4 shows the configuration of the vicinity of the corner of the semiconductor chip in which the power supply wiring for the input/output interface circuit is formed in this manner.

In the same figure,! Several input/output interface cells 31 are arranged on the outer periphery of the surface 33 of the semiconductor chip 32 . Power supply wiring for the turnout interface circuit 34a, 34
b is the plane 3 along this array of interface cells 31.
3 and interface cell 3I, and is electrically connected to a predetermined portion of each interface cell 31.

The power supply wiring 34a is a wiring connected to a high potential power supply that supplies, for example, V4d (power supply voltage).
b is a wiring connected to a low potential power source that supplies GND (ground voltage), for example. The power supply wirings 3b and 34b are configured to have a wider width than internal wiring arranged in a wiring channel (not shown) so that a larger amount of current flows through them.

The power supply wiring 34a, 34b is as shown in FIG.
It includes straight portions 35a, 35b formed overlapping the arrangement of the interface cells 31, and corner portions 36g, 36b bent along the corners of the surface 33 that cannot be formed overlapping the interface cells 21.

[Problems to be Solved by the Invention] In semiconductor integrated circuit devices, it is generally desired to form more input/output interface cells on a semiconductor chip in order to improve the processing function of the input/output interface circuit.

However, as mentioned above, in conventional semiconductor integrated circuit devices, input/output interface cells cannot be provided in areas near the corners of the semiconductor chip to form curved corner portions of power supply wiring for input/output interface circuits. There is a problem that the area becomes large.

SUMMARY OF THE INVENTION In view of these conventional problems, it is an object of the present invention to provide a semiconductor integrated circuit device in which more input/output interface cells can be arranged on a semiconductor chip.

[Means for Solving the Problems] In order to achieve the above-mentioned object, the present invention includes a semiconductor chip, a plurality of input/output interface cells arranged on the outer periphery of the semiconductor chip, and a predetermined method for the input/output interface cells. The power supply wiring is formed on the semiconductor chip to supply voltage and includes a straight part that overlaps the array of input/output interface cells and a corner part that curves along the corner of the semiconductor chip. It is characterized by being formed in multiple layers with a width narrower than that of the straight portion.

[Operations] In the semiconductor integrated circuit device of the present invention, a plurality of input/output interface cells are arranged on the outer periphery of the semiconductor chip. The power supply wiring is formed on the semiconductor chip and includes a straight portion that overlaps the array of input/output interface cells and a corner portion that curves along the corner of the semiconductor chip. The corner portions are formed in multiple layers with a narrower width than the straight portions. For example, if a straight section is constructed from a single metal layer,
By constructing the corner portions from multiple metal layers, the corner portions can thus be formed into multiple layers narrower than the straight portions. Therefore, the area occupied by the corner portion on the semiconductor chip can be reduced in the area near the corner of the semiconductor chip while maintaining the electrical resistance of the corner portion as low as that of the straight portion. Therefore, the straight line portion and the semiconductor chip portion in which input/output interface cells can be formed increase near this corner by this reduced area. As a result, it becomes possible to arrange more people interface cells in the area near the corner of the semiconductor chip.

These effects of the present invention will become clearer from the following examples of the present invention, and other effects of the present invention will become clearer.

[Example code] Embodiments of the present invention will be described based on the drawings.

FIG. 1 shows a mask slicing semiconductor integrated circuit device 1!10 which is an embodiment of the present invention.

In the figure, a semiconductor integrated circuit device 1o includes a semiconductor chip 12, a large number of input/output interface cells 11 arranged on the outer periphery of a surface 13 of the chip 12, and a large number of basic cells formed in the center of the surface 13. 17.

A large number of regularly arranged basic cells I7 are connected to the circuit device 1.
0, and electrical connections are made in the wiring channel 18 on the semiconductor chip I2 by internal wiring such as signal lines and basic cell power supply wiring (not shown).

A large number of interface cells 11 constitute an input/output interface circuit. each interface cell 11
A predetermined portion of is electrically connected to an input/output interface circuit power supply wiring I4 connected to an external power supply.

The power supply wiring 14 is connected to the interface cells 11 in order to supply a predetermined voltage to a large number of interface cells 11.
are formed on the surface 13 and the interface cells 12 along the array.

FIG. 2 shows an enlarged view of the structure near the corner of the semiconductor chip 12 of the circuit device 10. As shown in FIG.

In the figure, the power supply wiring includes two power supply wirings 14a114.
Contains b. The power supply wiring 14a is a wiring connected to a high potential power supply that supplies Vdd, for example, and is connected to the power supply wiring 1
4b is a wiring connected to, for example, a low potential power source that supplies GND or the ground. The power supply wiring 14g and 14b are
Compared to internal wiring (not shown) arranged in the wiring channel 18, it is configured to be wider so that more current can flow therethrough.

The power supply wiring 14a, 14b is as shown in FIG.
A straight line portion 151.15b formed overlapping the array of interface cells 11 and a semiconductor chip I2 formed on the surface 13 where no interface cells 11 are arranged.
It includes corner portions 16g and 16b bent along the corners of. In the figure, the straight portions 15aS15b are shown with single hatching, and the corner portions 16aS16b are shown with double hatching. Straight line portions 15a, 15b
are each constructed from a single conductive metal layer. On the other hand, corner part 16! , 16b are each formed in a multilayered manner by a plurality of conductive metal layers, and the straight portions 15a, 15b
It is thicker and narrower. Especially corner part 1
The thickness and width of 6aS16b are selected such that its electrical resistance is the same as that of the straight portions 15a and 15b, respectively. Therefore, for example, the corner portions 16a, 16b
In order to make the width narrower, the thickness should be made thicker.

Since the width of the corner portions 16i and 16b is narrow, as is clear from FIG. 2, compared to the conventional example shown in FIG. Straight section 15 depending on width! , 15b are longer, and the area occupied by the corner portions 16as 16b on the surface 13 is smaller. Therefore, in accordance with this reduced area, the area where interface cells can be formed increases near the corners of surface I3, and in this increased area, interface cells lla shown by broken lines are adjacent to the array of interface cells 11. It is arranged as follows. in this way,
Compared to the conventional example, in this example, in the area near the corner of the surface 13, the number of interface cells is increased by the number of interface cells lla.

FIG. 3 shows an enlarged view of the structure near the corner of a semiconductor chip of a semiconductor integrated circuit device according to another embodiment of the present invention.

In the figure, the input/output interface circuit power supply wiring provided on the surface 23 of the semiconductor chip 22 includes two power supply wirings 24! , 24b. Power wiring 241.2
4b is a straight line portion 25a, 25b formed overlappingly on the array of input/output interface cells 21, and a corner curved along the corner of the semiconductor chip 22 formed on the surface 23 where the interface cell 21 is not arranged. part 26i,
26b. In the figure, the straight part 25g
, 25b are single hatched, and the corner portions 28a, 2
6b are each indicated by double hatching. corner part 2
61.26b are each formed in multiple layers using a plurality of conductive metal layers, and are thicker and narrower than the straight portions 25a and 25b made of a single conductive metal layer. The thickness and width of the corner portions 26a and 26b are such that the electrical resistance is equal to that of the straight portion 25! , 25b, respectively.

Since the width of the corner portions 26a and 26b is narrow, as is clear from FIG. 3, compared to the case where the straight line portion and the corner portion are formed with the same width as in the conventional example shown in FIG. The length of the straight portion 25b increases in accordance with the width, and the area occupied by the corner portions 26a, 26b on the surface 23 decreases. Therefore, in accordance with this reduced area, the area where an interface cell can be formed increases near the corners of the surface 23, and the interface cell 21! shown by a broken line is formed in this increased area. is located. In this way, in this embodiment, especially the power supply wiring 24a and the power supply wiring 24a,
The interface cell 21a is arranged by using the area of the surface 23 provided between the power supply wirings 4b and 4b.

Compared to the conventional example, in this example, in the region near the corner of the surface 23, the number of interface cells is increased by the number of interface cells 21a.

[Effects of the Invention] As explained above, according to the semiconductor integrated circuit device of the present invention, the power supply wiring has a straight portion on the semiconductor chip that overlaps with the array of input/output interface cells, and a corner curved along the corner of the semiconductor chip. Since the corner part is formed in a multi-layer structure with a width narrower than the straight part, the electrical resistance of the corner part can be maintained as low as that of the straight part, and the electrical resistance of the corner part can be maintained as low as that of the straight part. The area occupied can be reduced in regions near the corners of the semiconductor chip. Therefore, the straight line portion and the semiconductor chip portion in which input/output interface cells can be formed increase near this corner by this reduced area. As a result, more input/output interface cells can be arranged in areas near the corners of the semiconductor chip. Therefore, it is possible to provide a semiconductor integrated circuit device in which more input/output interface cells can be arranged on a semiconductor chip.

[Brief explanation of drawings]

FIG. 1 is a plan view of the main part configuration of a semiconductor integrated circuit which is an embodiment of the present invention, FIG. 2 is a partially enlarged plan view of FIG. 1, and FIG. 3 is a partially enlarged plan view of another embodiment of the present invention. 4 are partially enlarged plan views of a conventional semiconductor integrated circuit device. lO...Semiconductor integrated circuit device, Il, Ila
, 21.21a... Input/output interface cell, 12.22... Semiconductor chip, 13.23
・・・plane, 14.14a 14b 24a 24b
---Power supply wiring, 15a, 15b, 25a, 2
5b, --- straight line part, 16a1.6b, 26a,
26b...corner part, 17...basic cell, 18...wiring channel. Figure 1 Figure 3 Figure 2 Figure 5b 4b Figure 4

Claims (1)

[Claims] a semiconductor chip; a plurality of input/output interface cells arranged on the outer periphery of the semiconductor chip; and a plurality of input/output interface cells formed on the semiconductor chip for supplying a predetermined voltage to the input/output interface cells. A power supply wiring including a straight line portion overlapping the cell arrangement and a corner portion curved along the corner of the semiconductor chip, and the corner portion is formed in a multi-layer structure having a width narrower than the straight line portion. A semiconductor integrated circuit device characterized by: