JP2544749B2 - Semiconductor integrated circuit - Google Patents

Description

The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having a GND wiring and a power supply wiring.

[Conventional technology]

Conventionally, in a semiconductor integrated circuit, a GND wiring and a power wiring connected to an external GND terminal and a power supply terminal are wired together with wiring for other signals and the like on a wiring layer. For this reason, these GND wiring and power supply wiring are extended around the chip to extend to a predetermined location in order to avoid short circuit with other wiring.

Also, the amount of current flowing through the GND wiring and power supply wiring is large, and especially at the core of the wiring, the total current flowing through the integrated circuit chip is concentrated, so wiring with a cross-sectional area that can withstand this amount of current should be used. There is a need to. In this case, since the thickness of the wiring is constant, the width of the wiring is increased to cope with this.

Furthermore, since the amount of current in the GND wiring and power supply wiring decreases toward the end, the wiring area is reduced by gradually narrowing the wiring width, and as a result, the width of the wiring increases from the trunk to the end. It was getting thinner.

[Problems to be solved by the invention]

In the conventional semiconductor integrated circuit described above, in the layout design when determining the patterning of the GND wiring and the power supply wiring, it is necessary to consider a wiring pattern of a complicated shape for routing these wirings There was a problem that required a lot of effort to make a decision.

Also, by increasing the width of the trunk of the wiring,
There is also a problem that the area of the chip is increased correspondingly, which is an obstacle to miniaturization of the chip.

Furthermore, at the ends of these wirings, the wiring resistance increases due to the long distance from the electrode to the end and the wiring width gradually becoming smaller, causing the GND level to float, the power supply level to drop, and the GND wiring and power supply wiring to There is also the problem of being vulnerable to riding noise.

An object of the present invention is to provide a semiconductor integrated circuit capable of solving all the above problems.

[Means for solving problems]

A semiconductor integrated circuit of the present invention is formed by sequentially laminating a plurality of wiring layers insulated by an interlayer insulating film on a semiconductor substrate on which elements are formed, and of these wiring layers, the lowest layer closest to the semiconductor substrate is formed. A wiring layer is formed over substantially the entire surface of the semiconductor substrate, the lowermost wiring layer is connected to one of a GND electrode and a power supply electrode, and at least one wiring layer above the lowermost wiring layer is connected to a signal wiring. It is configured as a wiring layer for.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a perspective view showing a wiring layer of a semiconductor integrated circuit of an embodiment of the present invention in an exploded and hierarchized manner. Each of (a) and (b) in FIGS. 2 to 4 shows different contacts. FIG. 3 is a partial plan view of a hole portion and a sectional view taken along the line AA.

In FIG. 1, 1 is a substrate made of a silicon plate on which a transistor pattern before the wiring layer is already formed,
For this substrate 1, the first wiring layer 2, the second wiring layer 3 and the third wiring layer 3
The wiring layer 4 is sequentially laminated with interlayer insulating films 11, 12 and 13 interposed therebetween. Here, the first and second wiring layers 2 and 3 are patterned so as to cover the entire chip, and the third wiring layer 4 is formed in a required wiring pattern. Further, 14 is a protective film.

Then, it is assumed here that the first wiring layer 2 is configured as a GND layer and the second wiring layer 3 is configured as a power supply layer. The first wiring layer 3 is connected to the GND electrode 7 provided in a part of the third wiring layer 4 by the contact hole 5 formed in the interlayer insulating films 12 and 13, and the second wiring layer 3 is connected to the interlayer insulating film 1.
The contact hole 6 opened in 3 connects to the power supply electrode 8 provided in a part of the third wiring layer 4.

In FIGS. 2A and 2B, 9 indicates a part of an element such as a transistor on the substrate 1, which is formed in a region defined by the element decomposition insulating film 10. A part 9a of the element 9 is connected to the first wiring layer 2 through a contact hole 11a formed in the insulating layer 11 provided on the substrate 1 and is connected to GND.

Further, in FIGS. 3A and 3B, the element 9
The other portion 9b is connected to the second wiring layer 3 through the contactor holes 11b and 12b formed in the interlayer insulating film 11 and the interlayer insulating film 12, and is connected to the power source. In this case, the first wiring layer 2 has a hole 2b that is slightly larger than the contact hole, so that the second wiring layer 3 is not short-circuited.

Further, in FIGS. 4A and 4B, the other portion 9c of the element 9 is connected to the third wiring layer 4 by the contact holes 11c, 12c and 13c formed in the interlayer insulating films 11, 12 and 13, respectively. It Also in this case, the holes 2c formed in the first wiring layer 2 and the holes 3c formed in the second wiring layer 3 prevent each wiring layer from being short-circuited.

Therefore, according to this structure, the first wiring layer 2 is connected to the GND electrode 7, and the second wiring layer 3 is connected to the power supply electrode 8.
Configured as GND wiring and electrode wiring, respectively. Since these wirings are formed in a layer different from the third wiring layer 4 as a wiring pattern, the degree of freedom in designing the circuit pattern can be increased and an effective circuit design can be realized. Also, GN
Since the D wiring and the power wiring are formed over almost the entire surface of the chip, it is possible to obtain a sufficient withstand voltage, and to increase the thickness of the terminal wiring connected to this to the required thickness to reduce its resistance. You can Although the three-layer wiring has been described in the embodiment, the same applies to a semiconductor integrated circuit having four or more wiring layers.

〔The invention's effect〕

As described above, according to the present invention, among the wiring layers laminated on the semiconductor substrate, the lowermost wiring layer closest to the semiconductor substrate is formed over substantially the entire surface of the semiconductor substrate, and the lowermost wiring layer is the GND electrode. Alternatively, since it is connected to one of the power supply electrodes and is configured as a wiring layer for at least one signal wiring in an upper wiring layer than the lowermost wiring layer, the labor particularly at the time of layout design of the signal wiring is reduced. In addition to reducing the wiring resistance and increasing the current-carrying capacity of the wiring, the coupling capacitance between the signal wiring and the element is suppressed to reduce the power supply level drop or the GND level floating and reduce noise fluctuations. There is an effect that can be strong.

[Brief description of drawings]

FIG. 1 is a schematic perspective view of an embodiment of the present invention disassembled by layers, FIGS. 2 to 4 show different contact hole portions, and in each drawing, (a) is a partial plan view,
(B) is sectional drawing which follows the AA line. 1 ... Silicon substrate, 2 ... First wiring layer, 3 ... Second wiring layer, 4 ... Third wiring layer, 5,6 ... Contact hole,
7 ... GND electrode, 8 ... power electrode, 9 ... element, 9a, 9b, 9
c …… Part of the element, 10 …… Element isolation insulating film, 11,12,13…
… Interlayer insulation film, 14 …… Protective film.

Claims (1)

(57) [Claims] 1. A plurality of wiring layers insulated by an interlayer insulating film are sequentially laminated on a semiconductor substrate on which an element is formed, and the wiring layer of these wiring layers, which is the lowest layer closest to the semiconductor substrate, is formed. The wiring layer is formed over substantially the entire surface of the semiconductor substrate, the lowermost wiring layer is connected to one of a GND electrode and a power supply electrode, and at least one wiring layer above the lowermost wiring layer is used for signal wiring. A semiconductor integrated circuit having a layer structure.