JPH0612792B2 - Wiring structure of semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a wiring structure of a semiconductor device, and particularly to a high integration degree,
The present invention relates to a wiring structure of a semiconductor device characterized by high speed.

[Conventional technology]

Conventionally, in this type of multi-layer wiring structure, a signal line, a power supply line, and a ground line are formed in a mutually intricate shape in the same wiring layer or in adjacent layers, that is, so-called wiring is formed.

[Problems to be solved by the invention]

The above-mentioned conventional multi-layer wiring structure has the following drawbacks because the power supply and ground lines have wiring shapes.

1. When the pattern of the power supply and the ground line becomes complicated, the wiring length increases, so that the wiring inductance increases.

2. The capacitance between the power line and ground line is small. This, combined with the drawback of the above 1, increases the impedance of the power supply wiring and deteriorates the transient characteristics.

3. As a result of insufficient wiring cross-sectional area of the power supply or ground line, the current density in the wiring increases, and the reliability of the wiring deteriorates due to electromigration or the like.

[Means for solving problems]

To achieve the above object, a wiring structure of a semiconductor device according to the present invention is a wiring structure of a semiconductor device having a signal wiring layer and a power wiring layer, wherein the signal wiring layer is on a main surface of a semiconductor substrate. Is provided for inputting / outputting signals to / from the active element formed on the substrate, and the power supply wiring layer supplies power to the active element formed on the semiconductor substrate and is separated from the signal wiring layer. Is formed of a metal layer having substantially the same area as one main surface of the semiconductor substrate, is electrically insulated from the signal wiring layer, and covers the signal wiring layer to cover the signal wiring layer. It is formed by laminating.

Further, the power supply wiring amount is made up of a plurality of wiring amounts, and the plurality of wiring layers are fixed to different potentials, electrically insulated from each other, and stacked one above the other.

The upper and lower layers of the plurality of wiring layers are electrically insulated by an interlayer film or an oxide film.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a vertical sectional view of the first embodiment of the present invention.

An element isolation film 102 formed on a silicon substrate 101
Gate electrode 103 and diffusion layer 10 separated by
There is an active element consisting of 4 etc., and the upper part is the underlying interlayer film 1
It is covered with 05. This active element and the first conduit wiring 107
Are connected by the wiring 106 in the contact hole. The second layer wiring 110 and the first layer wiring 107 are insulated by the second interlayer insulating film 108 and electrically connected by the first through hole wiring 109. Up to this point, the structure is the same as the conventional structure.

In this embodiment, the inter-contact hole wiring 106, the first layer wiring 107, the first through-hole wiring 109, and the second wiring 110 to which the refractory metal 119 is attached are formed as independent layers separated from these signal wiring layers. It has a power supply wiring layer.

The power supply wiring layer includes a third layer wiring 113 and a fourth wiring 116. The third layer wiring 113 and the fourth wiring 116 are ground plane wirings having an area substantially equal to one main surface of the silicon substrate 102, are made of metal layers, and are electrically insulated from each other and are stacked one above the other. ing.

The third layer wiring 113 and the fourth layer wiring 116 of the power supply wiring layer are
Fixed to different potentials, the power supply wiring layer supplies power to the active elements formed on the silicon substrate 101. Signal wiring layer (wirings 106, 107, 1
09, 110) inputs and outputs signals to and from the active elements formed on the silicon substrate 101.

The arrangement relationship between the power supply wiring layer and the signal wiring will be described.
As shown in FIG. 1, the power supply wiring layer includes wirings 106 and 10
The signal wiring layer composed of 7, 109 and 110 is covered and laminated on the signal wiring layer so as to be electrically insulated from the signal wiring layer. Specifically, the refractory metal 119 of the second layer wiring 110 is covered with the third interlayer film 111, and the third layer wiring 113 is formed on the refractory metal 119 of the second layer wiring 110 to form a third layer.
The interlayer film 111 is electrically insulated and laminated. Further, a fourth interlayer film 114 is formed on the third layer wiring 113,
The layer wiring 116 is formed on the third layer wiring 113 by the fourth interlayer film 114.
It is electrically insulated and laminated. Also, the fourth layer wiring 1
16 is covered with a protective film 117.

Electrical connection from these wiring layers to the active element or the lower layer wiring is performed by the wirings 112 and 115 in the through holes.
Here, the electrical insulation between the third-layer wiring 113 and the through-hole wiring 115 is achieved by the metal oxide film 118.
The metal oxide film 118 is formed, for example, by the method shown in FIG.

In FIG. 2, the second-layer wiring 201 has a structure in which at least the upper surface thereof is covered with a refractory metal 202, gold or the like, and the third interlayer film 203 and the third-layer wiring 2 are formed on the upper surface.
04 (here, an Al film) and a fourth interlayer film 205 are formed (FIG. 2 (a)). Next, an etching mask 206 is formed, and dry etching or the like is used to form the second mask.
A through hole 207 between wirings is opened (FIG. 2 (b)).
After removing the etching mask 206, the hydrate 208 of Al is formed on the side wall of the third-layer wiring Al film 204 by immersing it in warm water of 80 ° C. for several minutes, and this is hydrated. And as an insulating film between the through holes 207 (FIG. 2 (c)).

FIG. 3 is a vertical sectional view of the second embodiment of the present invention.

In FIG. 3, the structure below the third interlayer insulating film 301 is
Since it is the same as the first embodiment, the details are omitted.

In this embodiment, the third layer wiring 302 constituting the power supply wiring layer
The fourth-layer wiring 304 and the fourth-layer wiring 304 are electrically insulated by the metal oxide film 303 and are stacked one above the other. Reference numeral 301 is a third interlayer film, and 305 is a protective film. According to the present embodiment, the metal oxide film 303 not only electrically insulates the upper and lower wirings 32 and 304 from each other, but also the through-hole wiring 30.
6 and the third layer wiring 302 are electrically insulated.

In this embodiment, the first method for forming the fourth interlayer insulating film 303 is the first.
This is different from the embodiment. This forming method is shown in FIG.

In FIG. 4, the third interlayer film 40 is formed on the second layer wiring 401.
Second, the third layer wiring 403 is deposited (FIG. 4 (a)), and the through-hole 2-4 between wirings 405 is opened using the etching mask 404. (Fig. 4 (b)). After removing the etching mask 404, several thousand Å gold-side oxide 406 of the wiring layer 403 is selectively formed on the surface of the third-layer wiring 403 by an anodic oxidation method or the like, and this is used as a fourth interlayer film. Yes (4th
(Figure (c)).

As the metal used for the power supply wiring layer, Al, Ta, or the like can be used. Particularly, when Ta is used, a high-current wiring having high electromaculation resistance can be realized.

〔The invention's effect〕

As described above, the present invention has the following effects by forming the power supply wiring in the shape of a ground plane and forming the layer independent of the signal line.

1. The electric resistance of the power supply and ground wire can be made extremely low.

2. By increasing the capacitance to ground of the power supply wiring, combined with the above effects, the power supply impedance is reduced,
Increase the operating speed of the device.

3. The cross-sectional area of the power supply and ground lines becomes extremely large, and the current rate in the wiring and heat generation can be reduced, resulting in improved reliability against electromigration and the like.

[Brief description of drawings]

FIG. 1 is a longitudinal sectional view showing a first embodiment of the wiring structure of the present invention, and FIGS. 2 (a) to (c) show the first embodiment, especially the second embodiment.
-4 is a process sectional view showing a method of forming a structure near a through hole between wirings, FIG. 3 is a vertical sectional view showing a structure of a second embodiment of the present invention, and FIGS. 4 (a) to 4 (c) are FIG. 6 is a process sectional view showing the method for forming a fourth interlayer film, in particular, for the second embodiment. 101 ... Silicon substrate, 102 ... Element separation film, 1
03 ... Gate electrode, 104 ... Diffusion layer, 105 ... Underlayer interlayer film, 106 ... Contact hole wiring, 107
...... First layer wiring, 108 ...... Second interlayer film, 109 ...... First through hole wiring, 110 ...... Second layer wiring, 111
...... Third interlayer film, 112 ・ ・ ・ Wiring in through hole, 11
3 ... Third layer wiring, 114 ... Fourth interlayer film, 115 ...
2-4 through-hole wiring between wirings, 116 ... fourth layer wiring, 117 ... protective film, 118 ... metal oxide film, 119
...... High melting point metal, 201 ...... Second layer wiring, 202 ...... High melting point metal, 203 ...... Third interlayer film, 204 ...... Third layer wiring, 205 ...... Fourth interlayer film, 206 ...... Etching mask , 207 ... Through hole between wirings 2-4, 208
...... Metal oxide film, 301 ・ ・ ・ Third interlayer film, 302 ・ ・ ・ Third layer wiring, 303 ・ ・ ・ Metal oxide film, 304 ・ ・ ・ 4th layer wiring, 305 ・ ・ ・ Protective film, 306 ・ ・ ・ 2-4 Through-hole wiring between layer wirings, 401 ... Second layer wiring, 402 ... Third interlayer film, 403 ... Third layer wiring, 404 ... Etching mask, 405 ... 2-4th layer wiring through hole,
406 ... Metal oxide film.

Claims (3)

[Claims] 1. A wiring structure of a semiconductor device having a signal wiring layer and a power wiring layer, wherein the signal wiring layer is provided on one main surface of a semiconductor substrate, and is provided on an active element formed on the substrate. The power supply wiring layer is for inputting / outputting signals, supplies power to the active elements formed on the semiconductor substrate, is an independent layer separated from the signal wiring layer, and is a part of the semiconductor substrate. It is characterized in that it is made of a metal layer having an area substantially equal to that of the main surface, is electrically insulated from the signal wiring layer, covers the signal wiring layer, and is laminated on the signal wiring layer. Wiring structure of semiconductor device. 2. The power supply wiring layer is composed of a plurality of wiring layers, and the plurality of wiring layers are fixed to different potentials, electrically insulated from each other, and stacked one above the other. A wiring structure for a semiconductor device according to claim 1, wherein: 3. The wiring structure of a semiconductor device according to claim 2, wherein the upper and lower layers of the plurality of wiring layers are electrically insulated by an interlayer film or an oxide film. .