JPS63221649A - Interconnection structure of semiconductor device - Google Patents

Abstract

PURPOSE:To lower electrical resistance of a power source and a grounding line and to lower a power impedance and to increase an operational speed of the element, by forming a power source interconnection on one main surface of a semiconductor substrate so as to be shaped into a ground plane and making the power source interconnection be independent of a signal line and so increasing a capacity of the power source interconnection to ground. CONSTITUTION:Active elements, which consist of gate electrodes 103 and a diffusion layer 104 and the like and are isolated by an element isolation film 102 formed on a silicon substrate 101, are connected with a first layer interconnection 107 through contact hole interconnection 106. A second layer interconnection 110 and the first layer interconnection 107 are insulated through a second layer insulating film 108 and electrically connected through first through hole interconnection 109. A third layer interconnection 113 and a fourth layer interconnection 116 are formed as ground plate interconnection on the almost whole surface of the silicon substrate 101. Electrical connections between these interconnection layers and the active element or the lower layer are performed by through hole interconnections 112 and 115 and the like. Electrical insulation between the third layer interconnection 113 and the through hole interconnection 115 can be realized by a metallic oxidizing film 118.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention relates to the wiring structure of semiconductor devices, and particularly to the wiring structure of semiconductor devices.
This invention relates to the wiring structure of a semiconductor device characterized by high speed.

[Conventional technology]

Conventionally, in this type of multilayer wiring structure, a signal line, a power supply line, and a ground line have been formed in the same wiring layer or in adjacent layers in an intertwined shape, that is, so-called wiring.

[Problem that the invention seeks to solve]

The conventional multilayer wiring structure described above has the following drawbacks because the power supply and ground lines are in the form of wiring.

1. When the pattern of the power supply and grounding wires becomes complicated, the wiring length increases, which increases the wiring inductance. 2. The capacitance between the power supply line and the grounding line is small. This, together with the above-mentioned drawback 1, causes the total impedance of the power supply wiring to increase and deteriorates the transient characteristics.

3. Wiring cross-sectional area of power supply or grounding wire is sufficient and 2"L
As a result, the current density within the wiring increases, and the reliability of the wiring deteriorates due to electromigration and the like.

[Means for solving problems]

The wiring structure of the semiconductor device of the present invention includes a t signal wiring layer provided on one main surface of a semiconductor substrate, a first interlayer insulating film of f′L order provided so as to cover the entire layer of this signal arrangement, and On the first J-layer film, one side of the semiconductor substrate is completely covered with a metal wiring layer which is provided over almost the entire surface and which supplies the entire fixed potential. The metal wiring layer supplying a fixed potential may be composed of a plurality of wiring layers fixed at different potentials, and the wiring layers may be separated by an oxide of the wiring layer.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a longitudinal sectional view of a first embodiment of the invention.

Interelement isolation film 102 formed on a silicon substrate 101
separated by tLe, gate electrode 103 and expansion M1
Active element container consisting of 04 etc., the upper part is the base, ・-
It is covered with a mesenterium 105. The second active element and the first/# wiring 107 are connected by a wiring 106 in the contact hole.・Also, the second layer wiring 110 and the first layer wiring 1
Is 07 between the 2nd NI? 3 Insulated by the edge film 108 N1 Electrically connected by the wiring 109 in the first through hole 1
ing.

The structure up to this point is the same as the conventional structure.

In this embodiment, the third) ri wiring [113 and the fourth layer wiring 1
A ground plane wiring 16 is provided over almost the entire surface of the silicon substrate 101. Electrical connections from these wiring layers to active elements or lower layer wiring are made using through-hole recording [1
Conducted at 12,115 fathoms.

Here, the third layer wiring 113 and the through-hole wiring 115
Electrical insulation from the metal oxide film 118 is provided by the metal oxide film 118. This metal oxide film 118 is formed, for example, by the method shown in FIG.

In FIG. 2, the second layer wiring 201 has at least its upper surface made of high melting point metal! 52026 or gold, etc., to form a magnetic structure, and on top of this, a third interlayer film 203, a third layer wiring 204 (herein referred to as an Aj film), and a fourth interlayer film 205t.
- form (Fig. 2(a)).

Next, an etching mask 206 is formed, and the through hole 20 between the second and fourth wirings is etched by means such as dry etching.
7 Fully open (Fig. 2(b)). Etching mask 20
6 is removed, and after t, 1 is soaked in warm water at, for example, 80° C. for several minutes, thereby forming an irrigant 208t of Aj on the side wall of the third layer wiring AI film 204, which is then connected to the third layer wiring 204,
Used as an insulating film between the through holes 207 (Fig. 2 (
C)).

FIG. 3 is a longitudinal sectional view of a second embodiment of the invention.

Ru.

In this embodiment, the method of forming the fourth interlayer insulation 11g303 is different from that in the first embodiment. This forming method is shown in FIG.

In FIG. 4, a third interlayer film 40 is disposed on a second layer wiring 401.
2. Depositing the third layer wiring 20403 (Figure 4(a))
Then, a through hole 405 between the second and fourth wirings is opened using an etching mask 404'Th (FIG. 4(bl)).

After removing the etching mask 404t, several thousand metal oxides 406'i of the wiring layer 403 are selectively formed on the surface of the third layer wiring 403 by anodic oxidation or the like, and this is applied to the fourth layer. A film is formed (Fig. 4(C)).

As the third wiring layer metal, l! , Ta, etc. can be used, and in particular, when Tat is used, it is possible to realize a large current wiring with high resistance to electromagnetic corrosion.

〔Effect of the invention〕

As explained above, the present invention provides the following first-order effects by forming the power distribution S in the form of a ground plane and forming a layer independent of the signal line.

1. The electrical resistance of the power supply and grounding wires can be extremely low.

By increasing the grounding capacity of the power supply wiring, combined with the above effects, the power supply impedance is reduced,
Increase the operating speed of the element.

3. Since the cross-sectional area of the power supply and grounding lines is extremely large, the IT current density within the wiring and the heat generation can be reduced, thereby improving reliability against electromigration and the like.

[Brief explanation of drawings]

FIG. 1 is a vertical cross-sectional view showing a first embodiment of the wiring structure of the present invention, and FIGS. FIG. 3 is a vertical cross-sectional view showing the structure of the M2 embodiment of the present invention, and FIGS. It is a process sectional view showing a method of forming a four-layer interlayer film. 101...Silicon substrate, 102...
Interelement isolation film, 103...Gate electrode, 104
...Diffusion layer, 105... Base interlayer film,
106... Wiring inside contact hole, 107.
...First layer wiring, 108...Second interlayer film %109...First through hole interconnection, 110
...Second layer wiring, 111...Third interlayer film, 112...Wiring in through hole, 113.
...Third layer wiring, "l L4... Fourth interlayer film, 115... S/L-hole wiring between 2nd and 4th wiring, 116...・4th layer wiring, 117...
...Protective film, 118...Gold halide oxide 1■, 1
19... High melting point metal, 201... Second
Layer wiring, 202... High melting point metal, 203...
...Third interlayer film, 204...Third layer wiring, 2
05...Fourth interlayer film, 206...Etching mask, 207...Through hole between m2-4N wiring, 208...Metal oxide film. 301...Third intermembrane, 302...
3rd layer wiring, 303...Gold metallization film, 304.
...4th layer wiring, 305...protective film, 3
06...2nd-4N! Through-hole arrangement between J wiring! , 401... Second interlayer m, 402...
...Third interlayer film, 403...31st arrangement) edge, 4
04... Etching mask, 405...
・Through hole between 2nd and 4th layer wiring, 406...
Metal oxide film. , ″・°, −・1.＼ Agent Patent attorney Uchihara f, ＼・11,.

Claims (2)

[Claims] (1) A signal wiring layer provided on one main surface of a semiconductor substrate, a first interlayer insulating film provided to cover the signal wiring layer, and a 1. A wiring structure for a semiconductor device, comprising a metal wiring layer for supplying a fixed potential, which is provided over almost the entire principal surface of a semiconductor substrate. (2) The wiring structure of a semiconductor device according to claim 1, wherein the metal wiring layers are a plurality of wiring layers each fixed at a different potential and stacked vertically on top of each other. (3) The wiring structure of a semiconductor device according to claim 2, wherein the plurality of wiring layers are separated by an oxide film of a lower wiring layer.