經濟部智慧財產局員工消費合作社印製 501238 A7 B7___ 五、發明說明（f ) 發明之領域 本發明揭示一種半導體裝置及其製造方法，尤其是一 種LSI閘陣列（gate array)之半導體裝置及其製造方法。 發明背景 第1A及1B圖表示習用閘陣列之半導體裝置的製造方 法步驟。如第1A圖所示P型井（wel 1)202及N型井203 形成在 P -型半導體基體（semiconductor substrate)201 上，而隔離氧化層（separation oxidized layer)204形成在 P 型井 202 及 N 型井 2 03 上。擴散層（diffusion iayer)2〇5 形成在隔離氧化層2 0 4之頂表面，其中隔離氧化層2 0 4 及擴散層20 5之頂表面在同一面層（lavei)。而且，閘極2〇6形 成在隔離氧化層204之頂表面上，因而形成電晶體。其 次，第一層間絕緣層2 0 7形成在擴散層2 0 5、閘極2 0 6及 隔離氧化層204之上。 其次，如第1 B圖所示，接點2 0 8被形成以便通過第一 層間絕緣層2 0 7而連通擴散層2 0 5或閘極2 0 6。然後，第 一 A1(鋁）層2 09形成在第一層間絕緣層207之頂表面上， 因而形成LSI。在第1B圖所示基體中，接點20 8使得在 第一A1層209及閘極206或擴散層2 0 5之間電氣連接。 接點2 0 8形成方法是以諸如在第一介層間層2 0 7之中來 形成通道（through hall)(下文稱接點道（contact liall))及 接點道充塡金屬來形成接點20 8。 除了上述結構之外’另一種以接點來連接絕緣層所分 離之導電層的方法發表在及汨本專利申請案公報第 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） ------------ I I ------訂·！丨 — 丨丨丨線 (請先閱讀背面之注意事項再填寫本頁) i 經濟部智慧財產局員工消費合作社印製 501238 A7 _____Β7 __ 五、發明說明（\) 6 1 - 1 66047號中。在本方法中，做爲配線層（^1^以1&>^) 之第一及第二多矽晶層（polycrystalline Si)形成在Si02 (二氧化矽）所形成絕緣層中之不同位置處。然後，由 A 1 (鋁）所形成且產生和上述多矽晶之側表面接觸的接 點’形成連接S i 0 2所形成絕緣層下側之摻雜擴散層。 在閘陣列之L S I中’預先準備具有第1 a圖所示結構所 加工過程的基體，以形成接點2 0 8所選擇電晶體、及在 介層間絕緣層2 0 7之頂部上所形成來連接接點2 〇 8之a 1 層。如此，形成如第1B圖所示之LSI。 近年來，因爲L SI配線結構變成多層化，其製造方法 之步驟數逐漸增加，且其製造所花費時間加長。另一方 面’製造LSI陣列所費時間的降低是大幅地需要。尤其， 在L SI陣列中’因爲必需預先準備所加工過程之基體來 適用於接點形成開始，所以具有影響製造方法期間的主 要因素是在接點形成開始之後。 而且，在上述日本專利申請案公報第61-166047號中所 發表半導體裝置中，沒有表示適用於半導體裝置閘陣列 之結構（structure)，而且沒有發表有關減少製造加工過程 期間之問題。 發明槪沭 因而，本發明之目的在提供一種半導體裝置之製造方 法’其減少在接點形成開始之後製造加工過程之步驟數。 本發明進一步之目的在提供一種半導體裝置，其中減 少在接點形成開始之後製造加工過程的步驟數。 -4- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） I I--IISIIII — — — — — — — ^> — 1! — — — ! ^ 1 (請先閱讀背面之注意事項再填寫本頁) 501238 A7 B7Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 501238 A7 B7___ V. Description of the Invention (f) Field of the Invention The present invention discloses a semiconductor device and a manufacturing method thereof, particularly a semiconductor device of an LSI gate array and its manufacturing method. BACKGROUND OF THE INVENTION Figures 1A and 1B show steps of a method for manufacturing a semiconductor device using a conventional gate array. As shown in FIG. 1A, a P-type well (wel 1) 202 and an N-type well 203 are formed on a P-type semiconductor substrate 201, and a separation oxidized layer 204 is formed on the P-type well 202 and N-type well 2 03 on. A diffusion layer 205 is formed on the top surface of the isolation oxide layer 204. The top surface of the isolation oxide layer 204 and the diffusion layer 205 are on the same surface layer (lavei). Further, the gate electrode 206 is formed on the top surface of the isolation oxide layer 204, thereby forming a transistor. Next, a first interlayer insulating layer 207 is formed on the diffusion layer 205, the gate electrode 206, and the isolation oxide layer 204. Next, as shown in FIG. 1B, a contact 208 is formed so as to communicate with the diffusion layer 205 or the gate 206 through the first interlayer insulating layer 207. Then, a first A1 (aluminum) layer 209 is formed on the top surface of the first interlayer insulating layer 207, thereby forming an LSI. In the substrate shown in Fig. 1B, the contact 20 8 makes an electrical connection between the first A1 layer 209 and the gate electrode 206 or the diffusion layer 205. The contact 208 is formed by, for example, forming a through hall (hereinafter referred to as a contact liall) in the first interlayer interlayer 207 and filling the contact with metal to form the contact. 20 8. In addition to the above structure, 'Another method of connecting the conductive layer separated by an insulating layer with contacts is published in the first paper standard of this patent application bulletin and applies to the Chinese National Standard (CNS) A4 specification (210 X 297 public love ) ------------ II ------ Order!丨 — 丨 丨 丨 Line (Please read the notes on the back before filling out this page) i Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 501238 A7 _____ Β7 __ V. Description of Invention (\) 6 1-1 66047. In this method, the first and second polycrystalline Si layers as the wiring layer (^ 1 ^ 1 & > ^) are formed at different positions in the insulating layer formed by Si02 (silicon dioxide). Office. Then, a doped diffusion layer formed on the lower side of the insulating layer formed by connecting S i 0 2 is formed from A 1 (aluminum) and a contact is formed to contact the side surface of the polysilicon. In the LSI of the gate array, 'a substrate having the processing process of the structure shown in Fig. 1a is prepared in advance to form a transistor selected by the contact 2 08 and formed on top of the interlayer insulating layer 2 07. Connect the contact 1 to the a1 layer. Thus, an LSI as shown in FIG. 1B is formed. In recent years, as the LSI wiring structure has become multilayered, the number of steps in its manufacturing method has gradually increased, and the time it takes to manufacture it has increased. On the other hand, a reduction in the time required to manufacture an LSI array is greatly required. In particular, in the L SI array, since the substrate to be processed must be prepared in advance to be suitable for the start of contact formation, the main factor having an influence during the manufacturing method is after the start of contact formation. Furthermore, in the semiconductor device disclosed in the above-mentioned Japanese Patent Application Publication No. 61-166047, a structure suitable for a gate array of a semiconductor device is not indicated, and no problem has been disclosed regarding reduction of the manufacturing process. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a method of manufacturing a semiconductor device 'which reduces the number of steps in a manufacturing process after a contact formation is started. It is a further object of the present invention to provide a semiconductor device in which the number of steps of a manufacturing process after the start of contact formation is reduced. -4- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) I I--IISIIII — — — — — — — ^ > — 1! — — —! ^ 1 (Please read first Note on the back, please fill out this page) 501238 A7 B7
經濟部智慧財產局員工消費合作社印製 五、發明說明（ο 根據本發明之第一特徵，用於製造半導體裝置之方法 包含下列步驟： 根據預定圖型（predetermined pattern)，在半導體其# 上形成多種電路元件（element); 以第一介層間絕緣層來覆蓋多種電路元件； 根據預定圖型，在第一介層間絕緣層上形成由多數導 體（conductor)所構成之配線層（wiring layer); 以第二介層間絕緣層來覆蓋配線層；及 形成接點’其通過至少第一及第二介層間絕緣層中之 一層來連接電路元件及配線層且根據預定電路結構排除 在第二介層間絕緣層頂表面上之配線層的電氣導通。 根據上述方法，接點孔（contact hole)形成在配置多數 電路兀件之基體中’以便定位接近配線層及多數電路元 件。電路接點可簡單地以接點孔充塡導電材料來形成。 因而，電路元件可簡單地經由接點來連接配線層，減少 在接點形成開始之後製造加工過程的步驟數，而且可縮 短LSI閘陣列之製造加工過程期間。 根據本發明之第二特徵，半導體裝置包含： 多數電路元件，根據預定圖型來形成在半導體基體上· 第一絕緣層，用於覆蓋多數電路元件； 配線層’由根據預定圖型而形成在第一介層間絕緣層 上之多數導體所構成； 第二介層間絕緣層，用於覆蓋配線層；及 接點，通過至少第一及第二介層間絕緣層中之一層來 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -------------.1丨·! _ —訂丨丨丨·線_ (請先閱讀背面之注意事項再填寫本頁) 501238 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（斗） 連接配線層及電路元件，且根據預定電路結構來去除第 根據上述結構，多數電路兀件及第一介層間絕緣層开多. 成在所加工過程之基體上，多數導體所構成配線層根據 預定圖型來形成在第一介層間絕緣層之頂表面上。接點 形成在靠近配線層之預定位置處以便可獲得所期望的電 路。因而，電路元件可以簡單地經接點來連接配線層， 在接點形成開始後之製造方法的步驟數減少，而且可縮 短LSI閘陣列之製造加工過程期間。 附圖之簡單說明 本發明以附圖來更詳細說明，其中： 第1A及1B圖表示用於製造習用半導體裝置之方法的 橫剖面圖示； 第2圖表示用於製造根據本發明第一較佳實施例半導 體裝置之方法的平面圖示； 弟3圖表不沿剖線A - A所取半導體裝置之橫剖面圖示 第4圖表示在第2圖所示後續製造方法步驟中半導體 裝置的平面圖示； 第5圖表示沿剖線B -B所取圖示所示半導體裝置之橫 剖面圖示；及 第6圖是根據第二較佳實施例半導體裝置之橫剖面圖 示。 較佳實施例之說明 本發明之較佳實施例在下文中將參照附圖來詳細說 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------------------訂---------^ IAWI (請先閱讀背面之注咅心事項再填寫本頁) J^1238 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（r ) 明。 第2圖表示根據本發明之方法所製造的半導體裝置’ 第3圖表示沿剖線A-A所取第2圖所示半導體裝置之橫 剖面圖示。第4圖表不在第2圖所不製ia方法之步驟後 的半導體裝置，而第5圖表示沿剖線B -B所取第4圖所 示半導體裝置的橫剖面圖示。 如第3圖所示，P型井1〇2及N型井1〇3形成在P-型 基體101上，且隔離氧化層104形成在P型井102及N 型井103上。擴散層105形成在隔離氧化層1〇4周圍’ 而隔離氧化層104的頂表面及擴散層105位在同一層 面。而且，閘極1 〇6形成在隔離氧化層1 〇4之頂表面上。 如上所示，電晶體是經由隔離氧化層1 〇4、P型井1 02、 N型井1 〇 3、擴散層1 0 5及閘極1 0 6來形成。 而且，具有均勻厚度（例如約8 0 0 0】（埃））之第一介層 間絕緣層1 〇 7形成在擴散層1 0 5、閘極1 0 6及隔離氧化層 104上。然後，第一 A1層108圖型化在第一介層間絕緣 層1 〇 7之頂表面上的預定部份處。如第2圖所示，部份 第一 A1層配置成平行相對閘極106之水平方向，.其餘部 份配置成平行垂直方向，而且其橫向地相對細分。第3 圖表示 A1 層 108a、108b、108c、108d、108e、l〇8f、108g、 108 h、108i之橫剖面圖示。具有約8000】厚度之第二介 層間絕緣層109形成在第一 A1層108上。在第3圖所示 步驟中，電晶體尙未連接第一 A1層108。 其次，參照第4及5圖來說明在電晶體及第一 a 1層之 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 0 ^1 ^1 ϋ I ϋ 一φ, » .1 I n ϋ I ϋ ϋ ϋ ϋ ϋ ϋ n I .^1 I I I I H ϋ ϋ ϋ ^1 ϋ , (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 501238 κι ___Β7____ 五、發明說明U ) 間以接點1 1 〇的電氣連接。如第5圖所示，第一 A 1層1 〇 8 c 插置在接點1 1 〇a、1 1 Ob之間，該接點以蝕刻技術來通過 第一介層間絕緣層107及第二介層間絕緣層1〇9。而且， 接點110a、11 Ob之底表面接觸擴散層105。接點110a、 1 1 〇b之上部在第二介層間絕緣層1 09結合來形成接點 1 1 2。而且，所形成通過第一介層間絕緣層1 07及第二介 層間絕緣層1 〇 9之接點1 0 7形成條件在使得接點i ! 〇 c接 觸第一 A1層1 0 8 d之側表面，而且其底表面接觸閘極 l〇6b。而且’第一 A1層108f插置在接點ll〇d及ll〇e 之間，其通過第一介層間絕緣層1 0 7及第二介層間絕緣 層109。接點1 10d之底表面接觸閘極l〇6b，而接點1 i〇e 接觸擴散層1 〇 5。各接點1 1 〇是以導電材料之諸如W(鎢） 來以CVD方法來成長而形成，而且做爲電氣導通路徑。 接點1 1 〇配置用第一 A 1層1 〇 8來連接擴散層1 0 5或閘極。 如第5圖所示，接點1 1 〇 a、1 1 0 b被形成使得接觸第一 A1層108之頂表面及側壁，而且電氣連接第一 A1層 108b、108c、108d 及擴散層 1〇5。第一^ A1 層 108c 及 108f 初始相互隔離，而經由在隔離氧化層1 04及接點.1 1 0c、 1 l〇d上所形成之閘極106b來相互電氣連接。第一 A1層 108c、108f等作用爲電氣導通路徑之電極。 如上所述，根據上述實施例，預先所配置電晶體及根 據預定圖型所細分之第一 A1層間的電氣連接，可以形成 接點孔且再用充塡導電材料來塡它們來形成接點而建 立。而且，可圖型化在第二介層間絕緣層1 09之頂表面 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公f ) (請先閱讀背面之注意事項再填寫本頁) 11! 11 線丨攀- wi238Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the Invention (ο According to the first feature of the present invention, a method for manufacturing a semiconductor device includes the following steps: According to a predetermined pattern, a semiconductor device is formed on the semiconductor device # A variety of circuit elements (elements); a first interlayer insulation layer to cover a variety of circuit elements; according to a predetermined pattern, a wiring layer (wiring layer) composed of a plurality of conductors is formed on the first interlayer insulation layer; Covering the wiring layer with a second interlayer insulating layer; and forming a contact, which connects the circuit element and the wiring layer through at least one of the first and second interlayer insulating layers and is excluded from the second interlayer according to a predetermined circuit structure Electrical continuity of the wiring layer on the top surface of the insulating layer. According to the method described above, contact holes are formed in a substrate configured with most circuit elements so as to be positioned close to the wiring layer and most circuit elements. Circuit contacts can be simply It is formed by filling a contact hole with a conductive material. Therefore, a circuit element can be simply connected to a wiring layer through a contact, The number of steps in the manufacturing process after the start of contact formation is reduced, and the manufacturing process of the LSI gate array can be shortened. According to a second feature of the present invention, the semiconductor device includes: a plurality of circuit elements, which are formed on the semiconductor according to a predetermined pattern. On the substrate · The first insulating layer is used to cover most circuit elements; the wiring layer is composed of most conductors formed on the first interlayer insulating layer according to a predetermined pattern; the second interlayer insulating layer is used to cover the wiring Layers; and contacts, through at least one of the first and second interlayer insulation layers, this paper applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ---------- ---. 1 丨 ·! _ —Order 丨 丨 丨 · Line_ (Please read the notes on the back before filling out this page) 501238 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Invention Description (Doo) Connect the wiring layer and the circuit elements, and remove the first circuit structure according to the predetermined circuit structure. According to the above structure, most circuit elements and the first interlayer insulation layer are opened more. Formed on the substrate of the processing process, most conductors are constructed The wiring forming layer is formed on the top surface of the first interlayer insulating layer according to a predetermined pattern. The contact is formed at a predetermined position near the wiring layer so that a desired circuit can be obtained. Therefore, the circuit element can simply pass through the contact To connect the wiring layer, the number of steps in the manufacturing method after the contact formation starts is reduced, and the manufacturing process of the LSI gate array can be shortened. Brief Description of the Drawings The present invention will be described in more detail with the accompanying drawings, in which: And FIG. 1B shows a cross-sectional view of a method for manufacturing a conventional semiconductor device; FIG. 2 shows a plan view of a method for manufacturing a semiconductor device according to a first preferred embodiment of the present invention; A cross-sectional view of a semiconductor device taken from A to A. FIG. 4 shows a plan view of the semiconductor device in a subsequent manufacturing method step shown in FIG. 2; FIG. 5 shows a view taken along the section line B-B. A cross-sectional view of a semiconductor device; and FIG. 6 is a cross-sectional view of a semiconductor device according to a second preferred embodiment. Description of the preferred embodiment The preferred embodiment of the present invention will be described in detail below with reference to the drawings in accordance with the Chinese National Standard (CNS) A4 specification (210 X 297 mm) --------- ----------- Order --------- ^ IAWI (Please read the note on the back before filling out this page) J ^ 1238 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs System A7 B7 V. Description of the invention (r). Fig. 2 shows a semiconductor device manufactured according to the method of the present invention '. Fig. 3 shows a cross-sectional view of the semiconductor device shown in Fig. 2 taken along section line A-A. Figure 4 is not a semiconductor device after the steps of the ia method shown in Figure 2, and Figure 5 is a cross-sectional view of the semiconductor device shown in Figure 4 taken along section line B-B. As shown in FIG. 3, the P-type well 102 and the N-type well 103 are formed on the P-type substrate 101, and the isolation oxide layer 104 is formed on the P-type well 102 and the N-type well 103. The diffusion layer 105 is formed around the isolation oxide layer 104, and the top surface of the isolation oxide layer 104 and the diffusion layer 105 are located on the same plane. Further, the gate electrode 106 is formed on the top surface of the isolation oxide layer 104. As shown above, the transistor is formed through the isolation oxide layer 104, the P-type well 102, the N-type well 103, the diffusion layer 105, and the gate 106. Further, a first interlayer insulating layer 107 having a uniform thickness (for example, about 8000) (Angstroms) is formed on the diffusion layer 105, the gate electrode 106, and the isolation oxide layer 104. Then, the first A1 layer 108 is patterned at a predetermined portion on the top surface of the first interlayer insulating layer 107. As shown in Fig. 2, part of the first A1 layer is arranged parallel to the horizontal direction with respect to the gate electrode 106, and the other part is arranged parallel to the vertical direction, and it is relatively subdivided laterally. Fig. 3 shows cross-sectional views of the A1 layers 108a, 108b, 108c, 108d, 108e, 108f, 108g, 108h, 108i. A second interlayer insulating layer 109 having a thickness of about 8000] is formed on the first A1 layer 108. In the step shown in FIG. 3, the transistor 尙 is not connected to the first A1 layer 108. Next, with reference to Figures 4 and 5, it will be explained that the size of this paper on the transistor and the first a 1 layer applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 0 ^ 1 ^ 1 ϋ I ϋ 1 φ, ».1 I n ϋ I ϋ ϋ ϋ ϋ ϋ ϋ n I. ^ 1 IIIIH ϋ ϋ ϋ ^ 1 ϋ, (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 501238 κι ___ Β7 ____ 5. Description of the invention U) Electrical connection between contacts 1 1 0. As shown in FIG. 5, the first A 1 layer 1 0 8 c is interposed between the contacts 1 1 0a and 1 1 Ob, and the contacts pass through the first interlayer insulating layer 107 and the second via an etching technique. Interlayer insulation layer 109. The bottom surfaces of the contacts 110 a and 11 Ob are in contact with the diffusion layer 105. The upper portions of the contacts 110a and 110b are combined with the second interlayer insulating layer 1009 to form the contacts 1 12. In addition, the formed contact through the first interlayer insulating layer 107 and the second interlayer insulating layer 10 is formed under conditions such that the contact i! 〇 contacts the first A1 layer 1 0 8 d. Surface, and its bottom surface contacts the gate 106b. Furthermore, the 'first A1 layer 108f is interposed between the contacts 110d and 110e, and passes through the first interlayer insulating layer 107 and the second interlayer insulating layer 109. The bottom surface of the contact 1 10d contacts the gate 106b, and the contact 1ioe contacts the diffusion layer 105. Each contact 1 10 is formed by using a conductive material such as W (tungsten) to grow by a CVD method, and serves as an electrical conduction path. The contact 1 10 is configured to use the first A 1 layer 108 to connect the diffusion layer 105 or the gate. As shown in FIG. 5, the contacts 1 10a, 1 10b are formed so as to contact the top surface and the side wall of the first A1 layer 108, and the first A1 layers 108b, 108c, 108d and the diffusion layer 1 are electrically connected. 5. The first ^ A1 layers 108c and 108f are initially isolated from each other, and are electrically connected to each other through the gate electrodes 106b formed on the isolation oxide layer 104 and the contacts .1 10c and 110d. The first A1 layers 108c, 108f and the like function as electrodes for an electrical conduction path. As described above, according to the above embodiment, the electrical connection between the transistor and the first A1 layer subdivided according to a predetermined pattern can be formed into contact holes and then filled with conductive material to form them. set up. In addition, it can be patterned on the top surface of the second interlayer insulating layer 1 09. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 male f) (Please read the precautions on the back before filling this page) 11! 11 Line 丨 Climbing-wi238
i、發明說明（V) 上的第二A 1層，雖然在附圖中沒有圖示。 其次，說明本發明第二較佳實施例。 第6圖表示本發明之第二較佳實施例。自第5及6圖 以相同參考號碼來表示具有相同功能之結.構元件，而省 略其詳細說明。而且，由於P型井102、N型井103、隔 離氧化層1 〇 4、擴散層1 0 5、閘極1 〇 6、第一介層間絕緣 層107、第一 A1層108及第二介層間絕緣層109形成在 P型基體101上之方法和第2及3圖所示相同，省略其詳 細說明。 具有厚度約8 0 0 0】之第一介層間絕緣層1 〇 7形成在閘 極106上，而第一 A1層108a至l〇8i圖型化在第一介層 間絕緣層1 0 7之頂表面上的預定部份。在第6圖中，第 一 A1層10 8j形成鄰接第一 A1層l〇8a。具有厚度約8000】 之第二介層間絕緣層形成在第一 A1層1 0 8上。上述方法 和第一較佳實施例相同。 其次’第二層113a、113b圖型化在第二A1介層間絕緣 層109之頂表面上。第二A1層l〇3a、l〇3b分別相對聞 極106來配置成平行於水平及垂直方向，而且如同第一 A1層1 0 8其相對橫向細分。其次，第三介層間絕緣層丨i 4 形成在第二A 1層1 1 3 a、1 1 3 b上。此時，尙未實施到電晶 體、第一 A1層l〇8a至10 8j及第二A1層113a、113b之 電氣連接。 其次，接點 110a、110b' 110c、110d、ll〇e 形成如同 第5圖所示結構來通過第一介層間絕緣層丨〇7、第二介層 冬 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製i. The second A1 layer on the description of the invention (V), although not shown in the drawings. Next, a second preferred embodiment of the present invention will be described. Fig. 6 shows a second preferred embodiment of the present invention. From Figs. 5 and 6, the same reference numerals are used to indicate structural elements having the same functions, and detailed descriptions are omitted. Moreover, since the P-type well 102, the N-type well 103, the isolation oxide layer 104, the diffusion layer 105, the gate electrode 106, the first interlayer insulating layer 107, the first A1 layer 108, and the second interlayer The method for forming the insulating layer 109 on the P-type substrate 101 is the same as that shown in FIGS. 2 and 3, and detailed descriptions thereof are omitted. A first interlayer insulating layer 107 having a thickness of about 8 0 0 is formed on the gate electrode 106, and the first A1 layers 108a to 108i are patterned on top of the first interlayer insulating layer 107. A predetermined portion on the surface. In Fig. 6, the first A1 layer 108j is formed adjacent to the first A1 layer 108a. A second interlayer insulating layer having a thickness of about 8000] is formed on the first A1 layer 108. The above method is the same as the first preferred embodiment. Next, the second layers 113a, 113b are patterned on the top surface of the second A1 interlayer insulating layer 109. The second A1 layer 103a and 103b are respectively arranged parallel to the horizontal and vertical directions with respect to the electrode 106, and are relatively laterally subdivided like the first A1 layer 108. Secondly, a third interlayer insulating layer i 4 is formed on the second A 1 layer 1 1 3 a, 1 1 3 b. At this time, thorium is not electrically connected to the electric crystal, the first A1 layers 108a to 108j, and the second A1 layers 113a and 113b. Secondly, the contacts 110a, 110b ', 110c, 110d, and 110e form a structure as shown in Fig. 5 to pass the first interlayer insulating layer. 〇07, the second interlayer winter paper standards are applicable to Chinese National Standards (CNS) A4 size (210 X 297 mm) (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs
1 ϋ ϋ ϋ ϋ ϋ ϋ 一I ϋ ^1 ι ϋ I ϋ ϋ I ϋ ϋ ϋ n ϋ ϋ I n ϋ ϋ — ϋ H ϋ ϋ I ϋ I ϋ ϋ I 501238 A7 B7 五、發明說明（Γ) 間絕緣層1 0 9及第三介層間絕緣層1丨4。而且，接點n 〇 f、 1 1 〇g形成使得通過第二介層間絕緣層1 09及第三介層間 絕緣層1 1 4。接點1 1 0 f、1 1 〇 g接觸第二A I層i丨3 a、1丨3 b 之側表面。而且’因爲接點1 1 〇、1 1 2是由導電材料所構 成，電晶體、第一 A1層l〇8b至108d、l〇8f、l〇8j及第 二A1層113a、113b電氣連接接點no、112。在上述結 構中，第二A1層113a、113b分別以接點ii〇f、i10g來 連接第一 A1層108j。第一 A1層l〇8b至l〇8d、擴散層 105及第二A1層113b以接點ii〇a、n〇b(ii2)來相互連 接。而且，第一 A1層108f、閘極l〇6b及擴散層1〇5經 接點1 10d、1 10e來相互連接。 如上文所述，根據第二較佳實施例，前所配置之電晶 體及配置在介層間絕緣層使得平行相對閘極之水平及垂 直方向且其橫向地細分的第一及第二A 1層，以形成通過 介層間絕緣層之接點孔且以導電材料來充塡接點孔來互 相電氣連接。雖然在第6圖之實施例中形成兩a 1層，但 是本發明可應用到具有三層或更多A1層。 雖然在上述實施例中電晶體配置在半導體基體上，但 是本發明之應用領域從未限制在此情形，而且本發明可 應用到以其他電路元件來替代電晶體之情形。其他電路 元件可包括半導體邏輯電路，諸如反及閘（N A N D g a t e )或 被動電路元件之諸如電阻器。構成配線層之多數導體的 材料也未限制在A1，其他金屬材料之諸如Cu (銅）或半導 體材料之諸如多矽晶也可採用。 -10- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注音？事項再填寫本頁) ·11!11 經濟部智慧財產局員工消費合作社印製 501238 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（9 ) 如上文所述，根據本發明之半導體裝置及其製造方 法，電晶體及A 1配線層間之電氣導通實施僅先配置電晶 體及A1層在所加工基體上、使在介層間絕緣層上之預定 位置處形成接點孔及以導電材料來充塡接點孔。因而， 如果上述方法應用到L S I閘極陣列，則在結構元件間之 電氣連接過程簡化，且可縮短在L SI閘極陣列之製造期 間。 雖然本發明已以特定實施例詳細說明來完整且淸楚公 布說明，但是申請專利範圍不因此受限在此，而是銓釋 擅於本發明者所實施全部修改例及替換構造仍在本文所 發表基本精神及範圍內。 符號說明 101…P型基板 102". P型井 1 03…N型井 1 04…隔離氧化層 105…擴散層 1 0 6…闊極 107…第一介層間絕緣層 108，108 〜108i···第一 A1層 109…第二介層間絕緣層 0，1 1 0 a〜1 1 〇 g…接點 1 14…第三介層間絕緣層 202…P型井 -1 1 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ϋ n ϋ ϋ I ϋ .a— n ϋ n I n ϋ n ϋ a^i 一trjI ϋ ϋ aiB ϋ i ai_— I ϋ (請先閱讀背面之注意事項再填寫本頁) 501238 A7 _B7 五、發明說明（W) 203…Ν型井 2 0 4…隔離氧化層 2 〇 5…擴散層 2 0 6…闊極 2 0 7…介層間絕緣層 208…接點 209…錦層 (請先閱讀背面之注意事項再填寫本頁) -------訂---------丨· 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）1 ϋ ϋ ϋ ϋ ϋ I I I ϋ ^ 1 ι ϋ I ϋ ϋ I ϋ ϋ ϋ n ϋ ϋ I n ϋ ϋ — ϋ H ϋ ϋ I ϋ I ϋ ϋ I 501238 A7 B7 V. Description of the invention (Γ) The insulating layer 109 and the third interlayer insulating layer 1 丨 4. Further, the contacts n 0f and 110 g are formed so as to pass through the second interlayer insulating layer 10 09 and the third interlayer insulating layer 1 14. The contacts 1 10 f, 1 10 g contact the side surfaces of the second A I layer i 丨 3a, 1 丨 3b. And 'because the contacts 1 10 and 1 12 are made of a conductive material, the transistor, the first A1 layer 108b to 108d, 108f, 108j, and the second A1 layer 113a and 113b are electrically connected. Point no, 112. In the above-mentioned structure, the second A1 layer 113a and 113b are connected to the first A1 layer 108j with the contacts iif and i10g, respectively. The first A1 layers 108b to 108d, the diffusion layer 105, and the second A1 layer 113b are interconnected by contacts iia, nob (ii2). The first A1 layer 108f, the gate 106b, and the diffusion layer 105 are connected to each other via the contacts 110d and 110e. As mentioned above, according to the second preferred embodiment, the transistor and the first and second A1 layers which are arranged in the interlayer and the insulating layer disposed between the interlayers so as to be parallel to the horizontal and vertical directions of the gate and are laterally subdivided. To form a contact hole through the interlayer insulating layer and fill the contact hole with a conductive material to electrically connect to each other. Although two a1 layers are formed in the embodiment of Fig. 6, the present invention can be applied to three or more A1 layers. Although the transistor is disposed on the semiconductor substrate in the above embodiment, the application field of the present invention is never limited to this case, and the present invention can be applied to a case where the transistor is replaced by other circuit elements. Other circuit elements may include semiconductor logic circuits, such as resistors such as inverse gates (N A N D g a t e) or passive circuit elements. The material of most conductors constituting the wiring layer is also not limited to A1, and other metal materials such as Cu (copper) or semiconductor materials such as polysilicon can also be used. -10- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the note on the back? Matters before filling out this page) · 11! 11 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 501238 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (9) As mentioned above, according to the semiconductor device and its manufacturing method of the present invention, the electrical conduction between the transistor and the A1 wiring layer is only configured first The transistor and the A1 layer form a contact hole on the processed substrate at a predetermined position on the interlayer insulating layer and fill the contact hole with a conductive material. Therefore, if the above method is applied to the L S I gate array, the electrical connection process between the structural elements is simplified, and the manufacturing period of the L SI gate array can be shortened. Although the present invention has been described in detail with specific embodiments, it is complete and well-published. However, the scope of patent application is not limited here, but it is explained that all modifications and replacement structures implemented by the inventors are still good. Post basic spirit and scope. DESCRIPTION OF SYMBOLS 101 ... P-type substrate 102 ". P-type well 1 03 ... N-type well 1 04 ... Isolation oxide layer 105 ... Diffusion layer 1 0 6 ... Wide pole 107 ... First interlayer insulating layer 108, 108 to 108i ... · The first A1 layer 109 ... the second interlayer insulating layer 0, 1 1 0 a ~ 1 1 〇g ... the contact 1 14 ... the third interlayer insulating layer 202 ... the P-type well-1 1-This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) ϋ n ϋ ϋ I ϋ .a— n ϋ n I n ϋ n ϋ a ^ i a trjI ϋ ϋ aiB ϋ i ai_— I ϋ (Please read the back first Please pay attention to this page and fill in this page again) 501238 A7 _B7 V. Description of the invention (W) 203 ... N-well 2 0 4 ... Isolated oxide layer 2 0 5 ... Diffusion layer 2 0 6 ... Wide pole 2 0 7 ... Interlayer insulating layer 208… Contact 209… Golden layer (please read the notes on the back before filling this page) ------- Order --------- 丨 · Printed by the Employees' Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)