KR100587662B1 - Capacitor of semicon ductor device and method for fabricating the same - Google Patents

Abstract

Disclosed are a capacitor of a semiconductor device and a method of manufacturing the same, which can reduce the area occupied by a capacitor within a limited cell area without reducing capacitance, thereby enabling high integration of a bipolar device or a bi CMOS device. In order to achieve this, in the present invention, an emitter and a first conductive film pattern form a first capacitor on a semiconductor substrate with a first dielectric film interposed therebetween, and the first conductive film pattern and the second conductive film pattern intersect the second dielectric film. The second capacitor and the second conductive film pattern and the third conductive film pattern to form a third capacitor with a third dielectric film therebetween, the device configuration is made, the emitter and the second conductive film pattern is electrically connected In addition, a capacitor having a stacked structure is provided in which the first conductive layer pattern and the third conductive layer pattern are electrically connected to each other so that the first to third capacitors are connected in parallel.

Description

Capacitor of semi-conductor device and method for manufacturing same {Capacitor of semicon ductor device and method for fabricating the same}

1 is a cross-sectional view showing a capacitor structure of a conventional bipolar device;

2 is an equivalent circuit diagram of the capacitor shown in FIG. 1;

3 is a cross-sectional view showing a capacitor structure of a bipolar device according to the present invention;

4 is an equivalent circuit diagram of the capacitor shown in FIG.

5A through 5F are process flowcharts illustrating the capacitor manufacturing method of FIG. 3.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to reduce the area occupied by a capacitor on a substrate without reducing capacitance, thereby improving the degree of integration of a bipolar device or a bipolar CMOS device. The present invention relates to a capacitor of a semiconductor device and a method of manufacturing the same.

In a bipolar device or a bi CMOS device, a structure in which a metal film (or polysilicon film) and silicon (for example, an emitter) are connected with an insulating film therebetween or a polysilicon film and a polysilicon film are connected with an insulating film interposed therebetween Capacitor design is being made to have.

FIG. 1 is a cross-sectional view illustrating a capacitor structure of a bipolar device that has been conventionally used as an example.

According to the cross-sectional view of FIG. 1, in the conventional bipolar capacitor, an emitter 12 to be used as a lower electrode is formed in the semiconductor substrate 10, and an insulating film 14 is formed on the emitter 12. A wide contact hole is formed in the insulating film 14 to penetrate the insulating film 14 so that the surface of the emitter 12 is exposed to a predetermined portion, and a nitride film is formed in the predetermined part on the insulating film 14 including the contact hole. It can be seen that the dielectric film 16 is formed, and the conductive film pattern 18 made of a metal film or a polysilicon film to be used as an upper electrode is formed on the dielectric film 16. In FIG. 1, reference numeral 20 denotes a wiring line.

Therefore, as shown in the equivalent circuit diagram of FIG. 2, the capacitor having the above-described structure has an element structure such that a capacitance corresponding to C is secured.

However, when the capacitor is manufactured to have the above-mentioned structure, the following problem occurs in terms of high integration of the semiconductor device.

As the degree of integration of semiconductor devices has increased, the size of various unit devices constituting a semiconductor has been continuously reduced. However, in the case of capacitors, it is difficult to reduce the size due to various process constraints. It is in a state.

This can be attributed to the following reasons as can be seen in Equation (1) below.

C = (ε ₀ · ε) · (A / d) --------- (1)

Where C is the capacitance of the capacitor, ε ₀ is the dielectric constant of the vacuum, ε is the dielectric constant of the dielectric film, A is the area of the capacitor, and d is the thickness of the dielectric film.

In general, in order to reduce the area A occupied by the capacitor on the substrate and to maintain a constant C value, the thickness of the dielectric film 16 should be thinner than before, or a dielectric film having a large dielectric constant should be used.

Among these, the first method has a disadvantage in that it is difficult to apply to large-capacity memory devices because the reliability of the thin film is degraded by Fowler-Nordheim current when the thickness of the dielectric film is reduced to 100 Å or less. When using the dielectric film 16 made of a ferroelectric material such as PZT (Pb (Zr, Ti) O ₃ ) or BST (BaSrTi), it is difficult to directly deposit the film on the polysilicon bottom electrode. There is a limit to the application.

Therefore, it is difficult to reduce the area occupied by the capacitor within the limited unit cell area, and as a result, the integration of the semiconductor device may be limited. The same problem occurs in the manufacturing of bi-CMOS devices in addition to the bipolar devices, and therefore, there is an urgent need for improvement.

Accordingly, an object of the present invention is to take a capacitor in a stacked structure when manufacturing a bipolar device or a bi CMOS device, and by designing a device so that each of these capacitors are connected in parallel, the capacitor occupies the capacitor without reducing the capacitance within a limited cell area. The present invention provides a capacitor of a semiconductor device capable of reducing the area and thus improving integration.

Another object of the present invention is to provide a manufacturing method capable of effectively manufacturing the capacitor of the above structure.

In order to achieve the above object, the present invention provides a semiconductor substrate comprising an emitter; A first insulating film formed on the entire surface of the substrate; A wide contact hole formed through the first insulating film so that the surface of the emitter is partially exposed; A first dielectric layer formed on the first insulating layer including the wide contact hole; A first conductive film pattern formed on the first dielectric film in the vicinity thereof including the wide contact hole; A second insulating film formed on the entire surface of the resultant material; A first wide via hole formed through the second insulating layer so that the first conductive layer pattern is exposed on the wide contact hole; A second dielectric film formed on the second insulating film including the first wide via hole; A second conductive film pattern formed on the second dielectric film in the vicinity of the first wide via hole and electrically connected to the emitter; A third insulating film formed on the entire surface of the resultant material; A second wide via hole formed through the third insulating film so that the surface of the second conductive film pattern is exposed on the first wide via hole; A third dielectric film formed on the third insulating film including the second wide via hole; A third conductive film pattern formed on the third dielectric film in the vicinity of the second wide via hole and electrically connected to the first conductive film pattern, wherein the emitter and the first conductive film pattern A first capacitor is formed with a first dielectric film interposed therebetween, and the first and second conductive film patterns form a second capacitor with the second dielectric film interposed therebetween, and the second and third conductive film patterns are formed in the third capacitor. A capacitor of a semiconductor device configured to form a third capacitor with a dielectric film therebetween is provided.

In order to achieve the above another object, the present invention, the step of forming a first insulating film on the entire surface of the semiconductor substrate with an emitter; Forming a wide contact hole by etching the first insulating film so that the emitter surface is partially exposed; Forming a first dielectric film on the first insulating film including the wide contact hole; Etching the first dielectric film and the first insulating film so as to partially expose the emitter surface at a predetermined distance from the wide contact hole to form a narrow contact hole; Forming a first conductive layer on the entire surface of the resultant and selectively etching the first conductive layer to form a first conductive layer pattern connected to the first dielectric layer and a first wiring line connected to the emitter; Forming a second insulating film on the entire surface of the first dielectric film including the first conductive film pattern and the first wiring line; Etching the second insulating film to form a first wide via hole so that the first conductive film pattern is exposed on the wide contact hole; Forming a second dielectric film on the second insulating film including the first wide via hole; Etching the second dielectric film and the second insulating film to form a plurality of first narrow via holes such that one end of the first conductive film pattern and a surface of the first wiring line are partially exposed; Forming a second conductive film on the entire surface of the resultant and selectively etching the second conductive film to form a second conductive film pattern connected to the first wiring line and a second wiring line connected to the first conductive film pattern; Forming a third insulating film on the second dielectric film including the second conductive film pattern and the second wiring line; Etching the third insulating film to form a second wide via hole so that the second conductive layer pattern is exposed on the first wide via hole; Forming a third dielectric film on the third insulating film including the second wide via hole; Etching the third dielectric film and the third insulating film so as to expose a predetermined portion of the surface of the second wiring line to form a second narrow via hole; And forming a third conductive film on the entire surface of the resultant, and selectively etching the third conductive film to form a third conductive film pattern connected to the second wiring line.

When the capacitor is manufactured to have the above structure, the capacitance between the "emitter-first dielectric film-first conductive film pattern" is set to the capacitance between C1 and the "first conductive film pattern-second dielectric film-second conductive film pattern". When the capacitance between C2 and "second conductive film pattern-third dielectric film-third conductive film pattern" is C3, the total capacitance T is T = C1 + C2 + C3 = 3C (C = C1 = C2 = C3). Since the value is increased, the capacitance can be three times higher than the conventional case even if the area occupied by the capacitor within the limited cell area is the same as before. Therefore, even if the area occupied by the capacitor is about one third of the size, capacitance reduction does not occur, and as a result, the size of the capacitor can be reduced.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

3 is a cross-sectional view showing a capacitor structure of the bipolar device proposed in the present invention.

According to the cross-sectional view of FIG. 3, in the capacitor of the bipolar device proposed in the present invention, an emitter 102 is formed in the semiconductor substrate 10, and a first insulating film 104 is formed on the emitter 102. A wide contact hole is formed in the first insulating film 104 to penetrate the first insulating film 104 so that the surface of the emitter 102 is partially exposed, and on the first insulating film 104 including the wide contact hole. A first dielectric film 106 formed of a nitride film material is formed, and a first conductive film pattern 108 made of a metal film or a polysilicon film is formed on the first dielectric film 106 in the vicinity including the wide contact hole. A second insulating film 112 is formed on the entire surface of the resultant, and the second insulating film 112 penetrates through the second insulating film 112 so that the surface of the first conductive film pattern 108 is exposed from the upper portion of the wide contact hole. The first wide via hole is formed A second dielectric layer 114 of nitride material is formed on the second insulating layer 112 including the first wide via hole, and a metal is formed on the second dielectric layer 114 near the first dielectric layer 114 including the first wide via hole. A second conductive film pattern 118 formed of a film or polysilicon film is formed, and a third insulating film 120 is formed on the entire surface of the resultant product, and a second conductive film pattern 118 is formed in the third insulating film 120. A second wide via hole penetrating the third insulating film 120 is formed to expose a surface of the first wide via hole. The third wide via hole is formed on the third insulating film 120 including the second wide via hole. A dielectric film 122 is formed, and a third conductive film pattern 124 made of a metal film or a polysilicon film is formed on the third dielectric film 122 near the second wide via hole. 102-first dielectric film 10 6) -first conductive film pattern 108 constitutes the first capacitor, and " first conductive film pattern 108-second dielectric film 114-second conductive film pattern 118 " It can be seen that the device is configured such that the "second conductive film pattern 118-third dielectric film 122-third conductive film pattern 124" forms a third capacitor.

At this time, the emitter 102 and the second conductive film pattern 118 are electrically connected through the first wiring line 110 formed on one side of the capacitor, and the first conductive film pattern 108 and the third conductive film are electrically connected. The pattern 124 is electrically connected through the second wiring line 116 formed on the other side of the capacitor, so that the first to third capacitors are connected in parallel with each other.

4 shows an equivalent circuit diagram of a capacitor having the above structure. In the equivalent circuit diagram, for convenience, the capacitance between the "emitter 102-the first dielectric film 106-the first conductive film pattern 108" is set to C1, the "first conductive film pattern 108-the second dielectric film 114". The capacitance between -second conductive film pattern 118 "is shown as C2, and the capacitance between" second conductive film pattern 118-third dielectric film 122-third conductive film pattern 124 "is denoted by C3.

Therefore, the capacitor having the above structure is manufactured through the following sixth step as can be seen from the process flow chart shown in FIGS. 5A to 5F.

As a first step, as shown in FIG. 5A, a first insulating film 104 made of an oxide film is formed on the entire surface of the semiconductor substrate 100 including the emitter 102, and the surface of the emitter 102 is formed. The first insulating layer 104 is selectively etched to expose a predetermined portion to form a wide contact hole h1 in the insulating layer 104. Subsequently, a first dielectric layer 106 made of nitride is formed on the first insulating layer 104 including the wide contact hole h1.

As a second step, as shown in FIG. 5B, the first dielectric film 106 and the first insulating film 104 are exposed to a predetermined portion of the surface of the emitter 102 at a point spaced apart from the wide contact hole h1 by a predetermined distance. ) Is selectively etched to form a narrow contact hole h2.

As a third step, as shown in FIG. 5C, a first conductive film made of a metal film or a polysilicon film is formed on the entire surface of the resultant material, and the first dielectric film 106 is selectively etched to expose a predetermined portion of the surface of the first dielectric film 106. The conductive film pattern 108 and the first wiring line 110 are formed at the same time. In this case, the first conductive film pattern 108 is formed to be connected to the emitter 102 with the first dielectric film 106 interposed therebetween, and the first wiring line 110 is directly connected to the emitter 102. It is formed to be.

As a fourth step, as shown in FIG. 5D, a second insulating film 112 made of an oxide film is formed on the first dielectric film 106 including the first conductive film pattern 108 and the first wiring line 110. In addition, the first conductive layer pattern 108 is selectively etched to expose the surface of the first conductive layer pattern 108 on the wide contact hole h1 to form a first wide via hole h3 in the insulating layer 112. Subsequently, a second dielectric film 114 of nitride material is formed on the second insulating film 112 including the first wide via hole h3, and the surface of one end portion of the first conductive film pattern 108 and the first wiring are formed. The second dielectric layer 114 and the second insulating layer 112 are selectively etched to expose a predetermined portion of the surface of the line 110 to form a plurality of first narrow via holes h4.

As a fifth step, as shown in FIG. 5E, a second conductive film is formed on the entire surface of the resultant product, and the second conductive film pattern 118 and the second conductive film pattern 118 are selectively etched to expose a predetermined portion of the surface of the second dielectric film 114. 2 wiring lines 116 are formed simultaneously. In this case, the second conductive film pattern 118 is formed to be electrically connected to the emitter 102 through the first wiring line 110, and the second wiring line 116 is formed of the first conductive film pattern 108. It is formed to be electrically connected with. Subsequently, a third insulating film 120 of an oxide film is formed on the second dielectric film 114 including the second conductive film pattern 118 and the second wiring line 116, and the surface of the second conductive film pattern 118 is formed. Selectively etching the first wide via hole h3 to expose the second wide via hole h5 in the insulating layer 120, and then forming a third dielectric layer 122 of nitride material on the entire surface of the first wide via hole h3. The third dielectric layer 122 and the third insulating layer 120 are selectively etched to expose a predetermined portion of the surface of the second wiring line 116 to form a second narrow via hole h5.

As a sixth step, as shown in FIG. 5F, a third conductive film made of a metal film or a polysilicon film is formed on the entire surface of the resultant product, and the third dielectric film 122 is selectively etched to expose a predetermined portion of the surface of the third dielectric film 122. By forming the conductive film pattern 124, the process progress is completed. In this case, the third conductive film pattern 124 is formed to be electrically connected to the first conductive film pattern 108 through the second wiring line 116.

As described above, when the bipolar device is manufactured, as shown in the equivalent circuit diagram of FIG. 4, the total capacitance T of the capacitor shown in FIG. 3 has a value of T = C1 + C2 + C3, and thus C = C1 = C2 = C3. Assuming that the equation T = 3C holds. That is, even if the area occupied by the capacitor within the limited cell area is the same as before, the capacitance can be three times higher than in the related art. Therefore, when designing a capacitor as shown in FIG. 3, the area occupied by the capacitor within the limited cell area can be reduced to about 1/3 of the conventional size without reducing capacitance.

Here, as an example, only the capacitor structure of the bipolar device is mentioned, but the above structure is equally applicable to the manufacture of the bi-MOS device.

As described above, according to the present invention, when the bipolar device or the bi CMOS device is manufactured, the capacitors are stacked in a stacked structure, and the devices are designed so that they are connected in parallel to each other, so that the capacitors are limited within a limited cell area without reducing capacitance. Since the area to be occupied can be reduced, the degree of integration of the semiconductor device can be improved.

Claims (2)

A semiconductor substrate provided with an emitter; A first insulating film formed on the entire surface of the substrate; A wide contact hole formed through the first insulating film so that the surface of the emitter is partially exposed; A first dielectric layer formed on the first insulating layer including the wide contact hole; A first conductive film pattern formed on the first dielectric film in the vicinity thereof including the wide contact hole; A second insulating film formed on the entire surface of the resultant material; A first wide via hole formed through the second insulating film so that the first conductive film pattern is exposed on the wide contact hole; A second dielectric film formed on the second insulating film including the first wide via hole; A second conductive film pattern formed on the second dielectric film in the vicinity of the first wide via hole and electrically connected to the emitter; A third insulating film formed on the entire surface of the resultant material; A second wide via hole formed through the third insulating film so that the surface of the second conductive film pattern is exposed on the first wide via hole; A third dielectric film formed on the third insulating film including the second wide via hole; A third conductive film pattern formed on the third dielectric film in the vicinity of the second wide via hole and electrically connected to the first conductive film pattern, wherein the emitter and the first conductive film pattern A first capacitor is formed with a first dielectric film interposed therebetween, and the first and second conductive film patterns form a second capacitor with the second dielectric film interposed therebetween, and the second and third conductive film patterns are formed in the third capacitor. And a third capacitor having a dielectric film interposed therebetween. Forming a first insulating film on the entire surface of the semiconductor substrate including the emitter; Forming a wide contact hole by etching the first insulating film so that the emitter surface is partially exposed; Forming a first dielectric film on the first insulating film including the wide contact hole; Etching the first dielectric film and the first insulating film so as to partially expose the emitter surface at a predetermined distance from the wide contact hole to form a narrow contact hole; Forming a first conductive layer on the entire surface of the resultant and selectively etching the first conductive layer to form a first conductive layer pattern connected to the first dielectric layer and a first wiring line connected to the emitter; Forming a second insulating film on the entire surface of the first dielectric film including the first conductive film pattern and the first wiring line; Etching the second insulating film to form a first wide via hole so that the first conductive film pattern is exposed on the wide contact hole; Forming a second dielectric film on the second insulating film including the first wide via hole; Etching the second dielectric film and the second insulating film to form a plurality of first narrow via holes such that one end of the first conductive film pattern and a surface of the first wiring line are partially exposed; Forming a second conductive film on the entire surface of the resultant and selectively etching the second conductive film to form a second conductive film pattern connected to the first wiring line and a second wiring line connected to the first conductive film pattern; Forming a third insulating film on the second dielectric film including the second conductive film pattern and the second wiring line; Etching the third insulating film to form a second wide via hole so that the second conductive layer pattern is exposed on the first wide via hole; Forming a third dielectric film on the third insulating film including the second wide via hole; Etching the third dielectric film and the third insulating film so as to expose a predetermined portion of the surface of the second wiring line to form a second narrow via hole; And forming a third conductive film on the entire surface of the resultant, and selectively etching the third conductive film to form a third conductive film pattern connected to the second wiring line.

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