KR100699685B1 - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device and a method for manufacturing the same are provided to simplify the process by forming simultaneously an MIM(Metal-Insulator-Metal) lower electrode and a metal line, and to increase the capacitance by using the MIM lower electrode of a convavo-concave shape. An interlayer dielectric(110) is formed on a substrate(100) having a conductive layer. A contact subsidiary layer(120), an etch stop layer(130) and a metal film(140) are sequentially formed on the interlayer dielectric. The metal film is patterned to expose the etch stop layer. A dielectric film(150) is formed on the metal film and the etch stop layer. A titanium film(160) is formed on the dielectric film. A TiN layer(170) is formed on the titanium film. An MIM upper electrode(305) is formed by etching the TiN layer, the Ti film and the dielectric film. An MIM lower electrode(302) and a metal line(320) are simultaneously formed by etching the metal film, the etch stop layer and the contact subsidiary layer located at a portion except for the MIM upper electrode.

Description

Semiconductor device and manufacturing method therefor {SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF}

1 is a diagram illustrating a structure of a semiconductor device in accordance with an embodiment of the present invention.

2 to 8 are steps illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a method for manufacturing a semiconductor device having a high capacity metal insulator metal (MIM) capacitor.

BACKGROUND OF THE INVENTION In recent years, merged memory logic (MML) is a device in which a memory cell array unit, for example, a dynamic random access memory (DRAM) and an analog or peripheral circuit is integrated together in one chip. . Due to the emergence of such composite semiconductor devices, multimedia functions have been greatly improved, and high integration and high speed of semiconductor devices can be effectively achieved.

In a composite semiconductor device (MML), an analog circuit must implement a high capacity capacitor to operate at high speed. Therefore, in the analog circuit, a MIM capacitor having a small specific resistance and no parasitic capacitance due to depletion therein is used.

Conventionally, MIM type capacitors form titanium (Ti), titanium nitride (TiN), a first metal film, a dielectric, a second metal film, and a photoresist film sequentially on a semiconductor substrate including a conductive layer, and use the photoresist film as a mask to form a second metal. It is made by patterning a film, a dielectric, a first metal film, titanium nitride and titanium in sequence.

However, the MIM capacitor made through this manufacturing method is composed of the first electrode at the bottom and the second electrode at the top of the dielectric, and since the effective surface area of the capacitor is planar, there may be a limitation in securing the capacity of the capacitor. have.

Accordingly, the present invention provides a semiconductor device capable of forming a high capacity MIM capacitor which is advantageous in a semiconductor device that is gradually becoming highly integrated, and a method of manufacturing the same.

A semiconductor device and a method of manufacturing the same according to the present invention include a semiconductor substrate having a conductive layer, an interlayer insulating film formed on the semiconductor substrate, a metal wiring and a MIM capacitor formed at predetermined intervals on the interlayer insulating film, and the MIM capacitor The MIM lower electrode is formed of a contact auxiliary layer, an etch stop layer, and a metal layer spaced apart at predetermined intervals, which are sequentially formed on the interlayer insulating layer, and the etch stop layer is exposed between the metal layers, and the unevenness is formed on the MIM lower electrode. It is composed of a dielectric formed in a structure and an MIM upper electrode formed on the dielectric.

The metal layer may be aluminum (Al).

Forming an interlayer insulating film on a semiconductor substrate including a conductive layer, sequentially forming a contact auxiliary layer, an etch stop film and a metal layer on the interlayer insulating film, patterning the metal layer to expose a portion of the etch stop film, and the metal layer And forming a dielectric on the etch stop layer, forming a flat titanium layer on the dielectric, forming a titanium nitride layer on the titanium film, the titanium nitride film, the titanium Etching the film and the dielectric to form a MIM upper electrode of the MIM capacitor, and etching the metal layer, the etch stop layer, and the contact auxiliary layer existing in a region other than the MIM upper electrode region to etch the MIM lower portion of the MIM capacitor. Forming an electrode and a metal wiring.

The etch stop layer may be made of a thickness of 500 kPa to 1,500 kPa.

The contact auxiliary layer is formed to a thickness of 500 Å to 1,000 Å, the titanium film is formed to a thickness of 500 Å to 1,000 Å, the titanium nitride film is formed to a thickness of 500 Å to 1,500 Å, and the dielectric may have a thickness of 200 Å to 1,500 Å It can be formed in thickness.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, area, plate, etc. is over another part, this includes not only the part directly above the other part but also another part in the middle. On the contrary, when a part is just above another part, it means that there is no other part in the middle.

Next, a metal wiring and a method of forming the semiconductor device according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a diagram illustrating a structure of a semiconductor device in accordance with an embodiment of the present invention.

First, the structure of a semiconductor device will be described in detail with reference to FIG. 1.

As shown in FIG. 1, an interlayer insulating film 110 is formed on a semiconductor substrate 100 including a conductive layer, and a MIM capacitor 310 and a first metal wiring 320 are formed on the interlayer insulating film 110. The second metal wire 240 is formed on the first metal wire 320. The wiring insulating layer 220 is formed on the sidewalls of the MIM capacitor 310, the first and second metal wires 320 and 240, and the interlayer insulating film 110. The MIM capacitor 310 and the first and second metal wires 320, 240) is formed without a step.

In this case, the contact auxiliary layer 120, the etch stop layer 130, and the metal layer 140 are sequentially formed on the first metal wire 320. In addition, the MIM capacitor 310 may include a dielectric auxiliary layer on the MIM lower electrode 302 and the MIM lower electrode 302, which are formed by sequentially forming the contact auxiliary layer 120, the etch stop layer 130, and the metal layer 140. And a MIM upper electrode 305 formed by sequentially forming a titanium layer (Ti layer) 160 and a titanium nitride layer (TiN layer) 170 on the dielectric 150. In this case, the metal layer 140 of the MIM lower electrode 302 is spaced at a predetermined interval d to expose the lower etch stop layer 130.

2 to 8 are diagrams illustrating manufacturing steps of a semiconductor device according to an embodiment of the present invention.

As shown in FIG. 2, an interlayer insulating film 110 is formed on the semiconductor substrate 100 including the conductive layer, and the contact auxiliary layer 120, the etch stop film 130, the metal layer 140, and the first interlayer insulating film 110 are formed thereon. 1 Photosensitive film 150 is formed in order. At this time, the metal layer 140 is preferably aluminum. The etch stop layer 130 is made of titanium nitride (TiN) and is formed to have a thickness of 500 kV to 1,500 kPa. .

Next, as shown in FIG. 3, the etch stop layer 130 is exposed between the metal layers 140 spaced at a predetermined interval d by patterning the metal layer 140 using the first photoresist layer 150 as a mask. Be sure to In this case, the etch stop layer 130 becomes an etch stop point. The polymer 162 generated by the etching process remains on the sidewall of the metal layer 140 patterned through the etching process.

Subsequently, the first photoresist layer 160 is removed through a plasma process using oxygen (O 2).

Next, as shown in FIG. 4, the polymer 162 is removed by a wet etch process. Next, a dielectric 150 is formed on the metal layer 140 and the etch stop layer 130, and a titanium film 160 and a titanium nitride film 170 are sequentially formed thereon, as shown in FIG. 5. The second photoresist layer 180 is formed on the layer 170. In this case, the dielectric 150 may be formed of a nitride film or an oxide film, is formed to a thickness of 200 ~ 1,500 ,, the titanium film 160 is formed to a thickness of 500 ~ 1,000Å, the titanium nitride film 170 is 500 ~ It is preferable to form in thickness of 1,500 kPa.

6, the MN upper electrode 305 is formed by patterning the titanium nitride film 170, the titanium film 160, and the dielectric 150 using the second photoresist film 180 as a mask. 2 The photosensitive film 180 is removed. In this case, the metal layer 140 becomes an etch stop point.

Next, as shown in FIG. 7, the third photosensitive film 200 is formed on the entire upper surface of the semiconductor substrate 100, and as shown in FIG. 8, the metal layer 140 using the third photosensitive film 200 as a mask. The etch stop layer 130 and the contact auxiliary layer 120 are sequentially etched to form the MIM lower electrode 302 and the first metal wiring 320. At this time, a MIM capacitor 310 composed of the dielectric 150, the MIM lower electrode 302, and the MIM upper electrode 305 is formed. And the third photosensitive film 200 is removed.

Here, the MIM lower electrode 302 of the MIM capacitor 310 is formed of the metal layer 140 spaced apart at a predetermined interval d so that the dielectric 150 formed on the metal layer 140 forms the uneven structure A. FIG. As such, the surface area of the MIM capacitor 310 is wider by the surface area for the sidewall of the metal layer 140 than the surface area of the MIM capacitor having a conventional flat shaped dielectric. Therefore, the capacity of the MIM capacitor according to the present invention is larger than that of the conventional MIM capacitor.

Then, the wiring insulating layer 220 is deposited on the entire upper surface of the semiconductor substrate 100, and a chemical mechanical polishing (CMP) process is performed to planarize the layer to a height consistent with the titanium nitride 170. A contact hole 205 exposing the metal layer 140 of the first metal wire 320 is formed by patterning the wiring insulating layer 220 by using the mask 210 as a mask.

Next, as shown in FIG. 1, the metal thin film is filled in the contact hole 205 to form a second metal wire 240 that is electrically connected to the first metal wire 320.

According to the present invention, the MIM lower electrode and the metal wiring of the MIM capacitor are simultaneously made to simplify the process, and the MIM lower electrode is formed into an uneven structure, thereby increasing the surface area of the MIM capacitor to prepare for the layout in the chip. Since the capacity can be increased, the characteristics and reliability of the semiconductor device can be improved.

Although the preferred embodiments of the present invention have been described in detail above, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Accordingly, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concept of the present invention as defined in the following claims also fall within the scope of the present invention.

Claims (8)

delete delete Forming an interlayer insulating film on the semiconductor substrate including the conductive layer, Sequentially forming a contact auxiliary layer, an etch stop film, and a metal layer on the interlayer insulating film, Patterning the metal layer to expose a portion of the etch stop layer, Forming a dielectric on the metal layer and the etch stop layer; Forming a titanium layer on the dielectric; Forming a titanium nitride film (TiN layer) on the titanium film; Etching the titanium nitride film, the titanium film and the dielectric to form a MIM upper electrode of a MIM capacitor; and Etching the metal layer, the etch stop layer, and the contact auxiliary layer existing in a region other than the MIM upper electrode region to form a MIM lower electrode and a metal wiring of the MIM capacitor; Method for manufacturing a semiconductor device comprising a. In claim 3, The etch stop layer is a semiconductor device manufacturing method of about 500 ~ 1,500㎛ thickness. In claim 3, The contact auxiliary layer is a manufacturing method of a semiconductor device to form a thickness of 500 ~ 1,000Å. In claim 3, The titanium film is a method of manufacturing a semiconductor device to form a thickness of 500 ~ 1,000Å. In claim 3, The titanium nitride film is a method of manufacturing a semiconductor device to form a thickness of 500 kV to 1,500 kV. In claim 3, The dielectric is a method of manufacturing a semiconductor device to form a thickness of 200 ~ 1,500Å.

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