JPS5885550A - Manufacture of laminated integrated circuit element - Google Patents

Abstract

PURPOSE:To effectively obtain electric conduction between laminated layer semiconductor layers by exposing the part of respective semiconductor layers sequentially from the substrate side and accumulating wirings for connecting electrode extension ends between elements of the respective layers at the exposed part. CONSTITUTION:An impurity is implanted from the surface into a silicon substrate by an ordinary method, thereby forming a necessary semiconductor element, an electrode 3 to the element is accumulated, and the electrode 3 is led through the first oxidized silicon film 2 to the periphery of a silicon substrate 1 only at the necessary part of the electrode wiring between the elements formed on the upper silicon film laminated on the substrate 1. Thereafter, the electrode 3 is converted with the second oxidized silicon film 4 except the periphery of the substrate 1, and the second layer silicon film 5 is further formed similarly on the film 4 except the periphery of the substrate 1. Similarly, semiconductor elements and interlayer wirings are sequentially formed from the second layer to the uppermost silicon layer.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a laminated integrated circuit element, and more particularly to an electrode wiring technique between semiconductor layers constituting each circuit element.

In a stacked integrated circuit in which two or more semiconductor layers are stacked with a dielectric film on the entire surface or in part, and each semiconductor layer functions as a circuit element, it is necessary to conduct electrode wiring to electrically connect each semiconductor layer. There is. There is a method for this, which is conventionally used in multilayer printed circuit boards, etc., by forming through holes and obtaining electrical continuity between the upper and lower semiconductor layers through the through holes. need to have a minute diameter, which causes problems such as poor conduction, making it extremely difficult in practice to obtain a good interlayer wiring structure.

In addition, dielectric films generally have low thermal conductivity, so if a dielectric film is used to separate each semiconductor layer in a laminated integrated circuit element, dissipation of heat generated in the circuit element will be worsened, leading to malfunction. In view of the above-mentioned problems, the present invention prevents conduction defects in laminated integrated circuit elements and promotes heat dissipation from each laminated semiconductor layer by high thermal conductivity of electrodes taken out from each semiconductor layer. It is an object of the present invention to provide a method for manufacturing a laminated integrated circuit element having a good interlayer wiring formation technique.

Hereinafter, one embodiment of the F1 present invention will be explained in detail with reference to the drawings.

FIG. 1 is a configuration diagram of an interlayer wiring structure section explaining one embodiment of the present invention.

Impurities are introduced into the silicon substrate 1 from the surface using a normal method to form necessary semiconductor elements, electrodes 3 for the semiconductor elements are deposited, and the semiconductor is laminated on the silicon substrate 1. Only the parts where electrode wiring is required between the device and the silicon substrate 1 are connected to the periphery of the first
The electrode 3 is taken out through the silicon oxide film 2.

Thereafter, the electrode 3 is covered with a second silicon oxide film 4 except for the peripheral part of the silicon substrate 1, and a second layer silicon film 5 is further formed thereon, except for the peripheral part of the silicon substrate 1. Semiconductor elements are formed in this second layer silicon film 5 in the same manner as in the silicon substrate 1, and electrodes 7 are deposited thereon. At this time, the electrodes 7 of this semiconductor element are connected to the periphery of the second layer silicon film 5 through the third silicon oxide film 6 only where electrode wiring is required between the underlying silicon substrate l or the upper silicon film. Take it out. After forming a semiconductor element in the second layer silicon film 5, the electrodes 3, 7 are taken out around the silicon substrate 1 and the second layer silicon film 5.
The wiring 12 between them is formed in a laminated manner. Similarly, an electrode 11 is taken out around the third silicon film 9 through the silicon oxide film 10 of the rear tube 5 in which a semiconductor element is formed on the third silicon film 9 laminated via the fourth silicon oxide film 8. and electrodes 3 taken out around the silicon substrate 1 and the second layer silicon film 5,
After that, semiconductor elements and interlayer wirings are sequentially formed in the fourth layer, the fifth layer, and the uppermost silicon layer in the same manner.

The silicon oxide films 2, 4, 6, 8, and 10 are dielectric layers for interlayer isolation and insulate the layers from each other. Each electrode 3,7°I+
The wirings 12 and 13 are provided in layers by depositing metal such as Au alloy by vapor deposition or the like.

FIG. 2 is a plan view of the interlayer wiring of the laminated integrated circuit element manufactured in this manner, viewed from above. In the figure, the same symbols as in FIG. 1 indicate the same items.

The laminated integrated circuit element having the above structure is used as an integrated circuit device by covering the surface with resin or other insulating material as necessary.

In the above embodiment, the interlayer wiring was performed at the periphery of the chip, but as shown in FIG. 3, it may also be used at the center of the chip. In addition, interlayer wiring does not need to be performed after semiconductor elements such as transistors and resistors are formed in the silicon layer, and may be performed during the formation of semiconductor elements. may be formed.

As semiconductor materials, all semi-quaternary materials such as silicon in the embodiment, germanium, and gallium arsenide are applied.
Furthermore, two or more of these semiconductor materials may be used in each layer. Furthermore, these semiconductor materials may be single crystal, polycrystalline, or amorphous.

Further, the material used for the interlayer insulation may be any dielectric material, including the silicon oxide used in the embodiment, and may be used in a stack of two or more layers.

Any material may be used for the interlayer wiring as long as it is a conductive material, and any film forming method or pattern forming method may be used.

After forming a semiconductor film on the area where electrodes are taken out for interlayer wiring, etching is performed.

The semiconductor film may be removed using a lithography method or the like, or the semiconductor film may be prevented from being formed only in that portion during the formation of the semiconductor film.

As explained in detail above, according to the present invention, electrical continuity between stacked semiconductor layers can be reliably obtained, and a highly reliable stacked integrated circuit element that does not suffer from problems such as poor continuity can be manufactured. . Furthermore, heat generated from the circuit elements formed in each semiconductor layer can be efficiently dissipated into the atmosphere through the electrode extension ends extending outside the circuit elements, making it possible to maintain stable operating characteristics.

[Brief explanation of drawings]

FIG. 1 is a schematic cross-sectional view of an interlayer wiring portion of a laminated integrated circuit element, explaining one embodiment of the present invention. FIG. 2 is a plan view of the laminated integrated circuit element shown in FIG. 1. FIG. 3 is a plan view of a laminated integrated circuit device illustrating another embodiment of the present invention. l...Silicon substrate 2, 4, 6, 8. IQ... Oxidation Agent Patent Attorney Aihiko Fukushi

Claims (1)

[Claims] l In a laminated integrated circuit element in which at least two or more semiconductor layers are laminated with a dielectric layer interposed therebetween,
A method for manufacturing a laminated integrated circuit device, characterized in that a part of each semiconductor layer is sequentially exposed on the surface from the substrate side, and wiring for connecting electrode extension ends between elements of each semiconductor layer is deposited on the exposed part. .