JPS58213449A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the space of a contact opening, and to increase the degree of integration of the integrated circuit device by constituting the device so that the contact opening may be formed at one position. CONSTITUTION:A first layer polycrystalline silicon layer 3 and a second layer polycrystalline silicon layer 5 are laminated through a first inter-layer insulating film 4. An aluminum wiring layer 7 and both the first layer polycrystalline silicon layer 3 and the second layer polycrystalline silicon layer 5 are connected through the contact opening 8 formed from the surface of a second inter-layer insulating film 6 formed onto the second layer polycrystalline silicon layer 5.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, and particularly to the structure of a wiring layer thereof.

In response to the demand for higher density semiconductor integrated circuit devices, methods are being used to miniaturize pattern formation and to multilayer wiring layers. 'With regard to multilayer wiring layers, two layers of polycrystalline silicon layers are currently commonly used. Conventional 1st
The electrical connection between the first polycrystalline silicon layer, the second polycrystalline silicon layer, and the metal wiring layer formed thereon is provided in an interlayer insulating film formed between each layer. The contact holes were taken all the way through. For example, the connection between the first layer and the second layer of polycrystalline silicon is made through a contact hole provided in the interlayer insulating film between them, and the connection between the metal wiring layer and the second layer of polycrystalline silicon is made. The connection was made through the entire contact hole provided between them.

An object of the present invention is to simplify the structure and process of the connection between multilayer interconnections, which have conventionally been electrically connected through separate openings.

A semiconductor integrated circuit device of the present invention includes a first polycrystalline semiconductor layer provided on the entire surface of a semiconductor substrate via a first insulating film, and a second insulating film provided on the first polycrystalline semiconductor layer. a second polycrystalline semiconductor layer provided through a third insulating film, and a metal wiring layer provided on the second polycrystalline semiconductor layer with a third insulating film interposed therebetween; The main feature is that the connection to the first and second polycrystalline semiconductor layers is made through the same opening.

Next, embodiments of the present invention will be described using the drawings. In the embodiment of the present invention shown in FIGS. 1 to 3, a first polycrystalline silicon layer 3 and a second polycrystalline silicon layer 5 are laminated with a first glabella insulating film 4 in between. A second interlayer insulating film 6 provided on the second polycrystalline silicon layer 5
The aluminum wiring layer 7 is connected to the first polycrystalline silicon layer 5 and the second polycrystalline silicon layer 5 through contact holes 8 provided from the surface. The structure immediately before the contact tube hole 8 is provided is shown in FIG. A first polycrystalline silicon layer is formed.

In the MOB type integrated circuit device, the silicon dioxide 2 is a field insulating film and is formed to have a thickness of about 0.5 μm.

Further, in this embodiment, silicon dioxide 2. Although impurities are not introduced into the surface of the silicon substrate 1 immediately below, an impurity diffusion layer for a channel stopper may be provided. Further, the first polycrystalline silicon layer 3 or the second polycrystalline silicon layer 5 can be used as a gate electrode of an MO8 type transistor. The first glabellar insulating film 4 is silicon dioxide formed by vapor phase growth. This insulating film 4 is formed for the purpose of electrically insulating between the first polycrystalline silicon layer 3 and the second polycrystalline silicon layer 5. The first layer polycrystalline silicon 3 may be formed by thermal oxidation. The second layered insulating film 6 is made of phosphorus glass formed by vapor phase growth, and is deposited for the purpose of providing complete electrical insulation between the second polycrystalline silicon layer 5 and the aluminum wiring layer 7. It is something that will be done. A Z photoresist is applied to the surface of the substrate in the state shown in FIG. 3, and the resist in the area of the opening 8 is removed by t-ff1s, and then the interlayer films 6 and 3 are etched by anisotropic dry etching. Ching. Because of the anisotropic etching, the interlayer film is not side-etched, and in particular, since the side etching of the interlayer film 4 does not proceed, overhang does not occur at the end of the second layer polycrystalline silicon 5. The aluminum wiring layer 7 will not be disconnected at that part.

Conventionally, a contact hole is formed after forming a first interlayer insulating film, and then a second polycrystalline silicon layer is deposited to establish a connection between the first and second polycrystalline silicon layers. Furthermore, contact holes were formed in the second interlayer insulating film, and then a metal wiring layer was formed to establish all electrical connections between these layers. In the case of the present invention, the step of providing the contact hole only needs to be done once, and in that sense the process is simplified. Further, the contact hole only needs to be provided at one location, and the space for the contact hole may be smaller than the conventional case where the contact hole is provided at two locations. As described above, the present invention is extremely useful as a technology for increasing the density of integrated circuit devices.

Note that another polycrystalline semiconductor layer or an alloy layer of a polycrystalline semiconductor and a metal may be used for the first and second polycrystalline silicon layers. It goes without saying that the effects of the present invention can also be obtained by using an insulator other than silicon dioxide, such as silicon nitride, as the interlayer insulating film.

[Brief explanation of the drawing]

Fig. 1 is a plan view for explaining the present invention in detail, Fig. 2 is a cross-sectional view of the AA' thin section of Fig. 1 viewed in the direction of the arrow, and Fig. 3 is the same as Fig. 2. It is a diagram showing the intermediate steps up to this point. In the figure, l... silicon substrate, 2... silicon dioxide, 3... first layer polycrystalline silicon film,
4...First interlayer insulating film, 5...Second layer polycrystalline silicon film, 6...Second interlayer insulating film, 7... ...All aluminum wiring layers are shown.

Claims (1)

[Claims] A first polycrystalline semiconductor layer provided on the surface of the semiconductor substrate via a first insulating film, and a second polycrystalline semiconductor layer provided on the second polycrystalline semiconductor layer via a second insulating film. In a semiconductor integrated circuit device including a polycrystalline semiconductor layer and a metal wiring layer provided on the second polycrystalline semiconductor layer via a third insulating film, the metal wiring layer and the first A semiconductor integrated circuit device characterized in that a polycrystalline semiconductor layer and a second polycrystalline semiconductor layer are connected through the same opening.