JPS58173890A - Multilayer circuit board - Google Patents

Multilayer circuit board

Info

Publication number
JPS58173890A
JPS58173890A JP5629082A JP5629082A JPS58173890A JP S58173890 A JPS58173890 A JP S58173890A JP 5629082 A JP5629082 A JP 5629082A JP 5629082 A JP5629082 A JP 5629082A JP S58173890 A JPS58173890 A JP S58173890A
Authority
JP
Japan
Prior art keywords
wiring
signal
layer
power supply
ground
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5629082A
Other languages
Japanese (ja)
Inventor
雅一 山本
亮 正木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP5629082A priority Critical patent/JPS58173890A/en
Publication of JPS58173890A publication Critical patent/JPS58173890A/en
Pending legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発明は多層配線基板において、特性インピーダンスの
バラつきを減少させる手段に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to means for reducing variations in characteristic impedance in a multilayer wiring board.

多層配線基板は、電源層、接地層および信号配線層(以
下信号層と略記する)から構成されているが計算機用な
どの高速の信号伝送を目的とする場合は、信号層は電源
層あるいは接地層にはさまれたストリップライン構造に
なっていることが多い。その−例の断面図を第1図に示
す。
A multilayer wiring board consists of a power layer, a ground layer, and a signal wiring layer (hereinafter abbreviated as the signal layer). However, when the purpose is high-speed signal transmission such as for computers, the signal layer is a power layer or a connection layer. They often have a stripline structure sandwiched between strata. A sectional view of an example thereof is shown in FIG.

ここで、1は信号層、2は電源層と接地層を兼ねて導体
を面状に形成した電源・接地層、3は各層を貫通したス
ルーホール、4は信号層1に設けた信号配線である。こ
の場合、電源・接地層2は層数を減少させるため、信号
層102層ごとに設けられている。また、第2図はこの
種の構成を示す平面図で、同図の場合、信号配線のうち
X方向の信号配線4Xは実線で示すように紙面上の信号
層に設けられ、Y方向の信号配線4Yは破線で示すよう
に、その下の信号層に設けである。このように、電源・
接地層にはさまれた2層の信号層を1組として、直交し
た配線75!;なされている。
Here, 1 is a signal layer, 2 is a power supply/ground layer in which conductors are formed in a planar shape and serves as both a power supply layer and a ground layer, 3 is a through hole that penetrates each layer, and 4 is a signal wiring provided in signal layer 1. be. In this case, the power/ground layer 2 is provided for every 102 signal layers in order to reduce the number of layers. FIG. 2 is a plan view showing this type of configuration. In this figure, the signal wiring 4X in the X direction among the signal wirings is provided on the signal layer on the paper as shown by the solid line, and the signal wiring in the Y direction is The wiring 4Y is provided in the signal layer below it, as shown by the broken line. In this way, the power supply
The two signal layers sandwiched between the ground layers form a pair of orthogonal wiring lines 75! ; has been done.

ここで、ある信号配線について、上下1組の信号層の信
号配線が交差する本数を格子ピッチで規格化したものを
配線交差密度と称すると、従来の配線では配線交差密度
は一定にならない。また。
Here, regarding a certain signal wiring, if the number of signal wirings of a set of upper and lower signal layers that intersect is normalized by the lattice pitch is called wiring crossing density, then in conventional wiring, the wiring crossing density is not constant. Also.

従来の配線では配線の疎密があるため、信号配線の単位
長当りの対地容量に大きなバラつきがあり、このため特
性インピーダンスに不同が生じるという欠点が避けられ
なかった0 本発明は上記の欠点を解消し、多層配線基板において各
信号配線の特性インピーダンスのバラつきを小さくする
だめの高密団配線手段を提供することを目的としたもの
である。すなわち本発明においては、信号層で使用され
なかったすべての配線格子上に、電源・接地層に接続さ
れた付加配線を設けることにより、配線交差密度を一定
にし、かつ各信号配線の接地容量をほぼ同一にして、各
信号配線の特性イノビーダ7スを一定化するものである
。以下、本発明を実施例VCより詳細に説明する。
In conventional wiring, due to the spacing and density of the wiring, there is a large variation in ground capacitance per unit length of the signal wiring, which inevitably causes a disparity in characteristic impedance.The present invention eliminates the above drawback. However, it is an object of the present invention to provide a high-density wiring means for reducing variations in characteristic impedance of each signal wiring in a multilayer wiring board. That is, in the present invention, by providing additional wiring connected to the power supply/ground layer on all wiring grids that are not used in the signal layer, the wiring intersection density is kept constant and the ground capacitance of each signal wiring is reduced. This is to make the characteristics of each signal wiring constant by making them almost the same. Hereinafter, the present invention will be explained in more detail with reference to Example VC.

第3図は、多層配線基板の電源・接地層間に設た1組の
信号層すなわち上部信号層と下部信号層の2層の信号層
を示す平面図で、■印で示した信号用のスルーホール3
Aと、X印で示した電源・接地用のスルーホール3Bが
設けられ、これらを結ぶ配線4X、4Yがなされている
。ここで、従来の構成では太い実線で示した上部信号層
(すなわちX方向の配線のみを行なう)の配線4Xと。
Figure 3 is a plan view showing a pair of signal layers, an upper signal layer and a lower signal layer, installed between the power supply and ground layers of a multilayer wiring board. Hall 3
A and a through hole 3B for power supply and grounding indicated by an X mark are provided, and wirings 4X and 4Y are provided to connect these. Here, in the conventional configuration, the wiring 4X of the upper signal layer (that is, only the wiring in the X direction is performed) is shown by a thick solid line.

下部信号層(Y方向の配線のみを行なう)の太い破線で
示した配線4Yのみである。
There is only the wiring 4Y shown by the thick broken line in the lower signal layer (wiring in the Y direction only).

本発明においてはさらに電源・接地層に接続された細い
実線のX方向の配線5Xを上部信号層に、同じく電源・
接地層に接続された細い破線のY方向の配線5Yを下部
信号層に、それぞれ設ける。
In the present invention, a thin solid wire 5X in the X direction connected to the power supply/ground layer is also connected to the upper signal layer.
Thin broken line Y-direction wiring 5Y connected to the ground layer is provided in the lower signal layer.

かくすることにより、信号配線はそれぞれ格子ごとに、
すなわち各スルーホール間ごとに1回ずつ、対向する信
号層の配線と必ず交差することになる。
By doing this, the signal wiring is arranged for each grid.
That is, each through-hole will necessarily intersect with the wiring of the opposing signal layer once.

このようにして、配線交差密度を一様にし、配線〆の疎
による特性インピーダンスのバラつきを小さく抑えるこ
とができる。
In this way, the interconnect density can be made uniform, and variations in characteristic impedance due to sparse interconnections can be suppressed.

次に、本発明の他の実施例を第4図(a)〜(C)に示
す。ここで、(a)はマイクロストリップライン構造の
もの、(b)は2本チャンネルの場合、(C)は電源・
接地層にはさまれた信号層が2層のみでなく多層(図示
の場合は3層)とした場合である。
Next, other embodiments of the present invention are shown in FIGS. 4(a) to 4(C). Here, (a) is for microstrip line structure, (b) is for two channels, and (C) is for power supply/
This is a case where the signal layer sandwiched between the ground layers is not only two layers but multilayered (three layers in the illustrated case).

いずれも、信号配線4が行なわれなかったすべての配線
格子上に、電源・接地層に接続された配線5を設けるこ
とにより、特性インピーダンスを一定化し、クロストー
ク雑音を低減することができる。
In either case, by providing wiring 5 connected to the power supply/ground layer on all wiring grids where signal wiring 4 is not provided, characteristic impedance can be made constant and crosstalk noise can be reduced.

なお、このように電源・接地層に接続された付加配線を
設け、相対する信号層の信号配線と交差させることによ
り、場合によってはその信号配線O対地容量を増大させ
ることになるが、多層配線基板における高雀度の配線の
場合、本発明による付加配゛線は少数桁なわれるのみで
あり、対地容量の増加による影響に比べ、特性イノビー
ダンスを一定化することにより大きな効果を得ることが
できる。
Note that by providing additional wiring connected to the power supply/ground layer in this way and crossing the signal wiring of the opposing signal layer, the signal wiring O-to-ground capacity may be increased in some cases, but multilayer wiring In the case of high frequency wiring on the board, the additional wiring according to the present invention is only a few orders of magnitude, and compared to the effect of increasing the ground capacitance, a greater effect can be obtained by keeping the characteristic innovation constant. .

以上説明したように、不発明による付加配線を行なうこ
とにより、配線の高密度化された多層配線基板における
特性インピーダンスの一定化を図ることができる。
As explained above, by performing additional wiring according to the invention, it is possible to make the characteristic impedance constant in a multilayer wiring board with high wiring density.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は多層配線基板に配線が行なわれた従来の状態を
示す断面図に第2図は多層配線基板の1組の信号層に配
線が行なわれた従来の状態を示す平面図、第3図および
第4図(、)〜(c)は本発明の各実施例を示す断面図
である。 l・・・信号配線層、2・・・電源・接地層、3・・・
スルーホール、3A・・・信号用スルーホール、3B・
・・電源・接地用スルーホールs4・・・信号配線。
Fig. 1 is a sectional view showing a conventional state in which wiring is performed on a multilayer wiring board; Fig. 2 is a plan view showing a conventional state in which wiring is performed in one set of signal layers of a multilayer wiring board; 4(a) to 4(c) are cross-sectional views showing each embodiment of the present invention. l...Signal wiring layer, 2...Power/ground layer, 3...
Through hole, 3A... Signal through hole, 3B.
...Through hole s4 for power supply and grounding...Signal wiring.

Claims (1)

【特許請求の範囲】[Claims] 第1の絶縁板上に導体を面状に形成した電源・接地層と
、上d己電源・接地層にはさまれ第2の絶縁板上りこ行
または列方向の配勝俗子上に信号用導体を形成した信号
配線層とよりなる多層配線基板において、上記信号配線
層の1.3−号配線に使用されなかったすべての配線格
子−上に、上記電源・接地層に接続された配線を設ける
ことを特徴とする多層配線基板。
A power supply/ground layer with a planar conductor formed on the first insulating plate, and a second insulating plate sandwiched between the upper power supply/ground layer and a signal layer on the top of the second insulating plate in the row or column direction. In a multilayer wiring board consisting of a signal wiring layer on which a conductor is formed, the wiring connected to the power supply/ground layer is placed on all wiring grids that are not used for No. 1.3 wiring of the signal wiring layer. A multilayer wiring board characterized in that:
JP5629082A 1982-04-05 1982-04-05 Multilayer circuit board Pending JPS58173890A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5629082A JPS58173890A (en) 1982-04-05 1982-04-05 Multilayer circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5629082A JPS58173890A (en) 1982-04-05 1982-04-05 Multilayer circuit board

Publications (1)

Publication Number Publication Date
JPS58173890A true JPS58173890A (en) 1983-10-12

Family

ID=13022963

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5629082A Pending JPS58173890A (en) 1982-04-05 1982-04-05 Multilayer circuit board

Country Status (1)

Country Link
JP (1) JPS58173890A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6393672U (en) * 1986-12-10 1988-06-17
JPH03215995A (en) * 1990-01-10 1991-09-20 Internatl Business Mach Corp <Ibm> Multilayer wired module

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6393672U (en) * 1986-12-10 1988-06-17
JPH03215995A (en) * 1990-01-10 1991-09-20 Internatl Business Mach Corp <Ibm> Multilayer wired module

Similar Documents

Publication Publication Date Title
JP3238831B2 (en) Design method of multilayer printed circuit board
US6545876B1 (en) Technique for reducing the number of layers in a multilayer circuit board
US4560962A (en) Multilayered printed circuit board with controlled 100 ohm impedance
JP3138383B2 (en) Multi-chip module
US4553111A (en) Printed circuit board maximizing areas for component utilization
US20210327851A1 (en) Embedded organic interposer for high bandwidth
JP2513443B2 (en) Multilayer circuit board assembly
JPS62274692A (en) Printed circuit board
JPS6366993A (en) Multilayer interconnection board
US7017128B2 (en) Concurrent electrical signal wiring optimization for an electronic package
JPS58173890A (en) Multilayer circuit board
US6365839B1 (en) Multi-layer printed circuit board with dual impedance section
JPS63136694A (en) Multilayer interconnection board
JPS61131585A (en) Wiring board
JP2940045B2 (en) Semiconductor integrated circuit
US7358549B2 (en) Multi-layered metal routing technique
JPS62259500A (en) Circuit board
JPH0661594A (en) Circuit substrate
JPH04306506A (en) Flat cable
WO1985001156A1 (en) Printed circuit board maximizing areas for component utilization
JP3872713B2 (en) Multilayer wiring board
JPS58148498A (en) Yield improving pattern for ceramic thick film printed circuit board
JPH0534139Y2 (en)
JPS6342437B2 (en)
CN117979816A (en) Quantum chip packaging substrate and quantum computer