JPH01218051A - Wiring structure of wafer-scale integrated circuit - Google Patents

Abstract

PURPOSE:To sharply reduce the number of designing; manufacturing and inspection processes for a mask by a method wherein the greater part of the mask used to form a mutual wiring part between chip regions in a wafer-scale integrated circuit is designed as a standard pattern. CONSTITUTION:Two or more chip regions 2 are arranged on a wafer 1 at prescribed intervals in the line and row directions. A wiring group 4 extended in the line direction and a wiring group 5 extended in the row direction are formed on the wafer 1 outside the chip regions 2. The wiring group 4 includes two or more linear wiring parts 6 extended in the line direction; the wiring group 5 includes two or more linear wiring parts 7 extended in the row direction. A structure where the wiring group 4 composed of different wiring layers is repeated is presented at each length corresponding to an arrangement interval of the chip regions 2. In addition, end parts of the linear wiring parts 6 which are adjacent in an identical line are formed so as to be overlapped via an interlayer insulating layer. The same structure is formed between the linear wiring parts 7 extended in the row direction and included in the wiring group 5.

Description

DETAILED DESCRIPTION OF THE INVENTION [1] Relating to a wiring structure for interconnecting chip regions arranged in row and column directions in a wafer-scale integrated circuit.

The purpose is to reduce the number of man-hours required for designing, manufacturing, and inspecting interconnections between chip areas, and to form interconnections with high performance and high reliability.

A group of wirings provided extending in the row or column direction on the wafer outside the chip area, each of which is repeated for each chip area, formed from a different M layer for each repetition, and at the end of the repetition. A wiring group including a plurality of cotton-like wirings in which wirings formed from different wiring layers are overlapped with each other via an interlayer insulating layer, and an interlayer insulating layer is provided from a band in a chip region to a wiring group between the chip regions. A mutual wiring pattern is made up of the band wires provided so as to intersect with each other, and contact holes are provided in the interlayer insulating layer at predetermined positions.
It is constructed by connecting the linear wirings included in the desired wiring group and connecting the linear wirings and band wirings.

[Industrial application field]

The present invention relates to a wiring structure for interconnecting circuits formed in different chip areas in a wafer scale integrated circuit.

[Conventional technology]

A wafer-scale integrated circuit is a method in which the necessary integrated circuit blocks are formed in each of multiple chip areas on a semiconductor wafer, and interconnections between the integrated circuit blocks are formed on the wafer without separating these chip areas. It is manufactured by applying in this case.

Since not all chips formed on a wafer are good, integrated circuit blocks are formed with redundancy in advance, and a pass/fail test is performed on each integrated circuit block to determine whether the integrated circuit is a good product. Select blocks and perform interconnections between them.

As a result, the positions of good integrated circuit blocks to be interconnected differ from wafer to wafer, and it is necessary to design interconnection patterns for each wafer.

[Problem to be solved by the invention]

The following two methods have been proposed as methods for forming interconnections between integrated circuit blocks in conventional wafer-scale integrated circuits.

(1) Depending on the test results of the above integrated circuit block.

Method of manufacturing masks for interconnections According to this method, a dedicated interconnection mask and contact hole mask are designed and manufactured for each wafer, so there are many types of masks, and the manufacturing and inspection costs are high. .

(2) Common interconnections are provided on each wafer in advance, and depending on the test results of the integrated circuit blocks, interconnections are made using optical means such as a laser or electrical means such as a fuse. This method involves cutting all unnecessary interconnections or pre-forming all potential connections into a connectable structure. It is necessary to keep it. For this reason, the steps for cutting and connecting these are complicated and take a long time. moreover.

When unnecessary mutual wiring is cut, the resistance value at the cut point is not uniform enough; on the other hand, when necessary wiring is connected,
There are problems such as insufficient reliability at the connection points.

It is an object of the present invention to reduce the number of man-hours for designing, manufacturing, and inspecting interconnections between chip regions, and to make it possible to form interconnections with high performance and high reliability.

[Means to solve the problem]

The above object is to provide a plurality of chip regions arranged on a semiconductor wafer at a predetermined pitch in the row and column directions, each of which is partitioned by edges parallel to the row or column direction, and to pads arranged at a predetermined pitch near the edge; and a plurality of wiring groups disposed on the wafer outside the plurality of chip areas, each wiring group comprising:
It includes a plurality of linear wirings extending parallel to the nearest edge, and each of the linear wirings has a length approximately equal to the arrangement pitch of the chip area in each extending direction.

The linear wirings extending in the same direction are formed from different YA layers separated from each other by interlayer insulating layers for each wiring group adjacent in the row and column directions.

Each of the linear wirings included in one wiring group has an end that overlaps with one end of the cotton wiring included in the adjacent wiring group in the same row or column with the interlayer insulating layer interposed therebetween. an opening is provided in the interlayer insulating layer between predetermined end portions, and the overlapping end portions are connected to each other through the opening, and the end portions of each wiring group are connected to each other through the opening. The position is such that displacement of the arrangement pitch of the pads in the extending direction of the linear wiring or the minimum distance between the pad and the edge of the chip area in the extending direction is permitted, and the position is within the range of each of the wiring groups. The mutual positional relationship of the end portions is the same for the wiring groups including the linear wiring extending in the same direction, and from the pad in each chip area to the wafer outside the chip area. A wire formed to have a length that extends to reach the vicinity of the adjacent chip region, the wire group formed between the adjacent chip regions and the interlayer insulating layer or another interlayer insulating layer. The linear wires included in the wire group arranged between the adjacent chip regions have intersections that overlap each other via the intersecting portions, and an opening is provided in the glabella insulating layer at a predetermined intersection. and pad wiring interconnected through the open circuit. This is achieved by the wiring structure of a wafer-scale integrated circuit according to the present invention.

[For production]

Wiring provided extending in the row or column direction on the wafer outside the chip area is manipulated in chip area units,
Each repetition is formed from a different wiring layer, and a different layout is formed at the end of the repetition! A wire group consisting of linear wires provided so that wires formed from layers overlap each other with an interlayer insulating layer interposed therebetween, and a wire group consisting of linear wires provided so that the wires formed from layers overlap with each other with an interlayer insulating layer interposed therebetween, and a wire group consisting of linear wires provided so as to overlap each other with an interlayer insulating layer interposed therebetween, and a wire group consisting of linear wires provided so as to overlap each other with an interlayer insulating layer interposed therebetween. A wiring pattern is formed by forming a contact hole in the insulating layer between the eyebrows at a predetermined position to connect the linear wirings included in the desired wiring group and between the linear wiring and the band. Connect the wires together.

As a result, the mutual wiring between chip areas can be provided as a standard pattern common to all wafers, and the dedicated patterns required for each wafer are the connection points between the linear wirings and the connection points between the linear wirings and the pad wirings. Only the pattern of the contact hole is required, and it is only necessary to add this pattern to the mask for forming the contact hole in the two ordinary interlayer insulating layers. As a result, it becomes possible to significantly reduce the number of man-hours for designing interconnections between chip regions and for manufacturing and inspecting masks for each wafer.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

As shown in FIG. 1(a), a plurality of chip regions 2 are arranged at a predetermined pitch in the row and column directions on a wafer 1 made of, for example, single crystal silicon. Each chip area 2
has a rectangular shape defined by edges parallel to the row and column directions. On the wafer 1 in each chip area 2, one type of integrated circuit block necessary for constructing a wafer-scale integrated circuit is formed. Further, in each chip area 2, pads 3 are provided along the vicinity of the edge for connecting the integrated circuit block to an integrated circuit block in another chip area 2 or an external circuit outside the wafer 1. ing. The above structure is the same as that of a normal wafer scale integrated circuit.

In the present invention, a wiring group 4 extending in the row direction and a wiring group 5 extending in the column direction are formed on the wafer 1 outside the chip area 2. As shown in the enlarged view of FIG. 1(b), the wiring group 4 includes a plurality of linear wirings 6 extending in the row direction, and the wiring group 5 includes a plurality of linear wirings 7 extending in the column direction.

The cotton-like wiring 6 has a length approximately equal to the arrangement pitch in the row direction of the chip region 2, and is formed from a wiring layer different from the linear wiring in the wiring group 4 adjacent in one row or column direction. It is formed. That is, in FIG. 1 (bl), the linear wiring 61 included in the wiring group 41 is
The wiring layer is different from the linear wiring 62 included in the wiring group 43 and the linear wiring 63 included in the wiring group 43. In this case, four wiring groups (
4□, 43, etc.) may be formed from the same vA layer. In this way, different layouts can be created for each length corresponding to the arrangement pitch of the chip area 2! ! The wiring group 4 formed from the A layer exhibits a structure in which the wires are manipulated.

Furthermore, the ends of adjacent linear interconnections 6 in the same row are formed to overlap with each other with one interlayer insulating layer interposed therebetween. For example, as shown in FIG. 1(C), a linear wiring v
A6. is at one end of the linear arrangement 16□ at one end thereof, and at the other end.

It overlaps with one end of another linear wiring (not shown).

Therefore, the length of each cotton-like wiring 6 is longer than the arrangement pitch of the chip region 2 by the amount corresponding to the above-mentioned shape. and,
Nine interlayer insulating layers 8 are interposed in this overlapping portion, and the linear wirings 6 are insulated from each other by the interlayer insulating layers 8 unless necessary.

The above description is based on the relationship between the linear wirings 7 included in the wiring group 5 and extending in the column direction, for example, the linear wirings 7. The same is true for the linear wirings 72 and 73 adjacent thereto in the row or column direction.

As a result, the cotton wires 6 of the wire group 4 and the linear wires 7 of the wire group 5 can be arranged so as to intersect with each other with the interlayer insulating layer 8 interposed therebetween.

On the other hand, each band 3 is connected to a pad wiring 9 that extends on the wafer 1 outside the chip area 2 and has a length reaching the vicinity of the adjacent chip area 2.

The band wiring is formed between the chip region 2 in which it is formed and an adjacent chip region.

It intersects with the wiring group 4 or the wiring group 5 via the interlayer insulating layer or another interlayer insulating layer.

Therefore, referring to FIG. It is necessary to form the

Assuming that the linear wirings 6 and 7 and the pad wiring 9 are composed of two wiring layers -1 and 2, the relationship between each wiring and the wiring layer is as follows.

Linear wiring6. ...1 Linear wiring 6□...1l12 Linear wiring 63...What 2 Linear wiring 71,...W.

Linear wiring 7□...W2 Linear wiring 73...H2 Pad arrangement, v! 9I・・・・W2 Bad wiring 9□・・・・匈2 Band wiring9.・　・・−.

Pad wiring 94...-1 Now, an example will be described in which interconnections between chip regions are made using wiring groups structured as described above and pad wiring.

Referring to FIG. 2, it is assumed that the next pads of adjacent chip areas A and B are connected.

(Pad 3b in the al chip area and pad 3a in the chip area B (Pad 3C in the bl chip area and pad 3g in the chip area B) First, in order to form the mutual wiring of the (al).

A contact hole is generated in the interlayer insulating layer at each of the following intersection positions.

■Pad wiring 9b and wiring group 4 connected to pad 3b in chip area A. ■ Between the pad wiring vA9a connected to the pad 3a in the chip area B and the linear wiring 6B belonging to the wiring group 4□■ Between the linear wiring 6^ in the wiring group 41 Between the overlapping ends (T4) with the linear wiring 6B in the wiring group 4□,
In order to form the above (bl interconnection).

A contact hole is generated in the interlayer insulating layer at each of the following intersection positions.

■ Between the pad wiring 9c connected to the pad 3c in chip area A and the linear wiring 7^ belonging to wiring group 5■ Between the pad wiring 9g connected to pad 3g in chip area B and belonging to wiring group 5 A contact hole is created at least between the line wire 7A and the line wires overlapping each other at this position and the line wires and pad wires crossing each other are connected through these contact holes.

The plan view and sectional view of ■ and ■ in the case of (a) above are enlarged and shown in Figure 3 (al and (bl). Figure 3 (
With reference to a) and (b), on the wafer l an insulating layer IO
A linear wiring 6B is formed through the .

Interlayer insulating layer 8 having contact holes 11 and holes 2
Further, on the first interlayer insulating layer 8, a linear wiring 68 and a pad wiring 9a made of the same wiring layer are formed. In this way, the linear wiring 68 and the cotton wiring 6
The pad wiring 9a and the cotton wire 6B are connected to each other.

Connection through the contact holes 11 and 12 does not require any special process. 5 In the same way as a normal wiring formation process, the linear wiring 6B made of the lower wiring layer is formed as a standard pattern, and the contact holes 11 and 12 are formed as a standard pattern. and 12
is provided on the N-interlayer insulating layer s.

Connection can be achieved simply by forming the linear wiring 6^ and pad wiring 9a, which are comprised of the upper wiring layer, as a standard pattern.

Note that the number of integrated circuit blocks in the chip area is 1.
For example, when formed using a lower wiring layer made of polycrystalline silicon and an upper wiring layer made of metal such as aluminum, among the wiring groups 4 and 5 and the pad wiring 9 in the present invention, the lower wiring layer is used. For example, the linear wiring 6B in FIG. 3 can be formed using the upper wiring layer in the chip area. this is.

In the present invention, the wiring groups 4 and 5 and the pad wiring 9 are formed as a standard pattern, and interconnections between the chip areas 2 can be made by simply specifying the connection positions between these wiring groups and between the wiring group and the pad wiring. This is because it can be achieved with

Furthermore, the wiring groups 4 and 5 are electrically separated in chip area units, and have a structure that allows connection at necessary locations. Therefore, there is no need for processes such as cutting unnecessary wiring, and the number of linear wirings included in each wiring group is smaller than the number of wirings arranged between chip areas in conventional wafer-scale integrated circuits. Even with a small number of interconnections, it is possible to provide the required interconnection between the chip regions 2.

In addition, in the above embodiment, an example of interconnection between adjacent chip areas was shown, but between linear interconnects included in adjacent interconnect groups in the same direction and between linear interconnects included in intersecting interconnect groups. It is easily understood that interconnection can be provided between arbitrary chip regions by providing contact holes in each of the chip regions.

[1 Effect of the Invention] According to the present invention, most of the masks for forming interconnections between chip areas in a wafer-scale integrated circuit are designed as standard patterns, and a dedicated mask for each wafer is provided in the interlayer insulating layer. Since only a mask is used for forming contact holes, the number of man-hours for designing, manufacturing and inspecting the mask can be significantly reduced.

In addition, there is no need for processes such as connecting or disconnecting wires for one interconnection, and mutual interconnections can be performed using the same process as ordinary interconnection and interconnection connections, improving the characteristics and reliability of interconnections. It has the effect of improving

Furthermore, it is possible to handle the wiring pattern in the integrated circuit block formed in the chip area including the interconnection pattern between the chip areas. Since interconnections can be formed between the wafer-scale integrated circuits, no special skill or special equipment is required, and the manufacturing cost of wafer-scale integrated circuits can be improved economically.

[Brief explanation of the drawing]

FIGS. 1(a) to C1 are diagrams for explaining the structure of a standardized wiring pattern according to the present invention. FIG. 2 is a plan view showing an example of mutual wiring between chi-knob regions. 3(a) and 3(b) are an enlarged sectional view and a plan view for explaining the specific spatial structure of the connection point shown in FIG. is a pad. 4 and 5 are wiring groups. 6 and 7 are cotton-like wiring. 8 is an interlayer insulating layer. 9 is a pad wiring. 10 is an insulating layer. 11 and 12 are contact holes. 17th Concubine A The 3rd area of the main government of the great place

Claims (1)

[Scope of Claims] 1) A plurality of chip regions arranged on a semiconductor wafer at a predetermined pitch in the row and column directions, each of which is defined by edges parallel to the row or column direction, and each of the chip regions. a plurality of wiring groups arranged on the wafer outside the plurality of chip areas, each of the wiring groups being arranged near the edge of the wafer at a predetermined pitch; The linear wirings include a plurality of linear wirings extending parallel to the edge, each of the linear wirings having a length approximately equal to the arrangement pitch of the chip area in each extending direction, and the linear wirings extending in the same direction. Each of the wiring groups adjacent in the row and column directions is formed from different wiring layers separated from each other by an interlayer insulating layer, and each of the linear wirings included in one wiring group is adjacent in the same row or column. One end of the linear wiring included in the wiring group has an end that overlaps with the interlayer insulating layer interposed therebetween, and an opening is provided in the interlayer insulating layer between the predetermined end parts, so that the interlayer insulating layer overlaps with one end of the linear wiring included in the wiring group. The overlapping ends are connected to each other through the opening, and the mutual positions of the ends in each wiring group are determined by the arrangement pitch of the pads in the extending direction of the linear wiring or the chip area in the extending direction. The wire group including the linear wires in which a displacement of less than the minimum distance between the edge of the wire and the pad is allowed, and the mutual positional relationship of the end portions of each wire group extends in the same direction. a plurality of wiring groups that are the same for each chip area; and wiring lines formed to have a length extending from the pad in each chip area on the wafer outside the chip area and reaching the vicinity of the adjacent chip area. The wiring group formed between adjacent chip regions has an intersection that overlaps with the interlayer insulating layer or another interlayer insulating layer, and an opening is provided in the interlayer insulating layer at a predetermined intersection. A wafer-scale integrated circuit characterized in that the linear wiring included in the wiring group arranged between the adjacent chip regions and the pad wiring are mutually connected through the opening. wiring structure. 2) The wiring structure of a wafer-scale integrated circuit according to claim 1, wherein the pad wiring is formed from at least one wiring layer of the wiring layers forming the wiring group.