JPS6161700B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit having multiple layers of wiring layered with insulating layers in between, and particularly to an integrated circuit having logic circuit elements.

Each layer of wiring has a plurality of wirings for interconnecting logic circuit elements of the integrated circuit. These wirings are not provided at arbitrary positions within each layer, but at any of a plurality of predetermined positions for each layer. Integrated circuits are designed under the condition that there are virtual paths called wiring channels at these predetermined locations, and that wiring can be provided only on these paths. Typically, the wiring channels are parallel to each other and are regularly spaced, eg, equally spaced apart. For example, the first layer wiring is provided in some of a plurality of mutually parallel wiring channels extending laterally. On the other hand, the second layer wiring is provided in a plurality of mutually parallel wiring channels extending in the vertical direction. For example, when connecting a terminal of a first logic circuit element and a terminal of a second logic circuit element,
Terminals of the logic circuit element are provided on the first wiring channel of the first layer, and terminals of the second logic circuit element are provided on the second wiring channel of the first layer. 1st
connected to the terminals of the logic circuit elements of the first and first
Layer wiring is provided within the first channel. Similarly,
connected to the terminal of the second logic circuit element;
A first layer of wiring is provided within the second channel.

At the intersection of the first and second wiring channels and one wiring channel in the second layer, first and second through holes are provided in the insulating layer below the wiring channel in the second layer, and A second layer wiring is provided on the second layer wiring channel so as to be connected to the first and second wiring through the second through holes, respectively.

Thus, by providing wiring on appropriate wiring channels in the first and second layers, the elements of the integrated circuit can be interconnected.

However, in recent years, the degree of integration of integrated circuits has improved, and as a result, the number of logic circuit elements housed in one integrated circuit has increased.

If two layers of wiring are used as in the past, the number of wirings in each layer increases, which inevitably increases the size of the integrated circuit. In other words, the degree of integration decreases. In order to eliminate this problem, it is desirable to provide three or more layers of wiring. However, in this case, the following problem further arises.

Usually, wiring and insulating layers are alternately formed by vapor deposition, sputtering, etc. on a substrate on which a large number of circuit elements are formed. Therefore, a level difference occurs in the insulating layer due to the thickness of the underlying wiring, and this level difference may cause disconnection or short circuit in the wiring formed on the insulating layer. In order to reduce the effect of the level difference caused by the thickness of the underlying wiring, it is necessary to increase the thickness of the insulating layer or increase the width of the wiring and increase the spacing between the wirings, but the thickness of the insulating layer If the thickness is increased, the depth of the through hole for connecting wiring between adjacent wiring layers becomes large, making it easy for wire breakage to occur at the through hole portion. On the other hand, if the width of the wiring is increased and the interval between the wirings is increased, the wiring area becomes large, and even if the wiring density is increased by using three or more layers of wiring, it will not be useful for improving the degree of integration.

Furthermore, in the manufacture of integrated circuits, in order to inspect the manufactured integrated circuits, the insulator provided on the upper side of the wiring is peeled off, a probe is brought into contact with the wiring,
It may be desirable to observe changes in the signal on that wire. However, when three or more layers of wiring are provided, there is a risk that the first or second layer wiring cannot be contacted with a probe because of the third or higher layer wiring.

In addition, in this inspection, it may be desirable to use a microscope to observe whether the wiring is placed in the correct position or whether there is any breakage in the wiring. However, when three or more layers of wiring are provided, there is a risk that the wiring in the first or second layer cannot be seen because of the wiring in the third or higher layer.

Therefore, an object of the present invention is to reduce the level difference in the insulating layer caused by the wiring by providing the upper layer wiring so as to fill the level difference in the insulating layer caused by the lower layer wiring, thereby increasing the wiring density and increasing the integration density. An object of the present invention is to provide an integrated circuit with improved performance.

For this reason, in the present invention, three or more layers of wiring are provided,
The center positions of wirings in different layers that extend in the same direction are made to be different.

The present invention will be explained below with reference to Examples.

FIG. 1 shows the planar position of the center of the wiring channel in each layer when four layers of wiring are used. A solid line 101 shows the wiring channel for the first layer wiring, and a dotted line 102 shows the wiring channel for the second layer wiring. The dotted line 103 indicates the wiring channel of the third layer,
A double-dashed line 104 indicates a fourth layer wiring channel. Wiring channels 101 and 103, 102 and 1
04 run parallel to each other, and wiring channels 101 and 103 run perpendicular to 102 and 104, respectively. In the present invention, as shown in FIG. 1, wiring channels 101 and 103 and 102 and 104 running parallel to each other are arranged between a pair of adjacent wiring channels 101 of the first layer so that they do not overlap when viewed from above. One third layer wiring channel 103
runs, and one fourth layer wiring channel 1 runs between a pair of adjacent second layer wiring channels 102.
04 is set to run.

In particular, the third layer wiring channel 103 is provided between a pair of adjacent first layer wiring channels 101, and the fourth layer wiring channel 104 is provided between a pair of adjacent second layer wiring channels 102. ing.

FIG. 2 is a perspective view of an integrated circuit in which wiring is actually performed based on the embodiment shown in FIG.
04 are wiring channels 1 of the first to fourth layers, respectively.
01 to 104, and 710 is a semiconductor substrate. The centers of the wirings 701-704 are aligned with the wiring channels 101-104 in FIG. 1, respectively. In Figure 2, wiring 701-7
The insulator layer for insulating the 04 from each other is not shown for simplicity. 3 is a sectional view obtained by cutting the circuit of FIG. 2 along a plane including the center line of the wiring 702 and perpendicular to the substrate 710, and FIG. 4 is a cross-sectional view of the circuit of FIG. including;
7 is a cross-sectional view obtained by cutting along a plane perpendicular to a substrate 710. FIG. In these figures, 601-603
is the wiring 701 and 702, 702 and 703, 70
This is an insulating material layer for insulating each of 3 and 704 from each other. 604 is an insulating layer on the wiring 704. Reference numeral 605 indicates a through hole for connecting the wirings 701 and 702. Wiring 701-704
is formed of, for example, a metal such as aluminum, a metal compound, or a highly conductive semiconductor such as polysilicon. In addition, the insulating layer 601
-603 are formed of a transparent insulator such as sputtered silicon dioxide, polyimide resin, phosphor glass, or a combination thereof.

Wiring is performed using such multilayer wiring channels based on a known two-layer wiring technique as follows.

First-layer wiring 701 is provided at the positions of several first-layer wiring channels 101, an insulator layer 601 is laminated thereon, and second-layer wiring 701 is laminated thereon.
2 are provided at the positions of some of the second layer wiring channels 102, further, an insulator layer 602 is laminated thereon, and a third layer wiring 703 is placed on top of the insulating material layer 602. A fourth layer wiring 704 is provided at the position of some of the fourth layer wiring channels 104, and an insulating layer 603 is laminated on top of the insulating layer 603. 6
04 will be provided.

In this case, the wiring in the first layer is connected to the circuit element directly or through a through hole, and the wiring in the adjacent layer is interconnected through a through hole provided in an insulating layer between them. It can be done.

As can be seen from FIGS. 2 to 4, since there is no third layer wiring 703 on the first layer wiring 701, the insulator layers 601 to 603 on the first layer wiring 701
04 The third layer wiring 703 does not become an obstacle during peeling. Therefore, the signal on the wiring can be inspected by contacting the first layer wiring 701 with the probe. In addition, insulator layers 601 to 6
04 is made of a transparent material, and there is no third layer wiring 703 above the wiring 701, the first layer wiring 701 can be inspected with a microscope.

In addition to the above-mentioned ease of inspection, in this embodiment, the first layer wiring 701 extending in the same direction
The coupling capacitance between the wiring 703 and the third layer wiring 703 is extremely small because they do not overlap in the vertical direction. As a result, there is an effect that noise due to this coupling capacitance is small on the first layer wiring 701 and the third layer wiring 703.

As is clear from the above description, when the third layer wiring 703 is located between a pair of first layer wiring 701, in order to maximize the effect of the present invention, the first layer,
It is desirable that the sum of the widths w1 and w3 of the third layer wiring is equal to or less than the pitch p1 of the first layer wiring 701.
However, in reality, the present invention is effective even if this condition is not met.

The above also applies to the second layer wiring 702 and the fourth layer wiring 704.

Regarding the fourth layer wiring 704, furthermore,
The following can be said. If the third layer wiring 703 is above the first layer wiring 701, in the area where these two wirings and the fourth layer wiring 704 work, there is no space under the fourth layer wiring 704. , a first layer of wiring 701, insulator layers 601 and 602, a third layer of wiring 703, and an insulator layer 603.

On the other hand, in the vicinity of this intersection, below the fourth layer wiring 704 are the first, third wiring 701,
There is no layer 703, and three insulator layers 601 to 603 are stacked. As a result, in this intersecting portion and its vicinity, the fourth layer wiring 704
The height of will change by two layers. Such a large change in height has the disadvantage that the fourth layer wiring 704 is likely to be disconnected. In other words, in general, when there are multiple layers of wiring, if a wiring in a different layer that extends in the same direction crosses a wiring in another layer that extends in a direction perpendicular to this direction, the step of this last wiring will be It becomes large and wire breakage is likely to occur. However, according to the present invention, there is a third layer under the intersection of the fourth layer wiring 704 and the first layer wiring 701.
No layer wiring.

Therefore, as can be seen from FIG. 4, the level difference in the fourth layer wiring 704 is only one layer.
Therefore, when four layers of wiring are provided as in the present invention, there is an effect that disconnection in the fourth layer is less likely to occur.

FIG. 5 shows a second embodiment of the invention.

Due to restrictions in semiconductor manufacturing technology, the minimum width of upper-layer interconnects may have to be larger than that of lower-layer interconnects, and as a result, the interconnect pitches of upper-layer interconnects may also have to be larger. Therefore, in FIG. 2, each one of the upper layer wiring channels 103 and 104 is connected to the lower layer wiring channel 101.
and 102 channels.

In this way, by making the pitch of the upper layer wiring channel larger than that of the lower layer wiring channel, it is possible to overcome limitations in semiconductor manufacturing technology.

Next, a method of providing through holes for connecting wiring in different layers will be described in the case of FIG. 5.
It is easiest to provide a through hole at the intersection of wiring channels in which two wiring lines are respectively provided.

In FIG. 6a, wirings 311A and 311 provided in a pair of adjacent wiring channels 101 in the first layer are shown.
B are connected to two divided wirings 312A and 312B in the wiring channel 102 of the second layer, respectively, by through holes 301A and 301B provided at the intersections of these wiring channels. It is assumed that there is no need to provide a through hole at the intersection of the wiring channel 103 and the wiring channel 102 between the pair of wiring channels 101. Normally, it is desirable that the pitch of the wiring channels 101 be as small as possible so that as many first layer wirings as possible can be provided. Therefore, the wiring 311
It is desirable that the distance between A and 311B be as small as possible to the minimum pattern interval allowed to prevent short circuits between wirings.

In the case of FIG. 6a, the distance 321 between the wirings 312A and 312B must also be greater than this allowable minimum pattern spacing. If this distance 321 is equal to this allowable minimum pattern spacing, then the wiring 311A and 31
The distance between the wiring channels 101 and 1B need only be slightly larger than this allowable minimum pattern spacing, and therefore the pitch of the wiring channels 101 does not need to be particularly large. However, in this way, the wiring pattern 101
As shown in FIG. 6b, a through hole is provided at one intersection of the second layer wiring channel 102 and the first layer wiring channel 101, and then the same wiring channel 101 is It is not desirable to provide a through hole at the intersection of the third layer wiring channel 103 and the same wiring channel 102 located adjacent to the third layer. In FIG. 6b, the wiring 312A in the wiring channel 102 is connected to the wiring 312A in the wiring channel through the through hole 301.
A, and this wiring channel 101
The wiring 303 in the wiring channel 103 adjacent to is connected to the same wiring channel 10 by the through hole 302.
It is connected to another wiring 312B in 2. In this case, the distance 322 between wires 312A and 312B
is considerably smaller than the pitch of the wiring channel 101, and therefore must be less than the allowable minimum pattern spacing. Therefore, wiring connections as shown in FIG. 6b must be prohibited when the pitch of the wiring channels 101 is small. In other words,
When providing the through hole 302 at the intersection of the third layer wiring 303 and the second layer wiring 312B, the wiring 303
Check whether a through hole is provided at the intersection between the wiring channel 102 to which 12B belongs and the first layer wiring channel 101, which is adjacent to the upper intersection. For example, the provision of through holes at the above-mentioned intersection points should be prohibited. In other words, the ability to create through holes between upper-layer wiring is limited by the through-holes between lower-layer wiring.
When creating a through hole at the intersection of upper layer wiring channels, it is necessary to check whether there is a through hole at each intersection of adjacent lower layer channels, which complicates the computer processing for determining the wiring position. There is.

FIG. 7 shows an embodiment in which this problem is solved by limiting the locations where through holes are formed to the intersections of wiring channels in two adjacent layers. Here, a case is shown in which this intersection is aligned with the intersection (black circle 511) of the wiring channels 101 and 102 of the first and second layers, which allows the largest number of wiring channels to be selected in each of the vertical and horizontal directions.

Wiring 510 on first layer wiring channel 101
is the wiring 520 on the second layer wiring channel 102
These wiring channels can be connected to each other by through holes 501 provided at the intersections thereof. When connecting the wiring 530 on the wiring channel 103 of the third wiring layer, which is adjacent to the wiring channel 101 where the wiring 501 is provided, to the wiring 521 on the wiring channel 102 where the wiring 520 is provided, Intersection point 51 on wiring channel 102
1, a through hole 502 is provided at the intersection closest to the wiring channel 103 where the wiring 530 is to be provided, and a bent portion a that is guided by the through hole and has a direction perpendicular to the wiring channel 103 is provided in the wiring 530. As a result, the distance between the wires 520 and 521 on the same wiring channel 102 becomes approximately equal to the distance between the intersection points 511, which can be greater than the minimum allowable distance. Note that the bent portion a of the wiring 530 is formed at the same time as the rest of the wiring 530.
made from the same materials.

Note that the wiring 531 provided on the wiring channel 103 of the third layer and the wiring channel 10 of the fourth layer
When connecting the wiring 540 provided on 4,
A through hole is provided at one intersection 511 that is closest to any of these wiring channels.
Through hole 503 is an example of this through hole. The wiring 540 has a bent portion b that has a direction perpendicular to the wiring channel 104 and is guided to the through hole 503, and the wiring 531 has a bent part b that has a direction perpendicular to the wiring channel 103 and is led to the through hole 503. By providing the curved bent portion c, the wirings 531 and 540 can be connected to one intersection point 511.
The connection can be made through a through hole 503 provided in the.

Note that the bent portion b of the wiring 540 is
It is made at the same time and from the same material as the rest of 40. Further, the bent portion c of the wiring 531 is made at the same time as the rest of the wiring 513 and from the same material.

As described above, by providing the through hole at the intersection of the wiring channels of two adjacent layers, it is possible to create a through hole for the wiring in the upper layer without checking whether there is a through hole in the wiring in the lower layer. Computer processing for determining wiring becomes easier.

In the embodiment of FIG. 7, for example, if a wiring (not shown) is provided in the wiring channel 102 passing through an intersection with the through hole 503,
Although the change in height (level difference) of the wiring at the bent portion b becomes large, such a case rarely occurs, and therefore, overall, the probability of wire breakage occurring is low. Further, when a wiring is provided in the wiring channel 101, the capacitance between the wiring and the wiring 540 is small because these wirings are overlapped only at the bent portion b.

Furthermore, visual inspection or inspection using a probe of the wiring provided in this wiring channel 101 is only possible at the bent portions, and visual inspection or inspection is essentially possible.

Of course, if the fourth layer wiring is not used, the step difference at the bent portion or the coupling capacitance will be as small as any other wiring.

As described above, according to the present invention, it is possible to reduce the level difference in the insulating layer due to the lower layer wiring, so it is possible to reduce the level difference in the wiring due to the level difference without increasing the thickness of the insulating layer or increasing the width of the wiring and increasing the wiring spacing. It has the great advantage of being able to prevent wire breaks, increasing the wiring density and the degree of integration, and since there is no need to increase the thickness of the insulating layer, wire breaks at through holes are less likely to occur.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a four-layer wiring channel arrangement according to the present invention, and FIG. 2 is a perspective view of an integrated circuit having four layers of wiring provided according to the wiring channel arrangement of FIG. 1. , FIG. 3 is a cross-sectional view taken along a plane passing through the center of the second layer wiring of the integrated circuit in FIG. 2, and FIG. 4 is a cross-sectional view taken through the center of the fourth layer wiring of the integrated circuit in FIG. A cross-sectional view when cut along a plane passing through,
FIG. 5 is a diagram showing another arrangement of four-layer wiring channels according to the present invention, FIGS. 6a and 6b are diagrams showing how to provide through holes for interlayer connections in an integrated circuit according to the present invention, FIG. 7 is a diagram showing another way of providing through holes in the integrated circuit according to the present invention. 101...First layer wiring channel, 102...
2nd layer wiring channel, 103...3rd layer wiring channel, 104...4th layer wiring channel, 3
11A, 311B, 510...first layer wiring, 3
12,312B,520,521...2nd layer wiring, 303,530,531...3rd layer wiring,
540...4th layer wiring.

Claims (1)

[Scope of Claims] 1. A multi-layer wiring provided on a semiconductor substrate on which a large number of circuit elements are formed, and in which three or more layers are laminated with an insulating layer interposed between them to connect the circuit elements, Each layer has a plurality of wirings, and the plurality of wirings in each layer are provided at some of the plurality of wiring positions that are predetermined for each layer and arranged regularly and parallel to each other. Among the wirings, a plurality of wirings in the first layer and the third layer extend in the first direction,
The second layer wiring extends in a second direction perpendicular to the first direction, and the center position of each of the third layer wiring is
An integrated circuit having multilayer wiring, characterized in that the third layer wiring is offset from the center position of the first layer wiring and is provided to fill a step in an insulating layer caused by the first layer wiring. 2. The integrated circuit of item 1, wherein the insulating layer is made of a transparent insulator. 3. The integrated circuit according to item 1 or 2, wherein the spacing between the wirings in the third layer is larger than the spacing between the wirings in the first layer. 4 Among the plurality of wiring layers, the plurality of wirings in the fourth layer extend in the second direction, and the center thereof is located at a position offset from the center position of the wiring in the second layer. or the integrated circuit of item 2 or item 3. 5. The integrated circuit according to item 4, wherein the spacing between the wirings in the fourth layer is larger than the spacing between the wirings in the second layer. 6 Through-holes for connecting two wirings belonging to two adjacent layers shall be provided only at the intersection of the wiring channels in which the two wirings are respectively provided. Any one integrated circuit. 7 Through-holes for connecting two wirings belonging to two adjacent layers shall be any one of paragraphs 1 to 5 provided only at predetermined intersection points of wiring channels of a pair of adjacent layers. or one integrated circuit.